NXP Semiconductors TFA9812 User Manual

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

Rev. 02 — 22 January 2009 Preliminary data sheet

1. General description

The TFA9812 is a high-efﬁciency Bridge Tied Load (BTL) stereo Class-D audio ampliﬁer with a digital I2S audio input. It is available in a HVQFN48 package with exposed die paddle. The exposed die paddle technology enhances the thermal and electrical performances of the device.

The TFA9812 features digital sound processing and audio powerampliﬁcation.Itsupports I2C control mode and Legacy mode. In Legacy mode I2C involvement is not needed because the key features are controlled by hardware pin connections.

2. Features

2.1 General features

A continuous time output power of 2 × 12W(RL=8Ω,V an external heat sink. Due to the implementation of a programmable thermal foldback even for high supply voltages, higher ambient temperatures, and/or lower load impedances, the device operates without sound interrupting behavior.

TFA9812 is designed in such a way that it starts up easily (no special power-up sequence required). It features various soft and hard impact protection mechanisms to ensure an application that is both user friendly and robust.

A modulation technique is applied for the TFA9812, which supports common mode choke approach (1 common mode choke only per BTL ampliﬁer stage). This minimizes the number of external components.

n 3.3 V and 8 V to 20 V external power supply n High efﬁciency and low power dissipation n Speaker outputs fully short circuit proof across load, to supply lines and ground n Pop noise free at power-up/power-down and sample rate switching n Low power Sleep mode n Overvoltage and undervoltage protection on the 8 V to 20 V power supply n Undervoltage protection on the 3.3 V power supply n Overcurrent protection (no audible interruptions) n Overdissipation protection n Thermally protected and programmable thermal foldback n Clock error protection n I2C mode control or Legacy mode (i.e. no I2C) control n Four different I2C addresses supported n Internal Phase-Locked Loop (PLL) without using external components

= 15 V) is supported without

DDP

NXP Semiconductors

n No high system clock required (PLL is able to lock on BCK) n No external heat sink required n 5 V tolerant digital inputs n Supports dual coil inductor application n Easy application and limited external components required

2.2 DSP features

n Digital parametric 10-band equalizer n Digital volume control per channel n Selectable +24 dB gain boost n Analog interface to digital volume control in Legacy mode n Digital clip level control n Soft and hard mute n Thermal foldback threshold temperature control n De-emphasis n Output power limiting control n Polarity switch n Four Pulse Width Modulation (PWM) switching frequency settings

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

2.3 Audio data input interface format support

n Master or slave Master Clock (MCLK), Bit Clock (BCK) and Word Select (WS) signals n Philips I2S, standard I2S n Japanese I2S, Most Signiﬁcant Bit (MSB) justiﬁed n Sony I2S, Least Signiﬁcant Bit (LSB) justiﬁed n Sample rates from 8 kHz to 192 kHz

3. Applications

n Digital-in Class-D audio ampliﬁer applications n CRT and ﬂat-panel television sets n Flat-panel monitors n Multimedia systems n Wireless speakers n Docking stations for MP3 players

Preliminary data sheet Rev. 02 — 22 January 2009 2 of 66

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4. Quick reference data

Table 1. Quick reference table

Unless speciﬁed otherwise, V V

SS1=VSS2

24-bit I

Symbol Parameter Conditions Min Typ Max Unit

General

DDA

DDP

DDA(3V3)

DDD(3V3)

DDA(3V3)

DDD(3V3)

o(RMS)

= REFD = REFA = 0 V, T

S input data, MCLK clock mode, typical application diagram (Figure 13).

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

DDA=VDDP

=12V,V =25°C, RL=8Ω,fi= 1 kHz, fs= 44.1 kHz, fsw= 400 kHz,

amb

SSP1=VSSP2

analog supply voltage

power supply voltage

analog supply voltage (3.3 V)

digital supply voltage (3.3 V)

supply current soft mute mode, withload,

ﬁlter and snubbers connected

sleep mode

analog supply current (3.3 V)

operating mode

S slave mode - 2 4 mA

S master mode - 4 6 mA

sleep mode

= 12 V - 120 - µA = 1 V - 40 70 µA

digital supply current (3.3 V)

DDA=VDDP

operating mode

S slave mode - 15 25 mA

S master mode - 25 40 mA

sleep mode; DATA = WS = BCK = MCLK = 0 V

RMS output power Continuous time output power per channel; THD = 10 %;

=8Ω

= V

DDA

= V

DDA

= V

DDA

= 12 V - 8.3 - W

DDP

= 13.5 V - 10 - W

DDP

= 15 V - 12 - W

DDP

Short time (≤ 10 s) output power per channel; THD = 10 %;

=8Ω

output power

= V

DDA

RL=8Ω; P

= 17 V - 15 - W

DDP

= 8.3 W - 88 - %

o(RMS)

efﬁciency

=0V,V

DDA(3V3)=VDDD(3V3)

81220V

3.0 3.3 3.6 V

[1]

-3845mA

[1]

- 160 270 µA

-430µA

= 3.3 V,

[1] IPis thecurrent through theanalog supply voltage(V

voltage (V

Preliminary data sheet Rev. 02 — 22 January 2009 3 of 66

DDP

) pin.

) pin added to the current through the power supply

DDA

NXP Semiconductors

BTL stereo Class-D audio ampliﬁer with I2S input

5. Ordering information

Table 2. Ordering information

Type number Package

Name Description Version

TFA9812HN HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads;

48 terminals; body 7 × 7 × 0.85 mm

TFA9812

SOT619-8

Preliminary data sheet Rev. 02 — 22 January 2009 4 of 66

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Preliminary data sheet Rev. 02 — 22 January 2009 5 of 66

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6. Block diagram

NXP Semiconductors

TEST1 TEST2 AVOL V

743 32 40 36

PHASED LOCKED

LOOP

XTALIN

OSCILLATOR

MCLK

BCK

DATA

GAIN

CSEL

SDA/MS

46 45 44

INTERFACE

31 33ENABLE 34 35 36 37 38 39

SERIAL

AUDIO

CONTROL

INTERFACE

PARAMETRIC

EQUALIZER

XTALOUT

POWERUP

ADSEL2/PLIM2 ADSEL1/PLIM1

SCL/SFOR

Fig 1. TFA9812 block diagram

CLOCK

PROTECTION

LP UFP OFP

IBP

10-BAND

PROTECTION

OVP UVP OCP OTP ODP

ADDRESS

HEX 01

VOLUME

CONTROL

AND SOFT

MUTE

CDELAYDIAG

DDD(3V3)VDDA(3V3)VDDA

ADC

CSEL

THERMAL

FOLDBACK

INTER-

POLATION

FILTER AND

DE-EMPHASIS

STABD REFD STABA REFA

GAIN

REFERENCES

TFA9812

POWER LIMITER

PWM

CONTROLLER

PWM

CONTROLLER

EXPOSED DIE PADDLE V

CONTROL

LOGIC

CONTROL

LOGIC

CONTROL

LOGIC

CONTROL

LOGIC

DRIVER

HIGH

DRIVER

LOW

DRIVER

HIGH

DRIVER

LOW

DRIVER

HIGH

DRIVER

LOW

DRIVER

HIGH

DRIVER

LOW

SS1VSS2

STAB1

STAB2

488

18, 19

16, 17

10, 11

DDP

23, 24

26, 27

DDP

20, 21

SSP2

DDP

13, 14

SSP2

28 22

BOOT1P V

DDP

OUT1P

SSP2

BOOT1N

OUT1N

SSP1

STAB1 BOOT2P

OUT2P

BOOT2N

OUT2N

STAB2

010aaa217

BTL stereo Class-D audio ampliﬁer with I

TFA9812

S input

NXP Semiconductors

Figure 1 shows the block diagram of the TFA9812. For a detailed description of the audio

signal path see Section 8.1.

7. Pinning information

7.1 Pinning

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

terminal 1

index area

XTALIN ADSEL2/PLIM2 XTALOUT CSEL V

DDA(3V3)

STABA ENABLE

REFA AVOL

DDA

TEST1 CDELAY

SS1

STAB2 STAB1

SSP2

BOOT2N

SS2

MCLK

BCKWSDATA

4847464544434241403938 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28

10 27 11 26 12 25

1314151617181920212223

OUT2N

BOOT1P

TEST2

TFA9812HN

DDPVDDP

OUT2P

OUT1P

Transparent top view

REFD

DDD(3V3)

STABD

OUT1P

SDA/MS

SCL/SFOR

OUT1N

BOOT1P

ADSEL1/PLIM1 37

OUT1N

GAIN

POWERUP

DIAG

SSP1

BOOT1N

010aaa218

Fig 2. Pin conﬁguration, transparent top view

Table 3. Pinning description TFA9812

Pin Symbol Type Description

1 XTALIN I Crystal oscillator input 2 XTALOUT O Crystal oscillator output 3V

DDA(3V3)

P Analog supply voltage (3.3 V) 4 STABA O 1.8 V analog stabilizer output 5 REFA P Analog reference voltage 6V

DDA

P Analog supply voltage (8 V to 20 V) 7 TEST1 I Test signal input 1. For test purposes only (connect to V 8V

SS1

P PCB ground reference 9 STAB2 O Decoupling of internal 11 V regulator for channel 2 drivers 10 V 11 V

SSP2 SSP2

P Negative power supply voltage for channel 1 and channel 2

P Negative power supply voltage for channel 1 and channel 2 12 BOOT2N O Bootstrap high-side driver negative PWM output channel 2 13 OUT2N O Negative PWM output channel 2

)

Preliminary data sheet Rev. 02 — 22 January 2009 6 of 66

NXP Semiconductors

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

Table 3. Pinning description TFA9812

…continued

Pin Symbol Type Description

14 OUT2N O Negative PWM output channel 2 15 BOOT1P O Bootstrap high-side driver positive PWM output channel 1 16 OUT1P O Positive PWM output channel 1 17 OUT1P O Positive PWM output channel 1 18 V 19 V

DDP DDP

P Positive power supply voltage (8 V to 20 V)

P Positive power supply voltage (8 V to 20 V) 20 OUT2P O Positive PWM output channel 2 21 OUT2P O Positive PWM output channel 2 22 BOOT2P O Bootstrap high-side driver positive PWM output channel 2 23 OUT1N O Negative PWM output channel 1 24 OUT1N O Negative PWM output channel 1 25 BOOT1N O Bootstrap high-side driver negative PWM output channel 1 26 V 27 V

SSP1 SSP1

P Negative power supply voltage for channel 1 and channel 2

P Negative power supply voltage for channel 1 and channel 2 28 STAB1 O Decoupling of internal 11 V regulator for channel 1 drivers 29 DIAG O Fault mode indication output (open-drain pin) 30 CDELAY I Timing reference 31 POWERUP I Power-up pin to switch betweenSleep and other operational

modes 32 AVOL I Analog volume control (Legacy mode) 33 ENABLE I Enable input to switch between 3-state and other

operational modes 34 GAIN I Gain selection input to select between 0 dB and +24 dB

gain (Legacy mode) 35 CSEL I Control selection input to select between Legacy mode

C bus control) and I2C bus control

(no I

36 ADSEL2/PLIM2 I Address selection in I

C mode input 2, power limiter

selection input 2 in Legacy mode

37 ADSEL1/PLIM1 I Address selection in I

C mode input 1, power limiter

selection input 1 in Legacy mode

38 SCL/SFOR I I

C bus clock input in I2C mode, I2S serial data format

selection input in Legacy mode

39 SDA/MS I/O I

C bus data input and output in I2C mode, master/slave

selection input in Legacy mode 40 V

DDD(3V3)

P Digital supply voltage (3.3 V) 41 STABD O 1.8 V digital stabilizer output 42 REFD P Digital reference voltage 43 TEST2 I Test signal input 2; for test purposes only (connect to V

44 DATA I I 45 WS I/O I

S bus data input

S bus word select input (I2S slave mode) or output (I2S

master mode)

46 BCK I/O I

S bus bit clock input (I2S slave mode) or output (I2S

master mode)

)

Preliminary data sheet Rev. 02 — 22 January 2009 7 of 66

NXP Semiconductors

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

Table 3. Pinning description TFA9812

Pin Symbol Type Description

47 MCLK I/O Master clock input (I2S slave mode) or output (I2S master

48 V Exposed

die-paddle

SS2

- P PCB ground reference

8. Functional description

8.1 General

The TFA9812 is a high-efﬁciency stereo BTL Class-D ampliﬁer with a digital I2S audio input. It supports all commonly used I2S formats.

Figure 1 shows the functional block diagram, which includes the key function blocks of the

TFA9812. In the digital domain the audio signal is processed and converted to a pulse width modulated signal using BD modulation. A BTL conﬁgured power comparator carries out power ampliﬁcation.

The audio signal processing path is as follows:

1. The Digital Audio Input (DAI) block translates the I2S (-like) input signal into a standard internal stereo audio stream.

2. The 10-band parametric equalizer can optionally equalize the stereo audio stream. Both channels have separate equalization streams. It can be used forspeaker transfer curve compensation to optimize the audio performance of applied speakers.

3. Volume control in the TFA9812 is done by attenuation. The attenuation depends on the volume control settings and the thermal foldbackvalue. Soft mute is also arranged at this part. In Legacy mode the volume control is done by an on-board Analog-to-Digital Converter (ADC) which measures the analog voltage on pin 32.

4. The interpolation ﬁlter interpolates from 1 fs to the PWM controller sample rate (2048 fs at 44.1 kHz) by cascading FIR ﬁlters.

5. The gain block can boost the signal with 0 dB or +24 dB. Four speciﬁc gain settings are also provided in this block. These speciﬁc gain settings are related to maximum clip levels of < 0.5 %, 10 %, 20 % or 30 % THD at the TFA9812 output. These maximum clip levels are only valid with the gain boost set to 0 dB and a 0 dBFS input signal.

6. The power limiter limits the maximum output signal of the TFA9812. The power limiter settings are 0 dB, −1.5 dB, −3 dB, and −4.5 dB. This function can be used to reduce the maximum output power delivered to the speakers at a ﬁxed supply voltage and speaker impedance.

7. The PWM controller block transforms the audio signal into a BD-modulated PWM signal. The BD-modulation provides a high signal-to-noise performance and eliminates clock jitter noise.

8. Via four differential comparators the PWM signals are ampliﬁed by two BTL power output stages. By default the left audio signal is connected to channel 1 and the right audio signal to channel 2.

…continued

mode)

P PCB ground reference

Preliminary data sheet Rev. 02 — 22 January 2009 8 of 66

NXP Semiconductors

The block control deﬁnes the operational control settings of the TFA9812 in line with the actual I2C settings and the pin-controlled settings.

The PLL block creates the system clock and can take the I2S BCK, the MCLK or an external crystal as reference source.

The following protections are built into the TFA9812:

• Thermal Foldback (TF)

• OverTemperature Protection (OTP)

• OverCurrent Protection (OCP)

• OverVoltage Protection (OVP)

• UnderVoltage Protection (UVP)

• Window Protection (WP)

• Lock Protection (LP)

• UnderFrequency Protection (UFP)

• OverFrequency Protection (OFP)

• Invalid BCK Protection (IBP)

• DC-blocking

• ElectroStatic Discharge (ESD)

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

8.2 Functional modes

8.2.1 Control modes

The two control modes of the TFA9812 are I2C and legacy.

• In I

C mode the I2C format control is enabled.

• In Legacy mode a pin-based subset of the control options is available. The control

settings for features which are not available in Legacy mode are set to the default I2C register settings.

The control mode is selected via pin CSEL as shown in Table 4.

Table 4. Control mode selection

CSEL Pin value Control mode

0 Legacy (no I

In the functional descriptions below the control for the various functions will be described for each control mode. Section 9.6 summarizes the support given by each control mode for the various TFA9812 functions.

8.2.2 Key operating modes

There are six key operating modes:

• InSleep mode the voltage supplies are present, but power consumption for the whole

device is reduced to the minimum level. The output stages in Sleep mode are 3-state and I2C communication is disabled.

Preliminary data sheet Rev. 02 — 22 January 2009 9 of 66

NXP Semiconductors

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

• In Soft mute mode the I

S input signal is overruled with a soft mute.

– In Legacy control mode the analog input pin AVOL controls Soft mute mode. – In I2C control mode I2C control can be used to enable an automatic soft mute

function. See also Section 8.5.3.

• In Hard mute mode the PWM controller is overruled with a 50 % duty cycle square

pulse. The Hard mute mode is only available in I2C control mode.

• In Operating mode the TFA9812 ampliﬁes the I

S audio input signal in line with the

actual control setting.

• In 3-state mode the output stages are switched off.

• Fault mode is entered when a fault condition is detected by one or more of the

protection mechanisms implemented in the TFA9812. In Fault mode the actual device conﬁguration depends on the fault detected: see Section 8.7 for more information. Fault mode is for a subset of the faults ﬂagged on the DIAG output pin. When the DIAG pin is ﬂagged the output stages will be forced to enter 3-state mode. In Sleep mode the DIAG pin will not ﬂag fault modes.

Table 5. Operational mode selection

Pin: DIAG Output Operational mode

selected:

POWERUP ENABLE CSEL AVOL

0 - - - ﬂoating Sleep mode 1 - - - 0 / ﬂoating Fault mode (enabled by

system)

1 1 1 - ﬂoating Soft mute mode (in I2C

control mode)

1 1 0 < 0.8 V ﬂoating Soft mute (in Legacy control

mode) 1 0 - - ﬂoating 3-state mode 1 1 - - ﬂoating Operational mode

[1]

[2]

[1] Clocking faults do not trigger DIAG output. [2] Under these conditions soft mute still has to be enabled by the appropriate I2C setting.

8.2.3 I2S master/slave modes and MCLK/BCK clock modes

The I2S interface can be set in master or in slave.

• In I

S master mode the PLL locks to the output signal of the internal crystal oscillator

circuit which uses an external crystal. The BCK, WS and MCLK signals are generated by the TFA9812. On the MCLK pin the TFA9812 delivers a master clock running at the crystal frequency.

• In I

S slave mode the PLL can lock to: – The external MCLK signal on the MCLK pin called MCLK clock mode. – The I2S input BCK signal on the BCK pin called BCK clock mode.

The I2S master or slave mode can be selected:

• In I

C control mode by selecting the right I2C setting.

• In legacy control mode by selecting the right setting on the SDA/MS pin.

Preliminary data sheet Rev. 02 — 22 January 2009 10 of 66

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Table 6. I2S master/slave mode selection

Pin value Clock mode I2S mode CSEL SDA/MS

0 0 legacy slave 0 1 legacy master 1- I

[1] Under these conditions the mode is enabled by the appropriate I2C setting.

In I2S slave mode selection between BCK and MCLK clock modes is automatic. MCLK clock mode is given higher priority than BCK. If the MCLK clock is judged valid by

the protection circuit then MCLK clock mode is enabled. BCK clock mode is enabled when the MCLK clock is invalid (e.g. not available) and the BCK clock is judged valid by the protection circuit (see Section 8.7.11).

Table 7 shows the supported crystal frequencies in I2S master mode. Table 8 shows the supported MCLK frequencies in MCLK mode (I2S slave mode).

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

C slave or master

[1]

Table 9 shows the supported BCK frequencies in BCK mode (I2S slave mode).

Table 7. Valid crystal frequencies in I2S master mode

Control mode fs (kHz) Crystal frequency (MHz)

C 8, 16, 32, 64, 128 8.192

11.025, 22.05, 44.1, 88.2,

176.4 12, 24, 48, 96, 192 12.288

Legacy 32 8.192

44.1 11.2896 48 12.288

Table 8. Valid MCLK frequencies in I

S slave mode

Control mode fs (kHz) MLCK frequency (MHz)

C 8, 16, 32, 64, 128 8.192

32 18.432 (576 f

11.025, 22.05, 44.1, 88.2,

176.4

44.1 25.4016 (576 f 12, 24, 48, 96, 192 12.288

48 27.648 (576 f

11.2896

12.288

11.2896

16.9344

18.432

)

Preliminary data sheet Rev. 02 — 22 January 2009 11 of 66

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Table 8. Valid MCLK frequencies in I2S slave mode

Control mode fs (kHz) MLCK frequency (MHz)

Legacy 32 8.192

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

12.288

18.432 (576 f

44.1 11.2896

16.9344

25.4016 (576 f

48 12.288

18.432

27.648 (576 f

)

Table 9. Valid BCK frequencies in I

S slave mode

Control mode fs (kHz) BCK (x fs input)

C 8 to 192

8 to 192 8 to 192

Legacy 32, 44.1, 48 32 f

32, 44.1, 48 48 f 32, 44.1, 48 64 f

[1] The valid sample frequencies are shown in Section 9.5.7.

[1] [1] [1]

32 f 48 f 64 f

s s s s s s

Preliminary data sheet Rev. 02 — 22 January 2009 12 of 66

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8.3 Power-up/power-down

external

voltage

supplies

POWERUP

ENABLE

available

soft mute

setting in

C mode

I AVOL pin

in Legacy

mode

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

PWM

outputs

Operating

mode active

Fig 3. Power-up/power-down timing

8.3.1 Power-up

Figure 3 and Table 10 describe the power-up timing while Table 11 shows the pin control

for initiating a power-up reset.

Table 10. Power-up/power-down timing

Symbol Parameter Conditions Min Typ Max Unit

wake

d(on)

d(mute_off)

d(soft_mute)

wake-up time

turn-on delay time

mute off delay time

Soft mute delay time

wake

d(on)

d(mute_off)

d(soft_mute)

I2C control - 4 - ms

- 70 - 135 ms

- - - 128/f

I2C control - - 128/f legacy

control

-15-ms

[1]

010aaa219

[1] Mute in Legacy mode is controlled by AVOL pin.

Preliminary data sheet Rev. 02 — 22 January 2009 13 of 66

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In I2C control mode communication is enabled after 4 ms. The preferred I2C settings can be made within 66 ms before the PLL starts running. Finally, the output stages are enabled and the audio level is increased via a demute sequence if mute has previously been disabled.

Remark: In I2C mode soft mute is enabled by default. It can be disabled at any time while I2C communication is valid. In order to prevent audio clicks volume control (default setting is 0 dB) should be set before soft mute is disabled.

Remark: For a proper start-up in I2S master mode and I2C mode the following sequence should be followed:

1. The I2S master setting should be set and keep the default sample rate setting active.

2. Next, another sample rate setting than the default one should be selected.

3. Finally, when the default sample rate is used the default sample rate setting should be

8.3.2 Power-down

Figure 3 includes the power-down timing while Table 11 shows the pin control for enabling

power-down.

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

selected again.

Table 11. Power-up/power-down selection

Power-up pin value

0 Power-down (Sleep mode) 1 Power-up

Description

Putting the TFA9812 into power-down is equivalent to enabling Sleep mode (see Section 8.2.2). This mode is entered immediately and no additional clock cycles are required.

In order to prevent audible clicks, soft mute should be enabled at least T

d(soft_mute)

seconds before enabling Sleep mode. The speciﬁed low current and power conditions in Table 1 are valid within 10 µs after

enabling Sleep mode.

8.4 Digital audio data input

8.4.1 Digital audio data format support

The TFA9812 supports a commonly used range of I2S and I2S-like digital audio data input formats. These are listed in Table 12.

Table 12. Supported digital audio data formats

BCK frequency Interface format (MSB ﬁrst) Supported in I2C

control mode

32 f

48 f

Preliminary data sheet Rev. 02 — 22 January 2009 14 of 66

I2S up to 16-bit data yes yes MSB-justiﬁed 16-bit data yes yes LSB-justiﬁed 16-bit data yes yes I2S up to 24-bit data yes yes MSB-justiﬁed up to 24-bit data yes yes

Supported in Legacy control mode

NXP Semiconductors

Table 12. Supported digital audio data formats

BCK frequency Interface format (MSB ﬁrst) Supported in I2C

48 f 48 f 48 f 48 f 64 f 64 f 64 f 64 f 64 f 64 f

Remark: Only MSB-ﬁrst formats are supported.

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

Supported in Legacy

control mode

s s s s s s s s s s

LSB-justiﬁed 16-bit data yes no LSB-justiﬁed 18-bit data yes no LSB-justiﬁed 20-bit data yes no LSB-justiﬁed 24-bit data yes yes I2S up to 24-bit data yes yes MSB-justiﬁed up to 24-bit data yes yes LSB-justiﬁed 16-bit data yes no LSB-justiﬁed 18-bit data yes no LSB-justiﬁed 20-bit data yes no LSB-justiﬁed 24-bit data yes no

control mode

LEFT

MSB-JUSTIFIED FORMAT

LEFT

MSB B2 B3 B4 B5 B6

LEFT

BCK

DATA

BCK

DATA

BCK

DATA

BCK

DATA

BCK

DATA

BCK

MSB B2

MSB B2 MSBLSB LSB MSB B2B2

2112 3

MSB MSBB2

S-BUS FORMAT

MSB B2 B3 B4

RIGHT

321321

15 2 1

MSB

1518 17 2 1

1518 1720 19 2 1

1518 1720 1922 212324 2 1

B15

LSB

LSB-JUSTIFIED FORMAT 16 BITS

B17

LSB

LSB-JUSTIFIED FORMAT 18 BITS

B19

LSB

LSB-JUSTIFIED FORMAT 20 BITS

RIGHT

MSB B2

RIGHT

16 1518 17 2 1

MSB B2 B3 B4

RIGHT

MSB B2 B3 B4 B5 B6

RIGHT

15 2 1

B15 LSB

B17 LSB

1518 1720 19 2 1

B19 LSB

1518 1720 1922 212324 2 1

DATA

MSB

B5 B6 B7 B8 B9 B10

B3 B4

B23

LSB

LSB-JUSTIFIED FORMAT 24 BITS

MSB

B5 B6 B7 B8 B9 B10

B3 B4

B23 LSB

010aaa458

Fig 4. Serial interface input and output formats

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NXP Semiconductors

In I2C control mode the following sample frequency fs can be used: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz or 192 kHz. The I2C control for fs selection can be found in

Section 9.5.7.

In Legacy control mode the following sample frequencies (fs) can be used: 32 kHz,

44.1 kHz or 48 kHz.

8.4.2 Digital audio data format control

The BCK-to-WS and MCLK-to-WS frequency ratios are automatically detected, so no control settings need to be conﬁgured for these.

In I2C control mode all the formats listed in Table 12 are supported. The appropriate I2C controls for selecting the supported formats can be found in Section 9. In the Legacy control mode only a subset of the supported formats can be used. These are shown in

Table 12 and the required pin control is given in Table 13.

See Section 8.2.1 for details of how to enable Legacy control mode.

Table 13. Digital audio data format selection in Legacy control mode

SCL/SFOR pin value Interface formats (MSB-ﬁrst)

0I 1 MSB-justiﬁed

TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

8.5 Digital signal-processing features

8.5.1 Equalizer

8.5.1.1 Equalizer options

The equalizer function can be bypassed and the equalizer can be conﬁgured to either a 5-band or 10-band function. These settings are for both audio channels simultaneously.

There are 20 bands in the equalizer. These are distributed as follows:

• Bands A1 to A5 are bands 1 to 5 of output 1 (used in 5-band and 10-band

conﬁguration).

• Bands B1 to B5 are bands 1 to 5 of output 2 (used in 5-band and 10-band

conﬁguration).

• Bands C1 to C5 are bands 6 to 10 of output 1 (used in 10-band conﬁguration only).

• Bands D1 to D5 are bands 6 to 10 of output 2 (used in 10-band conﬁguration only).

In I2C control mode each band can be conﬁgured separately using I2C register settings. In Legacy control mode the equalizer is bypassed.

8.5.1.2 Equalizer band function

The shape of each parametric equalizer band is determined by the three ﬁlter parameters:

• (Relative) center frequency .

ω 2π fcfs⁄()=

• Quality factor Q.

• Gain factor G.

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In the above equation fcis the center frequency and fs is the sample frequency. The deﬁnition of the quality factor is the center frequency divided by the 3 dB bandwidth,

see Equation 1. In parametric equalizers this is only valid when the gain is set very small (−30 dB).

Each band ﬁlter can be programmed to perform a band-suppression (G < 1) or a band-ampliﬁcation (G > 1) function around the center frequency.

Each band of the TFA9812 equalizer has a second-order Regalia-Mitra all-pass ﬁlter structure. The structure is shown in Figure 5.

-----------------

f2f1–

f1: 20

f2: 20

BTL stereo Class-D audio ampliﬁer with I2S input



log 3dB fcf1>=

--------







log 3dB f2fc>,=

--------





TFA9812

(1)

X(z)

A(z)

Fig 5. Regalia ﬁlter ﬂow-diagram

−

K0/2

Y(z)

010aaa406

The transfer function of this all-pass ﬁlter is shown in Equation 2:

Hz() 12⁄ 1Az()+()K02⁄ 1Az()–()⋅+⋅=

A(z) is the second-order ﬁlter structure. The transfer function of A(z) is shown in

Equation 3:

Az()

K1K21K

-------------------------------------------------------------------------------- -

1K21K

+()Z1–Z2–+⋅⋅+

+()Z1–K1Z2–⋅+⋅⋅+

The relationship between the programmable parameters K0, K1, and K2 and the ﬁlter parameters G, ω, Q is shown in Equation 4 and Equation 5.

(2)

(3)

Use Equation 4 to calculate band suppression (G < 1) functions.

2Q G ωsin–⋅()2Q G ωsin+⋅()⁄=

ωcos–=

G1<

(4)

Use Equation 5 to calculate band ampliﬁcation (G ≥ 1) functions.

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TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

K0G=

2Q ωsin–()2Q ωsin+()⁄=

ωcos–=

G1≥

The ranges of the TFA9812 parametric equalizer settings for each band are:

• The Gain, G is from −30 dB to +12 dB.

• The center frequency, f

is from 0.0004 * fs to 0.49 * fs.

• The quality factor Q is from 0.001 to 8.

Using I2C control, ﬁlter coefﬁcients need to be entered for each ﬁlter stage to conﬁgure it as desired.

Figure 6, Figure 7 and Figure 8 show some of the possible transfer functions of the

equalizer bands. The relations are symmetrical for the suppression and ampliﬁcation functions. A skewing effect can be observed for the higher frequencies.

Different conﬁgurations are available for the same ﬁlter transfer function, thus allowing optimum numerical noise performance. The binary ﬁlter conﬁguration parameters t1and t control the actual conﬁguration and should be chosen according to Equation 6.

0 ω<=π 2⁄



1 ω>π 2⁄



0k2>=0



1k2<0





(5)

(6)

A maximum of 12 dB ampliﬁcation per equalizer stage can be achievedwith respect to the input signal. Each band of the equalizer is provided with a −6 dB ampliﬁcation, so in order to prevent numerical clipping for some ﬁlter settings with over 6 dB of ampliﬁcation, band ﬁlters can be scaled by 0 dB or −6 dB. For optimum numerical noise performance steps of

−6 dB ampliﬁcation should be applied to the highest possible sections that are still within scale signal processing safeguards. Band ﬁlters can be scaled with the binary parameters listed in Table 14.

Table 14. Equalizer scale factor coding

s scale factor (dB)

00 1 −6

8.5.1.3 Equalizer band control

For compact representation with positive signed parameters, parameters k1’ and k2’ are introduced in Equation 7.

The parameters k0, k1', k2', t1, t2 and s must be combined in two 16-bit control words, word1 and word2, and must ﬁt within the representation given in Table 15. Parameters k1' and k2' are unsigned ﬂoating-point representations in Equation 8.

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k1′

k2′

– t11=





+ t



– t20=





+ t



TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

(7)

kxM2E–⋅

M1<

In Equation 8, M is the unsigned mantissa and E the negative signed exponent. For example, in word2 bits [14:8] = [0111 010] represent k2' = (7/24) × 2−2 = 1.09375 10−1.

Table 15. Equalizer control word construction

Word Section Data

word1 15 t

word1 [14:4] 11 mantissa bits of k1’ word1 [3:0] Four exponent bits of k word2 15 t

’

word2 [14:11] Four mantissa bits of k2’ word2 [10:8] Three exponents bits of k word2 [7:1] k

’

word2 0 s

Section 9.5.4 shows the I2C address locations of the controls for various bands of the

equalizer.

010aaa222

Gain

(dB)

Q1 = 0.27

Q2 = 0.61

Q3 = 1.65

(8)

Frequency (Hz)

Fig 6. Transfer functions for several quality factors Q

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TFA9812

BTL stereo Class-D audio ampliﬁer with I2S input

Gain

(dB)

Fig 7. Transfer functions for several center frequencies f

Gain

(dB)

Frequency (Hz)

010aaa223

010aaa224

-6

-12

Fig 8. Transfer functions for several gain factors G

8.5.2 Digital volume control

In I2C control mode both audio channels have separate digital volume control. In Legacy control mode the volume control of both channels is common and the volume control setting depends on the supply voltage on the pin AVOL (32).

8-bit volume control is availableper channel. This is dB-linear down to −124 dB in steps of

0.5 dB. The last step of the volume control is mute.

Table 16 shows the various settings and their related channel suppression:

Frequency (Hz)

Preliminary data sheet Rev. 02 — 22 January 2009 20 of 66

+ 46 hidden pages

NXP Semiconductors TFA9812 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features

2.1 General features

2.2 DSP features

2.3 Audio data input interface format support

3. Applications

4. Quick reference data

5. Ordering information

6. Block diagram

7. Pinning information

7.1 Pinning

8. Functional description

8.1 General

8.2 Functional modes

8.2.1 Control modes

8.2.2 Key operating modes

8.2.3 I2S master/slave modes and MCLK/BCK clock modes

8.3 Power-up/power-down

8.3.1 Power-up

8.3.2 Power-down

8.4 Digital audio data input

8.4.1 Digital audio data format support

8.4.2 Digital audio data format control

8.5 Digital signal-processing features

8.5.1 Equalizer

8.5.1.1 Equalizer options

8.5.1.2 Equalizer band function

8.5.1.3 Equalizer band control

8.5.2 Digital volume control