NXP Semiconductors TDA8932B User Manual

TDA8932B

Class-D audio amplifier

Rev. 03 — 21 June 2007 Product data sheet

1. General description

The TDA8932B is a high efficiency class-D amplifier with low power dissipation.
The continuous time output power is 2 × 15 W in stereo half-bridge application (RL=4Ω)

or 1 × 30 W in mono full-bridge application (RL=8Ω). Due to the low power dissipation
the device can be used without any external heat sink when playing music. Due to the
implementation of thermal foldback, even for high supply voltages and/or lower load
impedances, the device remains operating with considerable music output power without
the need for an external heat sink.

The device has two full-differential inputs driving two independent outputs. It can be used
as mono full-bridge configuration (BTL) or as stereo half-bridge configuration (SE).

2. Features

n Operating voltage from 10 V to 36 V asymmetrical or ±5 V to ±18 V symmetrical
n Mono-bridged tied load (full-bridge) or stereo single-ended (half-bridge) application
n Application without heatsink using thermally enhanced small outline package
n High efficiency and low-power dissipation
n Thermally protected and thermal foldback
n Current limiting to avoid audio holes
n Full short-circuit proof across load and to supply lines (using advanced current

n Switchable internal or external oscillator (master-slave setting)
n No pop noise
n Full-differential inputs

3. Applications

n Flat panel television sets
n Flat panel monitor sets
n Multimedia systems
n Wireless speakers
n Mini and micro systems
n Home sound sets

protection)

NXP Semiconductors

4. Quick reference data

Table 1. Quick reference data

VP= 22 V; f

Symbol Parameter Conditions Min Typ Max Unit

Supplies

V

P

I

P

I

q(tot)

Stereo SE channel; R

P

o(RMS)

Mono BTL; R

P

o(RMS)

osc

supply voltage asymmetrical supply 10 22 36 V
supply current Sleep mode - 0.6 1.0 mA
total quiescent

current

RMS output power continuous time output power

RMS output power continuous time output power;

= 320 kHz; T

< 0.1 Ω

s

[1]

< 0.1 Ω

s

TDA8932B

Class-D audio amplifier

=25°C; unless otherwise specified.

amb

Operating mode; no load, no
snubbers and no filter
connected

[1]

per channel;
THD+N = 10 %; f

=4Ω; VP= 22 V 13.8 15.3 - W

R

L

=8Ω; VP= 30 V 14.0 15.5 - W

R

L

= 1 kHz

i

short time output power per
channel; THD+N = 10 %;
f

= 1 kHz

i

RL=4Ω; VP= 29 V 23.8 26.5 - W

THD+N = 10 %; f

=4Ω; VP= 12 V 15.5 17.2 - W

R

L

=8Ω; VP= 22 V 28.9 32.1 - W

R

L

= 1 kHz

i

short time output power;
THD+N = 10 %; f

= 1 kHz

i

RL=8Ω; VP= 29 V 49.5 55.0 - W

- 4050mA

[2]

[2]

[1] Output power is measured indirectly; based on R
[2] Two layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural

convection.

measurement.

DSon

5. Ordering information

Table 2. Ordering information

Type number Package

Name Description Version

TDA8932BT SO32 plastic small outline package; 32 leads;

body width 7.5 mm

TDA8932BTW HTSSOP32 plastic thermal enhanced thin shrink small outline

package; 32 leads; body width 6.1 mm; lead pitch

0.65 mm; exposed die pad

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 2 of 48

SOT287-1

SOT549-1

NXP Semiconductors

6. Block diagram

TDA8932B

Class-D audio amplifier

IN1P

IN1N

INREF

IN2P

IN2N

DIAG

CGND

OSCREF OSCIO V

10 31 8

2

3

12

15

14

4

7

OSCILLATOR

V

SSD

PROTECTIONS:

OVP, OCP, OTP,

UVP, TF, WP

PWM

MODULATOR

MANAGER

PWM

MODULATOR

DDA

CTRL

CTRL

DRIVER

HIGH

DRIVER

LOW

DRIVER

HIGH

DRIVER

LOW

V

DDA

STABILIZER 11 V

V

SSP1

V

DDA

STABILIZER 11 V

V

SSP2

28

BOOT1

29

V

DDP1

27

OUT1

26

V

SSP1

21

BOOT2

20

V

DDP2

22

OUT2

23

V

SSP2

25

STAB1

24

STAB2

POWERUP

ENGAGE

TEST

6

5

13

Fig 1. Block diagram

MODE

V

SSA

9

TDA8932B

V

SSD(HW)

1, 16, 17, 32

REGULATOR 5 V

V

SSD

V

DDA

V

SSA

HALF SUPPLY VOLTAGE

18

11

30

19

001aaf597

DREF

HVPREF

HVP1

HVP2

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 3 of 48

NXP Semiconductors

7. Pinning information

7.1 Pinning

TDA8932B

Class-D audio amplifier

V

SSD(HW)

ENGAGE BOOT1

POWERUP OUT1

OSCREF

HVPREF OUT2

V

SSD(HW)

1
2

IN1P OSCIO

3

IN1N HVP1

4

DIAG V

5
6
7

CGND V

8

V

DDA

V

SSA

INREF BOOT2

TEST V

IN2N HVP2
IN2P DREF

9
10
11
12
13
14
15
16

TDA8932BT

001aaf598

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

SSD(HW)

DDP1

SSP1

STAB1
STAB2
V

SSP2

DDP2

V

SSD(HW)

V

SSD(HW)

ENGAGE BOOT1

POWERUP OUT1

OSCREF V

HVPREF OUT2

V

SSD(HW)

1
2

IN1P OSCIO

3

IN1N HVP1

4

DIAG V

5
6
7

CGND V

8

V

DDA

9

V

SSA

10
11
12

INREF BOOT2

13

TEST V

14

IN2N HVP2

15

IN2P DREF

16

TDA8932BTW

Fig 2. Pin configuration SO32 Fig 3. Pin configuration HTSSOP32

7.2 Pin description

Table 3. Pin description

Symbol Pin Description

V

SSD(HW)

IN1P 2 positive audio input for channel 1
IN1N 3 negative audio input for channel 1
DIAG 4 diagnostic output; open-drain
ENGAGE 5 engage input to switch between Mute mode and Operating mode
POWERUP 6 power-up input to switch between Sleep mode and Mute mode
CGND 7 control ground; reference for POWERUP, ENGAGE and DIAG
V

DDA

V

SSA

OSCREF 10 input internal oscillator setting (only master setting)
HVPREF 11 decoupling of internal half supply voltage reference
INREF 12 decoupling for input reference voltage
TEST 13 test signal input; for testing purpose only
IN2N 14 negative audio input for channel 2
IN2P 15 positive audio input for channel 2
V

SSD(HW)

V

SSD(HW)

DREF 18 decoupling of internal (reference) 5 V regulator for logic supply

1 negative digital supply voltage and handle wafer connection

8 positive analog supply voltage
9 negative analog supply voltage

16 negative digital supply voltage and handle wafer connection
17 negative digital supply voltage and handle wafer connection

001aaf599

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

SSD(HW)

DDP1

SSP1

STAB1
STAB2

SSP2

DDP2

V

SSD(HW)

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 4 of 48

NXP Semiconductors

Table 3. Pin description (Continued)

Symbol Pin Description

HVP2 19 half supply output voltage 2 for charging single-ended capacitor for

V

DDP2

BOOT2 21 bootstrap high-side driver channel 2
OUT2 22 PWM output channel 2
V

SSP2

STAB2 24 decoupling of internal 11 V regulator for channel 2 drivers
STAB1 25 decoupling of internal 11 V regulator for channel 1 drivers
V

SSP1

OUT1 27 PWM output channel 1
BOOT1 28 bootstrap high-side driver channel 1
V

DDP1

HVP1 30 half supply output voltage 1 for charging single-ended capacitor for

OSCIO 31 oscillator input in slave configuration or oscillator output in master

V

SSD(HW)

Exposed die
pad

TDA8932B

Class-D audio amplifier

channel 2

20 positive power supply voltage for channel 2

23 negative power supply voltage for channel 2

26 negative power supply voltage for channel 1

29 positive power supply voltage for channel 1

channel 1

configuration

32 negative digital supply voltage and handle wafer connection

- HTSSOP32 package only

[1]

[1] The exposed die pad has to be connected to V

8. Functional description

8.1 General

The TDA8932B is a mono full-bridge or stereo half-bridge audio power amplifier using
class-D technology. The audio input signal is converted into a Pulse Width Modulated
(PWM) signal via an analog input stage and PWM modulator. To enable the output power
Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM
signal is applied to a control and handshake block and driver circuits forboth the high side
and low side. A 2nd-order low-pass filter converts the PWM signal to an analog audio
signal across the loudspeakers.

The TDA8932B contains two independent half-bridges with full differential input stages.
The loudspeakers can be connected in the following configurations:

• Mono full-bridge: Bridge Tied Load (BTL)

• Stereo half-bridge: Single-Ended (SE)

The TDA8932B contains common circuits to both channels such as the oscillator, all
reference sources, the mode functionality and a digital timing manager. The following
protections are built-in: thermal foldback, temperature, current and voltage protections.

SSD(HW)

.

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 5 of 48

NXP Semiconductors

8.2 Mode selection and interfacing

The TDA8932B can be switched in three operating modes using pins POWERUP and
ENGAGE:

• Sleep mode: with low supply current.

• Mutemode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at

• Operating mode: the amplifiers are fully operational with output signal.

• Fault mode.

Both pins POWERUP and ENGAGE refer to pin CGND.

Table 4 shows the different modes as a function of the voltages on the POWERUP and

ENGAGE pins.

Table 4. Mode selection

Mode Pin

Sleep < 0.8 V < 0.8 V don’t care
Mute 2 V to 6.0 V
Operating 2 V to 6.0 V
Fault 2 V to 6.0 V

TDA8932B

Class-D audio amplifier

the output is suppressed bydisabling the Vl-converter input stages. The capacitors on
pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical
supply only).

POWERUP ENGAGE DIAG

[1]
[1]
[1]

[1]

< 0.8 V

2.4 V to 6.0 V
don’t care < 0.8 V

[1]

> 2 V
>2V

[1] In case of symmetrical supply conditions the voltage applied to pins POWERUP and ENGAGE must never

exceed the supply voltage (V

DDA

, V

DDP1

or V

DDP2

).

If the transition between Mute mode and Operatingmode is controlled via a time constant,
the start-up will be pop free since the DC output offset voltage is applied gradually to the
output between Mute mode and Operating mode. The bias current setting of the
VI-converters is related to the voltage on pin ENGAGE:

• Mute mode: the bias current setting of the VI-converters is zero (VI-converters

disabled)

• Operating mode: the bias current is at maximum

The time constant required to apply the DC output offset voltage gradually between Mute
mode and Operating mode can be generated by applying a decoupling capacitor on pin
ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF.

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 6 of 48

NXP Semiconductors

V

P

POWERUP

DREF

HVPREF

HVP1, HVP2

2.0 V (typical)

ENGAGE

1.2 V (typical)

TDA8932B

Class-D audio amplifier

≤ 0.8 V

audio

OUT1, OUT2

PWM

DIAG

OSCIO

Fig 4. Start-up sequence

8.3 Pulse width modulation frequency

The output signal of the amplifier is a PWM signal with a carrier frequency of
approximately 320 kHz. Using a 2nd-order low-pass filter in the application results in an
analog audio signal across the loudspeaker. The PWM switching frequency can be set by
an external resistor Rosc connected between pins OSCREF and V
frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 kΩ,
the carrier frequency is set to an optimized value of 320 kHz (see Figure 5).

If two or more TDA8932B devices are used in the same audio application, it is
recommended to synchronize the switching frequency of all devices. This can be realized
by connecting all pins OSCIO together and configure one of the TDA8932B in the
application as clock master, while the other TDA8932B devices are configured in slave
mode.

AUDIO AUDIO AUDIO

PWMPWM

operating operating

001aaf885

SSD(HW)

sleepmute operating fault

. The carrier

Pin OSCIO is a 3-state input or output buffer.Pin OSCIO is configured in master mode as
oscillator output and in slave modeas oscillator input. Master mode is enabled byapplying
a resistor while slave mode is entered by connecting pin OSCREF directly to pin V

SSD(HW)

(without any resistor).
The value of the resistor also sets the frequency of the carrier which can be estimated by

the following formula:

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 7 of 48

NXP Semiconductors

TDA8932B

Class-D audio amplifier

osc

12.45 109×

=

--------------------------- -

Rosc

f

Where:

f

= oscillator frequency (Hz)

osc

Rosc = oscillator resistor (on pin OSCREF) (Ω)

550

f

osc

(kHz)

450

350

250

25 454030 35

Fig 5. Oscillation frequency as a function of resistor Rosc

(1)

001aad758

Rosc (kΩ)

Table 5 summarizes how to configure the TDA8932B in master or slave configuration.

For device synchronization see Section 14.6 “Device synchronization”.

Table 5. Master or slave configuration

Configuration Pin

OSCREF OSCIO

Master Rosc > 25 kΩ to V
Slave Rosc = 0 Ω; shorted to V

SSD(HW)

SSD(HW)

output
input

8.4 Protection

The following protection is included in the TDA8932B:

• Thermal Foldback (TF)

• OverTemperature Protection (OTP)

• OverCurrent Protection (OCP)

• Window Protection (WP)

• Supply voltage protection:

– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– UnBalance Protection (UBP)

• ElectroStatic Discharge (ESD)

The reaction of the device to the different fault conditions differs per protection.

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 8 of 48

NXP Semiconductors

8.4.1 Thermal Foldback (TF)

If the junction temperature of the TDA8932B exceeds the threshold level (Tj> 140 °C) the
gain of the amplifier is decreased graduallyto a level where the combination of dissipation
(P) and the thermal resistance from junction to ambient [R
temperature around the threshold level.

This means that the device will not completely switch off, but remains operational at lower
output power levels. Especially with music output signals this feature enables high peak
output power while still operating without any external heat sink other than the
printed-circuit board area.

If the junction temperature still increases due to external causes, the OTP shuts down the
amplifier completely.

8.4.2 OverTemperature Protection (OTP)

If the junction temperature Tj> 155 °C, then the power stage will shut down immediately.

8.4.3 OverCurrent Protection (OCP)

When the loudspeaker terminals are short-circuited or if one of the demodulated outputs
of the amplifier is short-circuited to one of the supply lines, this will be detected by the
OCP.

TDA8932B

Class-D audio amplifier

] results in a junction

th(j-a)

If the output current exceeds the maximum output current (I
be limitedby the amplifier to 4 A while the amplifier outputs remain switching (the amplifier
is NOT shutdown completely). This is called current limiting.

The amplifier can distinguish between an impedance drop of the loudspeaker and a
low-ohmic short-circuit across the load or to one of the supply lines. This impedance
threshold depends on the supply voltage used:

• Incase of a short-circuit across the load, the audio amplifier is switchedoff completely

and after approximately 100 ms it will try to restart again. If the short-circuit condition
is still present after this time, this cycle will be repeated. The average dissipation will
be low because of this low duty cycle.

• In case of a short to one of the supply lines, this will trigger the OCP and the amplifier

will be shut down. During restart the window protection will be activated. As a result
the amplifier will not start until 100 ms after the short to the supply lines is removed.

• In case of impedance drop (e.g. due to dynamic behavior of the loudspeaker) the

same protection will be activated. The maximum output current is again limited to 4 A,
but the amplifier will NOT switch off completely (thus preventing audio holes from
occurring). The result will be a clipping output signal without any artifacts.

8.4.4 Window Protection (WP)

The WP checks the PWM output voltage before switchingfrom Sleep mode to Mute mode
(outputs switching) and is activated:

> 4 A), this current will

O(ocp)

• During the start-up sequence, when pin POWERUP is switched from Sleep mode to

Mute mode. In the event of a short-circuit at one of the output terminals to V
V

, V

SSP1

for open-circuit outputs. Because the check is done before enablingthe power stages,
no large currents will flow in the event of a short-circuit.

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 9 of 48

DDP2

or V

the start-up procedure is interrupted and the TDA8932B waits

SSP2

DDP1

,

NXP Semiconductors

• When the amplifier is completely shut down due to activation of the OCP because a

8.4.5 Supply voltage protection

If the supply voltage drops below 10 V, the UnderVoltage Protection (UVP) circuit is
activated and the system will shut down directly. This switch-off will be silent and without
pop noise. When the supply voltage rises above the threshold level, the system is
restarted again after 100 ms.

If the supply voltage exceeds 36 V the OverVoltage Protection (OVP) circuit is activated
and the power stages will shut down. It is re-enabled as soon as the supply voltage drops
below the threshold level. The system is restarted again after 100 ms.

It should be noted that supply voltages > 40 V may damage the TDA8932B. Two
conditions should be distinguished:

1. If the supply voltage is pumped to higher values by the TDA8932B application itself

2. If a supply voltage > 40 V is caused by other or external causes, then the TDA8932B

TDA8932B

Class-D audio amplifier

short-circuit to one of the supply lines is made, then during restart (after 100 ms) the
window protection will be activated. As a result the amplifier will not start until the
short-circuit to the supply lines is removed.

(see also Section 14.3), the OVP is triggered and the TDA8932B is shut down. The
supply voltage will decrease and the TDA8932B is protected against any overstress.

will shut down, but the device can still be damaged since the supply voltage will
remain > 40 V in this case. The OVP protection is not a supply voltage clamp.

An additional UnBalance Protection (UBP) circuit compares the positive analog supply
voltage (V

) and the negative analog supply voltage (V

DDA

) and is triggered if the

SSA

voltage difference between them exceeds a certain level. This level depends on the sum
of both supply voltages. The unbalance threshold levels can be defined as follows:

• LOW-level threshold: V

• HIGH-level threshold: V

P(th)(ubp)l

P(th)(ubp)h

<8⁄5× V

>8⁄3× V

HVPREF

HVPREF

In a symmetrical supply the UBP is released when the unbalance of the supply voltage is
within 6 % of its starting value.

Table 6 shows an overview of all protection and the effect on the output signal.

Table 6. Protection overview

Protection Restart

When fault is removed Every 100 ms

OTP no yes
OCP yes no
WP yes no
UVP no yes
OVP no yes
UBP no yes

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 10 of 48

NXP Semiconductors

8.5 Diagnostic input and output

Whenevera protection is triggered, except for TF, pin DIAG is activated to LOWlevel (see

Table 6). An internal reference supply will pull-up the open-drain DIAG output to

approximately 2.4 V. This internal reference supply can deliver approximately 50 µA.
Pin DIAG refers to pin CGND. The diagnostic output signal during different short
conditions is illustrated in Figure 6. Using pin DIAG as input, a voltage < 0.8 V will put the
device into Fault mode.

TDA8932B

Class-D audio amplifier

V

2.4 V

0 V

o

amplifier
restart no restart

≈ 50 ms

≈ 50 ms

shorted load

2.4 V

0 V

V

o

short to

supply line

001aad759

Fig 6. Diagnostic output for different short-circuit conditions

8.6 Differential inputs

For a high common-mode rejection ratio and a maximum of flexibility in the application,
the audio inputs are fully differential. By connecting the inputs anti-parallel, the phase of
one of the two channels can be inverted, so that the amplifier can operate as a mono BTL
amplifier. The input configuration for a mono BTL application is illustrated in Figure 7.

In SE configuration it is also recommended to connect the two differential inputs in
anti-phase. This has advantages forthe current handling of the power supply at low signal
frequencies and minimizes supply pumping (see also Section 14.8).

IN1P
IN1N

OUT1

audio

input

IN2P
IN2N

OUT2

001aad760

Fig 7. Input configuration for mono BTL application

8.7 Output voltage buffers

When pin POWERUP is set HIGH, the half supply output voltage buffers are switched on
in asymmetrical supply configuration. The start-up will be pop free since the device starts
switching when the capacitor on pin HVPREF and the SE capacitors are completely
charged.

Output voltage buffers:

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 11 of 48

NXP Semiconductors

• PinsHVP1 and HVP2: The time requiredfor charging the SE capacitor depends on its

value. The half supply voltage output is disabled when the TDA8932B is used in a
symmetrical supply application.

• Pin HVPREF: This output voltage reference buffer charges the capacitor on pin

HVPREF.

• PinINREF: This output voltage reference buffercharges the input referencecapacitor

on pin INREF. Pin INREF applies the bias voltage for the inputs.

9. Internal circuitry

Table 7. Internal circuitry

Pin Symbol Equivalent circuit

1V
16 V
17 V
32 V

SSD(HW)
SSD(HW)
SSD(HW)
SSD(HW)

1, 16,

17, 32

TDA8932B

Class-D audio amplifier

V

DDA

V

SSA

001aad784

2 IN1P
3 IN1N
12 INREF
14 IN2N
15 IN2P

4 DIAG

2, 15

12

3, 14

V

DDA

2 kΩ

± 20 %

48 kΩ
± 20 %

48 kΩ
± 20 %

2 kΩ

± 20 %

V

SSA

V

DDA

4

2.5 V

50 µA

500 Ω

± 20 %

100 kΩ
± 20 %

V/I

HVPREF

V/I

001aad785

V

SSA

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

CGND

001aaf607

Product data sheet Rev. 03— 21 June 2007 12 of 48

NXP Semiconductors

Table 7. Internal circuitry (Continued)

Pin Symbol Equivalent circuit

5 ENGAGE

TDA8932B

Class-D audio amplifier

2 kΩ

± 20 %

2.8 V

I

ref

= 50 µA

V

DDA

5

100 kΩ
± 20 %

6 POWERUP

7 CGND

SSA

CGND

V

DDA

V

SSA

CGND

V

DDA

7

V

SSA

001aad789

001aaf608

001aad788

V

6

8V

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

DDA

8

V

SSA

V

SSD

001aad790

Product data sheet Rev. 03— 21 June 2007 13 of 48

NXP Semiconductors

Table 7. Internal circuitry (Continued)

Pin Symbol Equivalent circuit

9V

SSA

TDA8932B

Class-D audio amplifier

V

DDA

9

V

SSD

001aad791

10 OSCREF

11 HVPREF

13 TEST

V

DDA

I

ref

10

V

SSA

V

11

V

13

DDA

SSA

V

V

001aad795

001aad792

001aaf604

DDA

SSA

18 DREF

V

DD

18

V

SSD

001aag025

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 14 of 48

NXP Semiconductors

Table 7. Internal circuitry (Continued)

Pin Symbol Equivalent circuit

19 HVP2
30 HVP1

19, 30

V

V

DDA

SSA

TDA8932B

Class-D audio amplifier

001aag026

20 V
23 V
26 V
29 V

DDP2
SSP2
SSP1
DDP1

21 BOOT2
28 BOOT1

22 OUT2
27 OUT1

24 STAB2
25 STAB1

22, 27

20, 29

23, 26

21, 28

V

V

V

V

001aad798

OUT1, OUT2

001aad799

DDP1,

DDP2

SSP1,

SSP2

001aag027

V

DDA

24, 25

V

SSP1,

V

SSP2

001aag028

31 OSCIO

DREF

31

V

SSD

001aag029

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 15 of 48