NXP Semiconductors TDA8752B User Manual

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Rev. 03 — 21 July 2000 Product specification

1. General description

The TDA8752B is a triple 8-bit ADC with controllable amplifiers and clamps for the
digitizing of large bandwidth RGB signals.

The clamp level, the gain and all other settings are controlled via a serial interface
(either I2C-bus or 3-wire serial bus, selected via a logic input).

The IC also includes a PLL that can be locked to the horizontal line frequency and
generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the ADC.

It is possible to set the TDA8752B serial bus address to four different values, when
several TDA8752B ICs are used in a system, by means of the I2C-bus interface (for
example, two ICs used in an odd/even configuration).

2. Features

■ Triple 8-bit ADC

■ Sampling rate up to 110 Msps

c

c

■ IC controllable via a serial interface, which can be either I2C-bus or 3-wire serial

bus, selected via a TTL input pin

■ IC analog voltageinputfrom0.4 to 1.2 V (p-p) to produce a full-scale ADC input of

1 V (p-p)

■ Three clamps for programming a clamping code between −63.5 and +64 in steps

of1⁄2LSB for RGB signals, and from +120 to +136 in steps of1⁄2LSB for YUV
signals

■ Three controllable amplifiers: gain controlled via the serial interface to produce a

full-scale resolution of1⁄2LSB peak-to-peak

■ Amplifier bandwidth of 250 MHz

■ Low gain variation with temperature

■ PLL controllable via the serial interface to generate the ADC clock which can be

locked to a line frequency of 15 to 280 kHz

■ Integrated PLL divider

■ Programmable phase clock adjustment cells

■ Internal voltage regulators

■ TTL compatible digital inputs and outputs

■ Chip enable high-impedance ADC output

Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

■ Power-down mode

■ Possibility to use up to four ICs in the same system when using the I2C-bus

interface, or more when using the 3-wire serial bus interface

■ 1.1 W power dissipation.

3. Applications

■ RGB high-speed digitizing

■ LCD panels drive

■ LCD projection systems

■ VGA and higher resolutions

■ Using two ICs in parallel, a higher display resolution can be obtained: 200 MHz

pixel frequency.

4. Quick reference data

Table 1: Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

V

CCA

V

DDD

V

CCD

V

CCO

V

CCA(PLL)

V

CCO(PLL)

I

CCA

I

DDD

I

CCD

I

CCO

I

CCA(PLL)

I

CCO(PLL)

f

clk

f

ref(PLL)

f

VCO

INL DC integral non-linearity from analog input to digital

DNL DC differential non-linearity from analog input to digital

∆G

amp

B amplifier bandwidth −3 dB; T
t

set

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Product specification Rev. 03 — 21 July 2000 2 of 38

analog supply voltage for R, G and B channels 4.75 5.0 5.25 V
logic supply voltage for I2C-bus and 3-wire

4.75 5.0 5.25 V

serial bus
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V
analog PLL supply voltage 4.75 5.0 5.25 V
output PLL supply voltage 4.75 5.0 5.25 V
analog supply current − 120 − mA
logic supply current for I2C-bus and 3-wire − 1.0 − mA
digital supply current − 40 − mA
output stages supply current f

= 110 MHz; ramp input − 26 − mA

clk

analog PLL supply current − 28 − mA
output PLL supply current − 5 − mA
clock frequency −−110 MHz
PLL reference clock

15 − 280 kHz

frequency
VCO output clock frequency 12 − 110 MHz

−±0.5 ±1.5 LSB
output; full-scale; ramp
input; f

= 110 MHz

clk

−±0.5 ±1.0 LSB
output; full-scale; ramp

/∆T amplifier gain stability as a

function of temperature

settling time of the ADC block
plus AGC

input; f
V

ref

100 ppm/°C maximum

input signal settling
time <1 ns; T

= 110 MHz

clk

= 2.5 V with

=25°C 250 −−MHz

amb

amb

−−200 ppm/°C

−−6ns

=25°C

© Philips Electronics N.V. 2000. All rights reserved.

Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Table 1: Quick reference data

…continued

Symbol Parameter Conditions Min Typ Max Unit

DR

PLL

P

tot

j

PLL(rms)

PLL divider ratio 100 − 4095
total power dissipation f
maximum PLL phase jitter

(RMS value)

= 110 MHz; ramp input − 1.1 − W

clk

f

= 66.67 kHz;

ref

= 110 MHz

f

clk

− 112 − ps

5. Ordering information

Table 2: Ordering information

Type number Package Sampling

Name Description Version

TDA8752BH/8 QFP100 plastic quad flat package; 100 leads (lead length

SOT317-2 110

1.95 mm); body 14 × 20 × 2.8 mm

frequency (MHz)

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Product specification Rev. 03 — 21 July 2000 3 of 38

© Philips Electronics N.V. 2000. All rights reserved.

Philips Semiconductors

6. Block diagram

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

RAGC

RGAINC

RIN

RDEC

V

GAGC

GGAINC

GIN

GDEC

BAGC

BGAINC

BIN

BDEC

TDO

TCK
ADD2
ADD1

SEN

SCL

SDA

DIS

2

I

C/3W

V

ref

CCA(R)

V

CCA(G)

11
6
8

12
10

3

14
16

20
18

22
24

28
26

36
35

34
33
38
42
39
37
32

1, 5, 30, 31, 43 , 44
50, 51, 100

V

CCA(B)

V

DDD

19

27

SERIAL

INTERFACE

2

I

C-BUS

OR

3-WIRE

V

CCO(R)

40

V

CCO(G)

79

MUX

V

CCO(B)

69

HSYNCI

2

C-bus; 1-bit

I
(Hlevel)

90

59

V

CCA(PLL)

V

V

CCD

95

99

GREEN CHANNEL

G

AGND

21

V

SSD

B

29

ADC

CCO(PLL)

85

CLAMP

CLP

AGND

89

AGND

R

13

RED CHANNEL

BLUE CHANNEL

TDA8752B

REGULATOR

4 2 88 97 98

DEC2DEC1HSYNCn.c.

PWDWN

CP

OGND

41

PLL

OGND

70

CZ

G

OGND

R

60

OUTPUTS

AGND

B

48

PLL

OGND

96

DGND

PLL

86

82

71 to 78

61 to 68

49, 52 to 58

FCE467

45

17
15

25
23

47

84
83

81
80

92
91
93
94

9
7

46
87

RCLP

RBOT

R0 to R7

ROR

GCLP
GBOT

G0 to G7
GOR

OE
BCLP
BBOT

B0 to B7
BOR

CKADCO
CKBO

CKAO
CKREFO

CKEXT
INV
COAST
CKREF

Fig 1. Block diagram.

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Product specification Rev. 03 — 21 July 2000 4 of 38

© Philips Electronics N.V. 2000. All rights reserved.

Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

CLP RAGC

RCLP

V

P

150

RIN

V

ref

kΩ

3 kΩ

45 kΩ

FINE GAIN ADJUST

2

I

DAC

5

REGISTER

C-bus: 5 bits (Fr) I2C-bus: 7 bits (Cr)

Fig 2. Red channel diagram.

MUX

HSYNCI

CLAMP

CONTROL

AGC

RGAINC

V

CCAR

CLKADC

ADC

8

D

D ≥ R

R

8

1

7

1

REGISTER

COARSE GAIN ADJUST

DAC

8

REGISTER

2

C-bus: 8 bits (Or)

I

OUTPUTS

I2C-BUS

ROR

8

R0 to R7

OE

RBOT

FCE468

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Product specification Rev. 03 — 21 July 2000 5 of 38

Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

CKREF

2

I

C-bus; 1 bit

(Vlevel)

edge selector

2

I

C-bus;
1 bit
(Edge)

COAST

PHASE

FREQUENCY

DETECTOR

2

C-bus; 5 bits

I
(Ip, Up, Do)

DIV N (100 to 4095)

2

C-bus; 12 bits (Di)

I

C

Z

CZ CP

loop filter

2

I

C-bus;

3 bits (Z)

C

P

VCO

2

C-bus;

I

2 bits (Vco)

12 to

100 MHz

phase selector A

2

I

C-bus;

5 bits (Pa)

phase selector B

2

C-bus; 5 bits (Pb)

I

CKEXT INV

MUX

2

C-bus;

I

1 bit (Cka)

NCKBO

SYNCHRO

0°/180°

CLKADC

MUX

MUX

2

C-bus;

I

1 bit (Ckab)

2

C-bus;

I

1 bit (Ckb)

FCE465

CKADCO

CKBO

CKAO

CKREFO

Fig 3. PLL diagram.

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Product specification Rev. 03 — 21 July 2000 6 of 38

Philips Semiconductors

7. Pinning information

7.1 Pinning

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

DEC2

V

DEC1

RAGC
RBOT

RGAINC

RCLP

RDEC

V

CCA(R)

RIN

AGND

GAGC
GBOT

GGAINC

GCLP

GDEC

V

CCA(G)

GIN

AGND

BAGC

BBOT

BGAINC

BCLP

BDEC

V

CCA(B)

AGND

n.c.

n.c.

BIN

n.c.

CKADCO

CKBO

PLL

OGND

CKAO

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
5130

CKREFO
V

CCO(R)

R7
R6
R5
R4
R3
R2
R1
R0
OGND
V

CCO(G)

G7
G6
G5
G4
G3
G2
G1
G0
OGND
V

CCO(B)

B7
B6
B5
B4
B3
B2
B1
n.c.

R

G

PLL

CCA(PLL)

n.c.

V

CZCPAGND

99989796959493929190898887868584838281

100

1
2
3

ref

4
5
6
7
8

9
10
11
12
13

R

14
15
16
17
18
19
20
21

G

22
23
24
25
26
27
28
29

B

CCD

V

CKREF

COAST

TDA8752BH

CKEXT

INV

HSYNC

CLP

PWDWNOEDGND

V

CCO(PLL)

31323334353637383940414243444546474849

n.c.

n.c.

C/3W

2

I

ADD1

ADD2

TCK

TDO

DIS

SEN

SDA

DDD

V

SSD

V

SCL

n.c.

ROR

GOR

BOR

B

B0

OGND

50

n.c.

FCE469

Fig 4. Pin configuration.

9397 750 07338

Product specification Rev. 03 — 21 July 2000 7 of 38

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Philips Semiconductors

7.2 Pin description

Table 3: Pin description

Symbol Pin Description

n.c. 1 not connected
DEC2 2 main regulator decoupling input 2
V

ref

DEC1 4 main regulator decoupling input 1
n.c. 5 not connected
RAGC 6 red channel AGC output
RBOT 7 red channel ladder decoupling input (BOT)
RGAINC 8 red channel gain capacitor input
RCLP 9 red channel gain clamp capacitor input
RDEC 10 red channel gain regulator decoupling input
V

CCA(R)

RIN 12 red channel gain analog input
AGND
GAGC 14 green channel AGC output
GBOT 15 green channel ladder decoupling input (BOT)
GGAINC 16 green channel gain capacitor input
GCLP 17 green channel gain clamp capacitor input
GDEC 18 green channel gain regulator decoupling input
V

CCA(G)

GIN 20 green channel gain analog input
AGND
BAGC 22 blue channel AGC output
BBOT 23 blue channel ladder decoupling input (BOT)
BGAINC 24 blue channel gain capacitor input
BCLP 25 blue channel gain clamp capacitor input
BDEC 26 blue channel gain regulator decoupling input
V

CCA(B)

BIN 28 blue channel gain analog input
AGND
n.c. 30 not connected
n.c. 31 not connected

2

C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire

I

ADD1 33 I
ADD2 34 I
TCK 35 scan test mode input (active HIGH)
TDO 36 scan test output
DIS 37 I

SEN 38 select enable for 3-wire serial bus input (see Figure 10)

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

3 gain stabilizer voltage reference input

11 red channel gain analog power supply

R

G

B

13 red channel gain analog ground

19 green channel gain analog power supply

21 green channel gain analog ground

27 blue channel gain analog power supply

29 blue channel gain analog ground

serial bus (active LOW)

2

C-bus address control input 1

2

C-bus address control input 2

2

C-bus and 3-wire serial bus disable control input (disable at

HIGH level)

9397 750 07338

Product specification Rev. 03 — 21 July 2000 8 of 38

© Philips Electronics N.V. 2000. All rights reserved.

Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Table 3: Pin description

…continued

Symbol Pin Description

SDA 39 I2C-bus/3-wire serial bus data input
V

DDD

V

SSD

SCL 42 I

40 logic I2C-bus/3-wire serial bus digital power supply
41 logic I2C-bus/3-wire serial bus digital ground

2

C-bus/3-wire serial bus clock input
n.c. 43 not connected
n.c. 44 not connected
ROR 45 red channel ADC output bit out of range
GOR 46 green channel ADC output bit out of range
BOR 47 blue channel ADC output bit out of range
OGND

B

48 blue channel ADC output ground
B0 49 blue channel ADC output bit0 (LSB)
n.c. 50 not connected
n.c. 51 not connected
B1 52 blue channel ADC output bit1
B2 53 blue channel ADC output bit2
B3 54 blue channel ADC output bit3
B4 55 blue channel ADC output bit4
B5 56 blue channel ADC output bit5
B6 57 blue channel ADC output bit6
B7 58 blue channel ADC output bit7 (MSB)
V

CCO(B)

OGND

G

59 blue channel ADC output power supply

60 green channel ADC output ground
G0 61 green channel ADC output bit 0 (LSB)
G1 62 green channel ADC output bit 1
G2 63 green channel ADC output bit 2
G3 64 green channel ADC output bit 3
G4 65 green channel ADC output bit 4
G5 66 green channel ADC output bit 5
G6 67 green channel ADC output bit 6
G7 68 green channel ADC output bit 7 (MSB)
V

CCO(G)

OGND

R

69 green channel ADC output power supply

70 red channel ADC output ground
R0 71 red channel ADC output bit 0 (LSB)
R1 72 red channel ADC output bit 1
R2 73 red channel ADC output bit 2
R3 74 red channel ADC output bit 3
R4 75 red channel ADC output bit 4
R5 76 red channel ADC output bit 5
R6 77 red channel ADC output bit 6
R7 78 red channel ADC output bit 7 (MSB)
V

CCO(R)

79 red channel ADC output power supply

9397 750 07338

Product specification Rev. 03 — 21 July 2000 9 of 38

© Philips Electronics N.V. 2000. All rights reserved.

Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Table 3: Pin description

…continued

Symbol Pin Description

CKREFO 80 reference output clock re-synchronized horizontal pulse
CKAO 81 PLL clock output 3 (in phase with reference output clock

CKBO)

OGND

PLL

CKAO or

82 PLL digital ground
CKBO 83 PLL clock output 2
CKADCO 84 PLL clock output1 (in phase with internal ADC clock)
V

CCO(PLL)

85 PLL output power supply
DGND 86 digital ground
OE 87 outputenable; active LOW (when OEis HIGH, the outputs are

in high-impedance)

PWDWN 88 power-down control input (device is in Power-down mode

when this pin is HIGH)
CLP 89 clamp pulse input (clamp active HIGH)
HSYNC 90 horizontal synchronization input pulse
INV 91 PLL clock output inverter command input (invert when HIGH)
CKEXT 92 external clock input
COAST 93 PLL coast command input
CKREF 94 PLL reference clock input
V

CCD

AGND

PLL

95 digital power supply

96 PLL analog ground
CP 97 PLL filter input
CZ 98 PLL filter input
V

CCA(PLL)

99 PLL analog power supply
n.c. 100 not connected

9397 750 07338

Product specification Rev. 03 — 21 July 2000 10 of 38

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Philips Semiconductors

8. Functional description

This triple high-speed 8-bit ADC is designed to convert RGB signals, coming from an
analog source, into digital data used by a LCD driver (pixel clockupto 200 MHz when
using 2 ICs).

8.1 IC analog video inputs

The video inputs are internally DC polarized. These inputs are AC coupled externally.

8.2 Clamps

Three independent parallel clamping circuits are used to clamp the video input
signals on the black level and to control the brightness level. The clamping code is
programmable between code −63.5 and +64 and from +120 to +136 in steps of

1

⁄2LSB. The programming of the clamp value is achieved via an 8-bit DAC. Each

clamp must be able to correct an offset from ±0.1 V to ±10 mV within 300 ns, and
correct the total offset in 10 lines.

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Fig 5. Clamp definition.

8.3 Variable gain amplifiers

The clamps are controlled by an external TTL positive going pulse (pin CLP). The
drop of the video signal is <1 LSB.

Normally, the circuit operates with a 0 code clamp, corresponding to the 0 ADC code.
This clamp code can be changed from −63.5 to +64 as represented in Figure 5, in
steps of1⁄2LSB. The digitizedvideo signal is alwaysbetween code 0 and code 255 of
the ADC. It is also possible to clamp from code 120 to code 136 corresponding to
120 ADC code to 136 ADC code. Then clamping on code 128 of the ADC is possible.

255

digitized

video signal

CLP

video
signal

code 64
code 0

−63.5

code

clamp

programming

FCE471

= 120 to 136

Three independent variable gain amplifiers are used to provide, to each channel, a
full-scale input range signal to the 8-bit ADC. The gain adjustment range is designed
so that for an input range varying from 0.4 to 1.2 V (p-p), the output signal
corresponds to the ADC full-scale input of 1 V (p-p).

To ensure that the gain does not vary over the whole operating temperature range, an
external supplied reference voltage V

= 2.5 V (DC), with a maximum variation of

ref

100 ppm/°C, is used to calibrate the gain at the beginning of each video line before
the clamp pulse.

9397 750 07338

Product specification Rev. 03 — 21 July 2000 11 of 38

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Philips Semiconductors

The calibration of the gains is done using the following principle.

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

From the reference voltage V

a reference signal of 0.156 V (p-p) (1⁄16V

ref

ref

) is
generated internally. During the synchronization part of the video line, the multiplexer,
controlled by the TTL synchronization signal (HSYNCI, coming from HSYNC;
see Figure 1) with a width equal to one of the video synchronization signals (e.g. the
signal coming from a synchronization separator), is switched between the two
amplifiers.

The output of the multiplexer is either the normal video signal or the 0.156 V
reference signal (during HSYNC).

The corresponding ADC outputs are then compared to a preset value loaded in a
register. Depending on the result of the comparison, the gain of the variable gain
amplifiers is adjusted (coarse gain control; see Figure 2 and 6). The three 7-bit
registers receive data via a serial interface to enable the gain to be programmed.

The preset value loaded in the 7-bit register is chosen between approximately
67 codes to ensure the full-scale input range (see Figure 6). A contrast control can be
achieved using these registers. In this case care should be taken to stay within the
allowed code range (32 to 99).

A fine correction using three 5-bit DACs, also controlled via the serial interface, is
used to fine tune the gain of the three channels (fine gain control; see Figure 2 and 7)
and to compensate the channel-to-channel gain mismatch.

With a full-scale ADC input, the resolution of the fine register corresponds to1⁄2LSB
peak-to-peak variation.

Fig 6. Coarse gain control.

To use these gain controls correctly,it is recommended to fix the coarse gain (to have
a full-scale ADC input signal) to within 4 LSB and then adjust it with the fine gain. The
gain is adjusted during HSYNC. During this time the output signal is not related to the
amplified input signal. The outputs, when the coarse gain system is stable, are
related to the programmed coarse code (see Figure 6).

0.6

ADC output

code

255
227

160
128

V

i (p-p)

2

FCE472

N

COARSE

coarse

register

value

(67 codes)

code

127

99

32

0

0.156 =

G

(max)

G

(min)

V

0.2

ref

16

9397 750 07338

Product specification Rev. 03 — 21 July 2000 12 of 38

© Philips Electronics N.V. 2000. All rights reserved.