NXP Semiconductors S12 MagniV, S12ZVC Quick Start Manual

Quick Start Guide

S12 MagniV Mixed-signal MCUs

S12ZVC Evaluation Board

Introduction and default settings

Quick Start

2

This guide shows how to quickly connect the board to a host PC and
execute a demonstration application preloaded in to the flash memory.

The S12ZVC MCUintegrates:

• S12Z CPU

• Power supply

PNP external ballast transistor for
VDDX, VDDA, and VDDC

LED powerindicators

• Reset

• LEDs

• Buzzer

• ADC potentiometer

• Keyboard matrix

• High-voltage input

• Sensors

Temperature and humidity
Pressure sensor

Inertial sensor SPI X-Yaxis

• SENT

• CAN

• LIN

Default jumper positions of the
VLG-S12ZVC board are shown in the

following section.

Device overview S12ZVC family

The MC9S12ZVC family is a new member of the S12 MagniV product line integrating a
battery level (12 V) voltage regulator, supply voltage monitoring, high voltage inputs,and
a CAN physical interface. It’s primarily targeting at CAN nodes like sensors, switch panels,
or small actuators. It offers various low-power modes and wake-up management to
address sta te of the art pow er consu mptio nrequirements.

Some members of the MC9S12ZVC family are also offered for high temperature applications
requiring AEC-Q100 Grade 0 (-40°C to +150°C ambient operating temperature range) The
MC9S12ZVC family is based on the enhanced performance, linear address space S12Z
core and delivers an optimized solution with the integration of several key system components
into a single device, optimizing system architecture and achieving significant space savings.

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Jumper default configuration

This section describes about the jumper configuration.

Quick Start

Block Diagram shows the maximum configuration.

Not all pins or all peripherals are availableon all devicesand packages. Reroutingoptionsare not shown.

4

CAN-PHY

Pierce Oscillator

Temp

Sense

12-bit

Analog-Digital

Converter

MS-CAN

InternalRC

Oscillator,

+/-1.3%

PLL

with Frequency

Modulationoption

8-Bit
DAC

Analog

Comparator

2 x SCI

2 SPI

S12ZCPU 32 MHzBus

(25 MHZ @ >150°CTj)

Hi-Res-PWM 4ch 16-bit

Hi-Res-Timer 4ch16-bit

1 L1C

Up to 192KB

Flash (ECC)

PWM 4ch 16-bit

SENT TIMER 4ch 16-bit

EEPROM

with ECC up to

2 K bytes)

RAM with ECC

up to8 K bytes

Real TimeInterrupt

4 ch LSD(+25mA)

open drain

BDM/BDC

1ch HSD(+20mA)

open drain

2-HVI

V-SUP

VoltageSupply

Monitor

Vreg for CAN PHY

with ext. ballast (BCTLC)

Figure 1. S12ZVC architecture diagram1

5

Figure 2. Jumper configurationdiagram

PRIMARY SIDE

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6

Header Reference position

J5 1-2

J8 1-2

J10 2-3

J11 1-2

J12 1-2

J13 2-3

J15 1-2

J14 1-2

J20 1-2, 3-4, 5-6, 7-8

J48 1,2

J50

1-2, 3-4, 5-6, 7-8, 9-10,

11-12, 13-14, 15-16

Header Reference position

J16 1, 2

J17 1, 2

J18 1, 2

J19 1, 2

J22 1-2, 3-4, 5-6, 7-8

J25 1, 2

J26 1- 2

J29 1- 2

J30 1- 2

J31 1- 2

J35 1- 2

Quick Start

Jumper default configuration

The following table lists the jumper default configuration.