NXP Semiconductors Qorivva MPC5643L Reference Manual
Freescale Semiconductor
Document Number: AN4034
Application Note
Qorivva MPC5643L Dual
Processor Mode
by: Mark Ruthenbeck
Applications Engineering
Microcontroller Solutions Group
Rev. 0, 03/2011
1 Scope
This paper is a brief tutorial and description on how to
select and run the MPC5643L in decoupled parallel
mode (DPM).
2 Reference material
Freescale document MPC5643LRM, MPC5643L
Microcontroller Reference Manual, Rev. 7, October
2010.
3 Overview
The paper reviews the dual core modes of the
MPC5643L, but focuses on the operation of the
decoupled parallel mode (DP mode or DPM) on the chip
and on how to enable the DPM.
The MPC5643L operates in both lock step mode and
DPM — this paper will focus on the DPM mode.
Contents
1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Reference material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 MPC5643L dual core architecture . . . . . . . . . . . . . . . . . . 2
4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.2 Sphere of replication . . . . . . . . . . . . . . . . . . . . . . . . 3
4.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.1 Hardware setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Software setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.3 Basic dual core flash boot program flow . . . . . . . . . 5
6 Changing between LSM and DPM . . . . . . . . . . . . . . . . . 7
6.1 Configure the flash programming utility . . . . . . . . . . 7
6.2 Dump shadow flash to s-record file . . . . . . . . . . . . . 8
6.3 Modify s-record file to change LSM/DPM configuration
8
6.4 Program shadow flash with updated user configura-
tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.5 Verify new configuration . . . . . . . . . . . . . . . . . . . . . 9
7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
© Freescale Semiconductor, Inc., 2011. All rights reserved.
MPC5643L dual core architecture
4 MPC5643L dual core architecture
The MPC5643L, a SafeAssure solution, is a symmetrical dual core device based on Power Architecture™.
This device can run in one of two modes, lock step and decoupled parallel (DP) modes. The lock step mode
is for safety critical systems that require redundancy. The DP mode is for additional performance. The
increased performances possible in DP mode can be estimated in first approximation as about 1.6 the
performance of the LS mode at the same frequency.
In the DP mode, each CPU core and each connected channel run independently from the other one, and
redundancy checkers (RCCU) are disabled.
As you can see in the block diagram below, the core power architecture and core peripherals (DMA
controller, interrupt controller, crossbar bus system, memory protection unit, flash and RAM controllers,
peripheral bus bridge, system timers, and the watchdog timer) are replicated. This is referred to as the
sphere of replication.
This replication is one of the features that enables this chip to be used in a safety environment. In a dual
core mode, this replication adds a bit of additional programming for full operation.
Qorivva MPC5643L Dual Processor Mode, Rev. 0
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4.1 Block diagram
SRAM
PMU
SWT
ECSM
STM
INTC
DMA
Crossbar Switch
VLE
MMU
I-CACHE
SPE
e200z4
VLE
MMU
I-CACHE
SPE
e200z4
Memory Protection Unit
Crossbar Switch
Memory Protection Unit
AIPS Bridge
JTAG
Nexus
JTAG
Nexus
RC
RC
RC
RC
FlexRay
AIPS Bridge
TSENS T-Sens
ECC bits
Flash memory
ECC bits + logic
SIUL
MC
WakeUp
ADC
ADC
XOSC
BAM
SSCM
Secondary PLL
FMPLL
IRCOSC
CMU
CMU
CTU
PIT
FCCU
FlexPWM
FlexPWM
eTimer
eTimer
eTimer
FlexCAN
FlexCAN
LINFlex
LINFlex
DSPI
DSPI
DSPI CRC
CMU
SEMA4
PMU
SWT
ECSM
STM
INTC
DMA
SEMA4
SWG
ECC logic for SRAM ECC logic for SRAM
MPC5643L dual core architecture
4.2 Sphere of replication
The chip has two sets of peripherals around the core Power Architecture. With two sets of peripherals, the
software will need to initialize both sets of peripherals. This adds to the amount of code, but not necessarily
to the complexity of the code.
4.3 Memory map
If the system is in lock step mode, the sphere of replication peripherals have the identical memory map.
However, if the system is in dual processor mode, these same peripherals have unique addresses. On
core(0) the SoR peripherals remain at the LSM addresses, and the core(1) SoR peripherals are now visible
at a different set of addresses.
Qorivva MPC5643L Dual Processor Mode, Rev. 0
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Startup
If in DP mode, the SRAM location is modified from lock step (LS) mode. In LS mode, there is 128 KB of
contiguous SRAM beginning at location 0x4000_0000. In DP mode, the memory is split into two 64 KB
areas, 0x4000_0000 to 0x4000_FFFF and 0x5000_0000 to 0x5000_FFFF.
All the peripherals that are not included in the SoR maintain their memory-mapped addresses. There is no
change of the addresses for the non-SoR peripherals.
5Startup
5.1 Hardware setup
The decision of which mode the chip runs (LSM and DPM) is determined by a user bit, LSM_DPM, in the
shadow sector of the flash. If this bit is 0, then the unit starts up in DP mode.
0123456789101112131415
SWT XOSC LSM_
DPM
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
STCU Reserved
Figure 1. Shadow Flash — User Area
The shadow flash sector is located at 0x00F0_0000. The user configuration is located at offset 0x3E10.
This is also readable at flash register BIU4 (Flash_regs_base + 0x2C).
Refer to Section 6, “Changing between LSM and DPM” for detailed instructions on how to program the
shadow flash to switch between LSM and DPM.
5.2 Software setup
During the boot sequence, this dual core architecture is set up with one core being the master and the other
core designated as slave. That is to say, the primary core, Core(0), is run from reset and executes code,
which then sets up and releases reset to Core(1). At that time, the system then begins operating in dual
processor mode.
The System Status and Configuration Module (SSCM) is the control module for making the second core
operational. The registers of interest are:
• DPM Boot Register: Base + 0x0018
• Boot Key Register: Base + 0x001C
Qorivva MPC5643L Dual Processor Mode, Rev. 0
Freescale Semiconductor 4
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