NXP Semiconductors P89LPC9321 UM10310 User Manual

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UM10310

P89LPC9321 User manual

Rev. 2 — 1 November 2010 User manual

Document information

Info

Content

Keywords

P89LPC9321

 

 

Abstract

Technical information for the P89LPC9321 device

 

 

NXP Semiconductors

UM10310

 

 

P89LPC9321 User manual

Revision history

 

 

 

 

Rev

Date

Description

 

 

Section 2.3: added low speed oscillator information.

v.2

20101101

 

 

Section 15.1: added low speed oscillator information.

 

 

Section 15.3: added low speed oscillator information.

 

 

Section 15.5: added low speed oscillator information.

 

 

Table 8: added low speed oscillator information.

v.1

20081201

Initial version.

 

 

 

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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© NXP B.V. 2010. All rights reserved.

User manual

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2 of 139

NXP Semiconductors

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P89LPC9321 User manual

1. Introduction

The P89LPC9321 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC9321 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9321 in order to reduce component count, board space, and system cost.

1.1 Pin configuration

 

P2.0/ICB

1

 

28

P2.7/ICA

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.1/OCD

2

 

27

P2.6/OCA

 

 

 

 

 

 

 

 

 

 

 

 

 

P0.0/CMP2/KBI0

3

 

26

P0.1/CIN2B/KBI1

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.7/OCC

4

 

25

P0.2/CIN2A/KBI2

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.6/OCB

5

 

24

P0.3/CIN1B/KBI3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.5/RST

 

6

 

23

P0.4/CIN1A/KBI4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

7

P89LPC9321FDH

22

P0.5/CMPREF/KBI5

 

 

 

 

 

 

 

 

 

 

 

 

P3.1/XTAL1

8

 

21

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.0/XTAL2/CLKOUT

9

 

20

P0.6/CMP1/KBI6

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.4/INT1

 

10

 

19

P0.7/T1/KBI7

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.3/INT0/SDA

11

 

18

P1.0/TXD

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.2/T0/SCL

12

 

17

P1.1/RXD

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.2/MOSI

13

 

16

P2.5/SPICLK

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.3/MISO

14

 

15

P2.4/SS

 

 

 

 

 

 

 

 

 

002aae104

 

 

 

Fig 1. TSSOP28 pin configuration

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P1.7/OCC

 

P0.0/CMP2/KBI0

 

P2.1/OCD

 

P2.0/ICB

P2.7/ICA

 

P2.6/OCA

P0.1/CIN2B/KBI1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

4

 

3

 

2

1

28

 

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.6/OCB

5

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.5/RST

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

7

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.1/XTAL1

8

 

 

 

P89LPC9321FA

 

P3.0/XTAL2/CLKOUT

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.4/INT1

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.3/INT0/SDA

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

17

 

18

 

 

 

 

 

12

 

13

 

14

15

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.5/SPICLK

 

P1.1/RXD

P1.0/TXD

 

 

 

 

 

P1.2/T0/SCL

 

P2.2/MOSI

 

P2.3/MISO

 

P2.4/SS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25 P0.2/CIN2A/KBI2

24 P0.3/CIN1B/KBI3

23 P0.4/CIN1A/KBI4

22 P0.5/CMPREF/KBI5

21 VDD

20 P0.6/CMP1/KBI6

19 P0.7/T1/KBI7

002aae105

Fig 2. PLCC28 pin configuration

 

P2.0/ICB

1

 

28

P2.7/ICA

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.1/OCD

2

 

27

P2.6/OCA

 

 

 

 

 

 

 

 

 

 

 

 

 

P0.0/CMP2/KBI0

3

 

26

P0.1/CIN2B/KBI1

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.7/OCC

4

 

25

P0.2/CIN2A/KBI2

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.6/OCB

5

 

24

P0.3/CIN1B/KBI3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.5/RST

 

6

 

23

P0.4/CIN1A/KBI4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

7

P89LPC9321FN

22

P0.5/CMPREF/KBI5

 

 

 

 

 

 

 

 

 

 

 

 

P3.1/XTAL1

8

 

21

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.0/XTAL2/CLKOUT

9

 

20

P0.6/CMP1/KBI6

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.4/INT1

 

10

 

19

P0.7/T1/KBI7

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.3/INT0/SDA

11

 

18

P1.0/TXD

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.2/T0/SCL

12

 

17

P1.1/RXD

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.2/MOSI

13

 

16

P2.5/SPICLK

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.3/MISO

14

 

15

P2.4/SS

 

 

 

 

 

 

 

 

 

002aae106

 

 

 

Fig 3. DIP28 pin configuration

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User manual

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NXP Semiconductors

 

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P89LPC9321 User manual

 

1.2

Pin description

 

Table 1. Pin description

 

 

 

 

 

 

 

 

 

Symbol

 

Pin

 

Type

Description

 

P0.0 to P0.7

 

 

 

I/O

Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset

 

 

 

 

 

Port 0 latches are configured in the input only mode with the internal pull-up

 

 

 

 

 

disabled. The operation of Port 0 pins as inputs and outputs depends upon the

 

 

 

 

 

port configuration selected. Each port pin is configured independently. Refer to

 

 

 

 

 

Section 4.1 “Port configurations” for details.

 

 

 

 

 

 

The Keypad Interrupt feature operates with Port 0 pins.

 

 

 

 

 

 

All pins have Schmitt triggered inputs.

 

 

 

 

 

 

Port 0 also provides various special functions as described below:

 

 

 

 

 

 

P0.0/CMP2/ KBI0

3

 

I/O

P0.0 — Port 0 bit 0.

 

 

 

 

 

 

 

 

 

 

 

 

O

CMP2 — Comparator 2 output.

 

 

 

 

 

 

 

 

 

 

 

 

I

KBI0 — Keyboard input 0.

 

 

 

 

 

 

 

P0.1/CIN2B/

26

 

I/O

P0.1 — Port 0 bit 1.

 

KBI1

 

 

 

 

 

 

 

 

 

I

CIN2B — Comparator 2 positive input B.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

KBI1 — Keyboard input 1.

 

 

 

 

 

 

 

P0.2/CIN2A/

25

 

I/O

P0.2 — Port 0 bit 2.

 

KBI2

 

 

 

 

 

 

 

 

 

I

CIN2A — Comparator 2 positive input A.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

KBI2 — Keyboard input 2.

 

 

 

 

 

 

 

P0.3/CIN1B/

24

 

I/O

P0.3 — Port 0 bit 3. High current source.

 

KBI3

 

 

 

 

 

 

 

 

 

I

CIN1B — Comparator 1 positive input B.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

KBI3 — Keyboard input 3.

 

 

 

 

 

 

 

P0.4/CIN1A/

23

 

I/O

P0.4 — Port 0 bit 4. High current source.

 

KBI4

 

 

 

 

 

 

 

 

 

I

CIN1A — Comparator 1 positive input A.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

KBI4 — Keyboard input 4.

 

 

 

 

 

 

 

 

 

 

 

 

I

AD13 — ADC1 channel 3 analog input.

 

 

 

 

 

 

 

P0.5/CMPREF/

22

 

I/O

P0.5 — Port 0 bit 5. High current source.

 

KBI5

 

 

 

 

 

 

 

 

 

I

CMPREF — Comparator reference (negative) input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

KBI5 — Keyboard input 5.

 

 

 

 

 

 

 

P0.6/CMP1/ KBI6

20

 

I/O

P0.6 — Port 0 bit 6. High current source.

 

 

 

 

 

 

 

 

 

 

 

 

O

CMP1 — Comparator 1 output.

 

 

 

 

 

 

 

 

 

 

 

 

I

KBI6 — Keyboard input 6.

 

 

 

 

 

 

 

P0.7/T1/KBI7

19

 

I/O

P0.7 — Port 0 bit 7. High current source.

 

 

 

 

 

 

 

 

 

 

 

I/O

T1 — Timer/counter 1 external count input or overflow output.

 

 

 

 

 

 

 

 

 

 

 

I

KBI7 — Keyboard input 7.

 

 

 

 

 

 

 

P1.0 to P1.7

 

 

 

I/O, I

Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for

 

 

 

[1]

three pins as noted below. During reset Port 1 latches are configured in the input

 

 

 

 

 

only mode with the internal pull-up disabled. The operation of the configurable

 

 

 

 

 

Port 1 pins as inputs and outputs depends upon the port configuration selected.

 

 

 

 

 

Each of the configurable port pins are programmed independently. Refer to

 

 

 

 

 

Section 4.1 “Port configurations” for details. P1.2 to P1.3 are open drain when

 

 

 

 

 

used as outputs. P1.5 is input only.

 

 

 

 

 

 

All pins have Schmitt triggered inputs.

 

 

 

 

 

 

Port 1 also provides various special functions as described below:

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P89LPC9321 User manual

Table 1. Pin description …continued

 

 

 

 

 

 

 

 

 

Symbol

Pin

Type

 

Description

P1.0/TXD

18

I/O

P1.0

Port 1 bit 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

TXD — Transmitter output for serial port.

 

 

 

 

 

P1.1/RXD

17

I/O

P1.1

Port 1 bit 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

RXD — Receiver input for serial port.

 

 

 

 

 

P1.2/T0/SCL

12

I/O

P1.2

Port 1 bit 2 (open-drain when used as output).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

T0 — Timer/counter 0 external count input or overflow output (open-drain when

 

 

 

 

 

 

 

 

used as output).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

SCL — I2C-bus serial clock input/output.

 

 

 

 

 

11

I/O

P1.3

Port 1 bit 3 (open-drain when used as output).

P1.3/INT0/SDA

 

 

 

 

 

 

I

INT0

External interrupt 0 input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

SDA — I2C-bus serial data input/output.

 

 

 

 

 

10

I/O

P1.4

Port 1 bit 4. High current source.

P1.4/INT1

 

 

 

 

 

 

 

I

INT1

External interrupt 1 input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

I

P1.5

Port 1 bit 5 (input only).

P1.5/RST

 

 

 

 

 

 

 

I

RST

External Reset input during power-on or if selected via UCFG1. When

 

 

 

 

 

 

 

 

functioning as a reset input, a LOW on this pin resets the microcontroller, causing

 

 

 

 

 

 

 

 

I/O ports and peripherals to take on their default states, and the processor begins

 

 

 

 

 

 

 

 

execution at address 0. Also used during a power-on sequence to force ISP

 

 

 

 

 

 

 

 

mode.

 

 

 

 

 

P1.6/OCB

5

I/O

P1.6

Port 1 bit 6. High current source.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

OCB — Output Compare B

 

 

 

 

 

P1.7/OCC

4

I/O

P1.7

Port 1 bit 7. High current source.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

OCC — Output Compare C.

 

 

 

 

P2.0 to P2.7

 

I/O

Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset

 

 

 

 

 

 

 

 

Port 2 latches are configured in the input only mode with the internal pull-up

 

 

 

 

 

 

 

 

disabled. The operation of Port 2 pins as inputs and outputs depends upon the

 

 

 

 

 

 

 

 

port configuration selected. Each port pin is configured independently. Refer to

 

 

 

 

 

 

 

 

Section 4.1 “Port configurations” for details.

 

 

 

 

 

 

 

 

All pins have Schmitt triggered inputs.

 

 

 

 

 

 

 

 

Port 2 also provides various special functions as described below:

 

 

 

 

 

P2.0/ICB

1

I/O

P2.0

Port 2 bit 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

ICB — Input Capture B.

 

 

 

 

 

P2.1/OCD

2

I/O

P2.1

Port 2 bit 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

OCD — Output Compare D.

 

 

 

 

 

P2.2/MOSI

13

I/O

P2.2

Port 2 bit 2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

MOSI — SPI master out slave in. When configured as master, this pin is output;

 

 

 

 

 

 

 

 

when configured as slave, this pin is input.

P2.3/MISO

14

I/O

P2.3

Port 2 bit 3.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

MISO — When configured as master, this pin is input, when configured as slave,

 

 

 

 

 

 

 

 

this pin is output.

 

 

 

 

 

 

 

 

 

 

 

 

 

15

I/O

P2.4

Port 2 bit 4.

P2.4/SS

 

 

 

 

 

 

 

I/O

SS

SPI Slave select.

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User manual

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NXP Semiconductors

 

UM10310

 

 

 

P89LPC9321 User manual

Table 1. Pin description …continued

 

 

 

 

 

Symbol

Pin

Type

Description

P2.5/SPICLK

16

I/O

P2.5 — Port 2 bit 5.

 

 

 

 

 

 

I/O

SPICLK — SPI clock. When configured as master, this pin is output; when

 

 

 

configured as slave, this pin is input.

 

 

 

 

P2.6/OCA

27

I/O

P2.6 — Port 2 bit 6.

 

 

 

 

 

 

O

OCA — Output Compare A.

 

 

 

 

P2.7/ICA

28

I/O

P2.7 — Port 2 bit 7.

 

 

 

 

 

 

I

ICA — Input Capture A.

 

 

 

 

P3.0 to P3.1

 

I/O

Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset

 

 

 

Port 3 latches are configured in the input only mode with the internal pull-up

 

 

 

disabled. The operation of Port 3 pins as inputs and outputs depends upon the

 

 

 

port configuration selected. Each port pin is configured independently. Refer to

 

 

 

Section 4.1 “Port configurations” for details.

 

 

 

All pins have Schmitt triggered inputs.

 

 

 

Port 3 also provides various special functions as described below:

 

 

 

 

P3.0/XTAL2/

9

I/O

P3.0 — Port 3 bit 0.

CLKOUT

 

 

 

 

O

XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is

 

 

 

 

 

selected via the flash configuration.

 

 

 

 

 

 

O

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).

 

 

 

It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or

 

 

 

external clock input, except when XTAL1/XTAL2 are used to generate clock

 

 

 

source for the RTC/system timer.

 

 

 

 

P3.1/XTAL1

8

I/O

P3.1 — Port 3 bit 1.

 

 

 

 

 

 

I

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

 

 

 

selected via the flash configuration). It can be a port pin if internal RC oscillator or

 

 

 

watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not

 

 

 

used to generate the clock for the RTC/system timer.

 

 

 

 

VSS

7

I

Ground: 0 V reference.

 

 

 

 

VDD

21

I

Power supply: This is the power supply voltage for normal operation as well as

 

 

 

Idle and Power-down modes.

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

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NXP Semiconductors

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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P89LPC9321 User manual

1.3 Functional diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

VSS

 

 

 

 

 

 

 

 

 

KBI0

 

 

CMP2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TXD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KBI1

 

 

CIN2B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RXD

SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KBI2

 

 

CIN2A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KBI3

 

 

CIN1B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT0

 

 

SDA

 

 

 

 

 

 

PORT 0

 

 

 

 

 

 

PORT 1

 

 

 

KBI4

 

 

CIN1A

 

 

 

 

 

 

 

 

 

 

 

INT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KBI5

 

 

CMPREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KBI6

 

 

CMP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OCB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KBI7

 

 

T1

 

 

 

 

 

P89LPC9321

 

 

 

 

 

OCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT

 

 

XTAL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICB

 

 

 

 

 

 

 

 

 

 

 

PORT 3

 

 

 

 

 

 

 

 

 

OCD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOSI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MISO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PORT 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPICLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OCA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

002aae103

 

 

 

 

 

 

 

 

 

Fig 4. Functional diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UM10310

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2010. All rights reserved.

User manual

Rev. 2 — 1 November 2010

8 of 139

NXP Semiconductors

UM10310

 

P89LPC9321 User manual

1.4 Block diagram

 

 

 

P89LPC9321

 

 

 

 

 

 

ACCELERATED 2-CLOCK 80C51 CPU

 

 

 

 

8 kB

 

UART

TXD

 

 

 

 

RXD

 

 

 

CODE FLASH

 

 

 

 

internal bus

 

 

 

 

 

 

 

 

 

 

256-BYTE

 

I2C-BUS

SCL

 

 

 

DATA RAM

 

SDA

 

 

 

 

 

 

 

 

 

 

 

SPICLK

 

 

 

512-BYTE

 

SPI

MOSI

 

 

 

AUXILIARY RAM

 

MISO

 

 

 

 

 

 

 

 

 

 

 

SS

 

 

 

512-BYTE

 

REAL-TIME CLOCK/

 

 

 

 

 

SYSTEM TIMER

 

 

 

 

DATA EEPROM

 

 

 

 

 

 

 

 

 

 

 

 

 

TIMER 0

T0

 

P3[1:0]

 

PORT 3

 

TIMER 1

T1

 

 

CONFIGURABLE I/Os

 

 

 

 

 

 

 

 

CMP2

 

 

 

 

 

 

 

 

 

PORT 2

 

ANALOG

CIN2B

 

P2[7:0]

 

 

CIN2A

 

 

CONFIGURABLE I/Os

 

 

 

 

 

COMPARATORS

CMP1

 

 

 

 

 

 

CIN1A

 

P1[7:0]

 

PORT 1

 

 

CIN1B

 

 

CONFIGURABLE I/Os

 

 

OCA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CCU (CAPTURE/

OCB

 

P0[7:0]

 

PORT 0

 

OCC

 

 

 

COMPARE UNIT)

 

 

CONFIGURABLE I/Os

 

OCD

 

 

 

 

 

ICA

 

 

 

 

 

 

 

 

 

 

 

 

ICB

 

 

 

KEYPAD

 

 

 

 

 

 

INTERRUPT

 

 

 

 

 

 

WATCHDOG TIMER

 

 

 

 

 

 

AND OSCILLATOR

 

 

 

 

 

 

PROGRAMMABLE

CPU

 

 

 

 

 

OSCILLATOR DIVIDER

clock

 

 

 

CRYSTAL

XTAL1

 

ON-CHIP RC

POWER MONITOR

 

 

 

CONFIGURABLE

OSCILLATOR

(POWER-ON RESET,

 

 

OR

 

 

 

 

OSCILLATOR

WITH CLOCK

BROWNOUT RESET)

 

 

RESONATOR

XTAL2

 

 

 

DOUBLER

 

 

 

 

 

 

 

 

 

 

 

 

002aae102

 

Fig 5.

Block diagram

 

 

 

 

UM10310

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2010. All rights reserved.

User manual

Rev. 2 — 1 November 2010

9 of 139

NXP Semiconductors

UM10310

 

P89LPC9321 User manual

1.5 Special function registers

Remark: SFR accesses are restricted in the following ways:

User must not attempt to access any SFR locations not defined.

Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

‘0’ must be written with ‘0’, and will return a ‘0’ when read.

‘1’ must be written with ‘1’, and will return a ‘1’ when read.

UM10310

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2010. All rights reserved.

User manual

Rev. 2 — 1 November 2010

10 of 139

manual User

2010 November 1 — 2 .Rev

139 of 11

UM10310

.disclaimers legal to subject is document this in provided information All

.reserved rights All .2010 .V.B NXP ©

Table 2.

Special function registers

 

 

 

 

 

 

 

 

 

* indicates SFRs that are bit addressable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

Description

SFR

Bit functions and addresses

 

 

 

 

 

Reset value

 

 

 

addr.

MSB

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

E7

E6

E5

E4

E3

E2

E1

E0

 

 

ACC*

 

Accumulator

E0H

 

 

 

 

 

 

 

 

00

0000 0000

AUXR1

 

Auxiliary

A2H

CLKLP

EBRR

ENT1

ENT0

SRST

0

-

DPS

00

0000 00x0

 

 

function

 

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

F7

F6

F5

F4

F3

F2

F1

F0

 

 

B*

 

B register

F0H

 

 

 

 

 

 

 

 

00

0000 0000

BRGR0[2]

 

Baud rate

BEH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

generator 0

 

 

 

 

 

 

 

 

 

 

 

 

 

rate low

 

 

 

 

 

 

 

 

 

 

 

BRGR1[2]

 

Baud rate

BFH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

generator 0

 

 

 

 

 

 

 

 

 

 

 

 

 

rate high

 

 

 

 

 

 

 

 

 

 

 

BRGCON

 

Baud rate

BDH

-

-

-

-

-

-

SBRGS

BRGEN

00[2]

xxxx xx00

 

 

generator 0

 

 

 

 

 

 

 

 

 

 

 

 

 

control

 

 

 

 

 

 

 

 

 

 

 

CCCRA

 

Capture

EAH

ICECA2

ICECA1

ICECA0

ICESA

ICNFA

FCOA

OCMA1

OCMA0

00

0000 0000

 

 

compare A

 

 

 

 

 

 

 

 

 

 

 

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

CCCRB

 

Capture

EBH

ICECB2

ICECB1

ICECB0

ICESB

ICNFB

FCOB

OCMB1

OCMB0

00

0000 0000

 

 

compare B

 

 

 

 

 

 

 

 

 

 

 

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

CCCRC

 

Capture

ECH

-

-

-

-

-

FCOC

OCMC1

OCMC0

00

xxxx x000

 

 

compare C

 

 

 

 

 

 

 

 

 

 

 

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

CCCRD

 

Capture

EDH

-

-

-

-

-

FCOD

OCMD1

OCMD0

00

xxxx x000

 

 

compare D

 

 

 

 

 

 

 

 

 

 

 

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

CMP1

 

Comparator 1

ACH

-

-

CE1

CP1

CN1

OE1

CO1

CMF1

00[1]

xx00 0000

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

CMP2

 

Comparator 2

ADH

-

-

CE2

CP2

CN2

OE2

CO2

CMF2

00[1]

xx00 0000

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

DEECON

 

Data EEPROM

F1H

EEIF

HVERR

ECTL1

ECTL0

-

EWERR1

EWERR0

EADR8

08

00001000

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Semiconductors NXP

manual User P89LPC9321

UM10310

manual User

2010 November 1 — 2 .Rev

139 of 12

UM10310

.disclaimers legal to subject is document this in provided information All

.reserved rights All .2010 .V.B NXP ©

Table 2.

Special function registers …continued

 

 

 

 

 

 

 

 

 

* indicates SFRs that are bit addressable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

Description

SFR

Bit functions and addresses

 

 

 

 

 

Reset value

 

 

 

addr.

MSB

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

DEEDAT

 

Data EEPROM

F2H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

data register

 

 

 

 

 

 

 

 

 

 

 

DEEADR

 

Data EEPROM

F3H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

address

 

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

DIVM

 

CPU clock

95H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

divide-by-M

 

 

 

 

 

 

 

 

 

 

 

 

 

control

 

 

 

 

 

 

 

 

 

 

 

DPTR

 

Data pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

(2 bytes)

 

 

 

 

 

 

 

 

 

 

 

DPH

 

Data pointer

83H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

high

 

 

 

 

 

 

 

 

 

 

 

DPL

 

Data pointer

82H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

low

 

 

 

 

 

 

 

 

 

 

 

FMADRH

 

Program flash

E7H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

address high

 

 

 

 

 

 

 

 

 

 

 

FMADRL

 

Program flash

E6H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

address low

 

 

 

 

 

 

 

 

 

 

 

FMCON

 

Program flash

E4H

BUSY

-

-

-

HVA

HVE

SV

OI

70

0111 0000

 

 

control (Read)

 

 

 

 

 

 

 

 

 

 

 

 

 

Program flash

E4H

FMCMD.7

FMCMD.6

FMCMD.5

FMCMD.4

FMCMD.3

FMCMD.2

FMCMD.1

FMCMD.0

 

 

 

 

control (Write)

 

 

 

 

 

 

 

 

 

 

 

FMDATA

 

Program flash

E5H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

data

 

 

 

 

 

 

 

 

 

 

 

I2ADR

 

I2C-bus slave

DBH

I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

GC

00

0000 0000

 

 

address

 

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

DF

DE

DD

DC

DB

DA

D9

D8

 

 

I2CON*

 

I2C-bus control

D8H

-

I2EN

STA

STO

SI

AA

-

CRSEL

00

x000 00x0

 

 

register

 

 

 

 

 

 

 

 

 

 

 

I2DAT

 

I2C-bus data

DAH

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Semiconductors NXP

manual User P89LPC9321

UM10310

manual User

2010 November 1 — 2 .Rev

139 of 13

UM10310

.disclaimers legal to subject is document this in provided information All

.reserved rights All .2010 .V.B NXP ©

Table 2.

Special function registers …continued

 

 

 

 

 

 

 

 

 

* indicates SFRs that are bit addressable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

Description

SFR

Bit functions and addresses

 

 

 

 

 

Reset value

 

 

 

addr.

MSB

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

I2SCLH

 

Serial clock

DDH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

generator/SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

duty cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

register high

 

 

 

 

 

 

 

 

 

 

 

I2SCLL

 

Serial clock

DCH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

generator/SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

duty cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

register low

 

 

 

 

 

 

 

 

 

 

 

I2STAT

 

I2C-bus status

D9H

STA.4

STA.3

STA.2

STA.1

STA.0

0

0

0

F8

1111 1000

 

 

register

 

 

 

 

 

 

 

 

 

 

 

ICRAH

 

Input capture A

ABH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

register high

 

 

 

 

 

 

 

 

 

 

 

ICRAL

 

Input capture A

AAH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

register low

 

 

 

 

 

 

 

 

 

 

 

ICRBH

 

Input capture B

AFH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

register high

 

 

 

 

 

 

 

 

 

 

 

ICRBL

 

Input capture B

AEH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

register low

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

AF

AE

AD

AC

AB

AA

A9

A8

 

 

IEN0*

 

Interrupt

A8H

EA

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

00

0000 0000

 

 

enable 0

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

EF

EE

ED

EC

EB

EA

E9

E8

 

 

IEN1*

 

Interrupt

E8H

EIEE

EST

-

ECCU

ESPI

EC

EKBI

EI2C

00[1]

00x0 0000

 

 

enable 1

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

BF

BE

BD

BC

BB

BA

B9

B8

 

 

IP0*

 

Interrupt

B8H

-

PWDRT

PBO

PS/PSR

PT1

PX1

PT0

PX0

00[1]

x000 0000

 

 

priority 0

 

 

 

 

 

 

 

 

 

 

 

IP0H

 

Interrupt

B7H

-

PWDRTH

PBOH

PSH/

PT1H

PX1H

PT0H

PX0H

00[1]

x000 0000

 

 

priority 0 high

 

 

 

 

PSRH

 

 

 

 

 

 

 

 

Bit address

FF

FE

FD

FC

FB

FA

F9

F8

 

 

IP1*

 

Interrupt

F8H

PIEE

PST

-

PCCU

PSPI

PC

PKBI

PI2C

00[1]

00x0 0000

 

 

priority 1

 

 

 

 

 

 

 

 

 

 

 

IP1H

 

Interrupt

F7H

PIEEH

PSTH

-

PCCUH

PSPIH

PCH

PKBIH

PI2CH

00[1]

00x0 0000

 

 

priority 1 high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Semiconductors NXP

manual User P89LPC9321

UM10310

manual User

2010 November 1 — 2 .Rev

139 of 14

UM10310

.disclaimers legal to subject is document this in provided information All

.reserved rights All .2010 .V.B NXP ©

Table 2.

Special function registers …continued

 

 

 

 

 

 

 

 

 

* indicates SFRs that are bit addressable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

Description

SFR

Bit functions and addresses

 

 

 

 

 

Reset value

 

 

 

addr.

MSB

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

KBCON

 

Keypad control

94H

-

-

-

-

-

-

PATN

KBIF

00[1]

xxxx xx00

 

 

register

 

 

 

 

 

 

 

_SEL

 

 

 

KBMASK

 

Keypad

86H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

interrupt mask

 

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

KBPATN

 

Keypad pattern

93H

 

 

 

 

 

 

 

 

FF

1111 1111

 

 

register

 

 

 

 

 

 

 

 

 

 

 

OCRAH

 

Output

EFH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

compare A

 

 

 

 

 

 

 

 

 

 

 

 

 

register high

 

 

 

 

 

 

 

 

 

 

 

OCRAL

 

Output

EEH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

compare A

 

 

 

 

 

 

 

 

 

 

 

 

 

register low

 

 

 

 

 

 

 

 

 

 

 

OCRBH

 

Output

FBH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

compare B

 

 

 

 

 

 

 

 

 

 

 

 

 

register high

 

 

 

 

 

 

 

 

 

 

 

OCRBL

 

Output

FAH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

compare B

 

 

 

 

 

 

 

 

 

 

 

 

 

register low

 

 

 

 

 

 

 

 

 

 

 

OCRCH

 

Output

FDH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

compare C

 

 

 

 

 

 

 

 

 

 

 

 

 

register high

 

 

 

 

 

 

 

 

 

 

 

OCRCL

 

Output

FCH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

compare C

 

 

 

 

 

 

 

 

 

 

 

 

 

register low

 

 

 

 

 

 

 

 

 

 

 

OCRDH

 

Output

FFH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

compare D

 

 

 

 

 

 

 

 

 

 

 

 

 

register high

 

 

 

 

 

 

 

 

 

 

 

OCRDL

 

Output

FEH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

compare D

 

 

 

 

 

 

 

 

 

 

 

 

 

register low

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

87

86

85

84

83

82

81

80

 

 

P0*

 

Port 0

80H

T1/KB7

CMP1

CMPREF

CIN1A

CIN1B

CIN2A

CIN2B

CMP2

[1]

 

 

 

 

 

 

/KB6

/KB5

/KB4

/KB3

/KB2

/KB1

/KB0

 

 

 

 

Bit address

97

96

95

94

93

92

91

90

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Table 2.

Special function registers …continued

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

* indicates SFRs that are bit addressable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

Description

SFR

Bit functions and addresses

 

 

 

 

 

 

 

 

 

 

Reset value

 

 

 

addr.

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1*

 

Port 1

90H

OCC

OCB

 

 

 

 

 

 

 

 

 

 

T0/SCL

RXD

TXD

[1]

 

 

RST

INT1

INT0/SDA

 

 

 

Bit address

A7

A6

 

A5

 

 

A4

A3

A2

A1

A0

 

 

P2*

 

Port 2

A0H

ICA

OCA

SPICLK

 

 

 

 

MISO

MOSI

OCD

ICB

[1]

 

 

SS

 

 

 

Bit address

B7

B6

 

B5

 

 

B4

B3

B2

B1

B0

 

 

P3*

 

Port 3

B0H

-

-

-

 

-

 

 

-

-

XTAL1

XTAL2

[1]

 

P0M1

 

Port 0 output

84H

(P0M1.7)

(P0M1.6)

(P0M1.5)

(P0M1.4)

(P0M1.3)

(P0M1.2)

(P0M1.1)

(P0M1.0)

FF[1]

1111 1111

 

 

mode 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P0M2

 

Port 0 output

85H

(P0M2.7)

(P0M2.6)

(P0M2.5)

(P0M2.4)

(P0M2.3)

(P0M2.2)

(P0M2.1)

(P0M2.0)

00[1]

0000 0000

 

 

mode 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1M1

 

Port 1 output

91H

(P1M1.7)

(P1M1.6)

-

 

(P1M1.4)

(P1M1.3)

(P1M1.2)

(P1M1.1)

(P1M1.0)

D3[1]

11x1 xx11

 

 

mode 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1M2

 

Port 1 output

92H

(P1M2.7)

(P1M2.6)

-

 

(P1M2.4)

(P1M2.3)

(P1M2.2)

(P1M2.1)

(P1M2.0)

00[1]

00x0 xx00

 

 

mode 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2M1

 

Port 2 output

A4H

(P2M1.7)

(P2M1.6)

(P2M1.5)

(P2M1.4)

(P2M1.3)

(P2M1.2)

(P2M1.1)

(P2M1.0)

FF[1]

1111 1111

 

 

mode 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2M2

 

Port 2 output

A5H

(P2M2.7)

(P2M2.6)

(P2M2.5)

(P2M2.4)

(P2M2.3)

(P2M2.2)

(P2M2.1)

(P2M2.0)

00[1]

0000 0000

 

 

mode 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3M1

 

Port 3 output

B1H

-

-

-

 

-

 

 

-

-

(P3M1.1)

(P3M1.0)

03[1]

xxxx xx11

 

 

mode 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3M2

 

Port 3 output

B2H

-

-

-

 

-

 

 

-

-

(P3M2.1)

(P3M2.0)

00[1]

xxxx xx00

 

 

mode 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCON

 

Power control

87H

SMOD1

SMOD0

-

 

 

BOI

GF1

GF0

PMOD1

PMOD0

00

0000 0000

 

 

register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCONA

 

Power control

B5H

RTCPD

DEEPD

VCPD

-

 

 

I2PD

SPPD

SPD

CCUPD

00[1]

0000 0000

 

 

register A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

D7

D6

 

D5

 

 

D4

D3

D2

D1

D0

 

 

PSW*

 

Program status

D0H

CY

AC

 

F0

 

RS1

RS0

OV

F1

P

00

0000 0000

 

 

word

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PT0AD

 

Port 0 digital

F6H

-

-

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

-

00

xx00 000x

 

 

input disable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RSTSRC

 

Reset source

DFH

-

BOIF

BOF

 

POF

R_BK

R_WD

R_SF

R_EX

[3]

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RTCCON

 

RTC control

D1H

RTCF

RTCS1

RTCS0

-

 

 

-

-

ERTC

RTCEN

60[1][6]

011x xx00

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Table 2.

Special function registers …continued

 

 

 

 

 

 

 

 

 

* indicates SFRs that are bit addressable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

Description

SFR

Bit functions and addresses

 

 

 

 

 

Reset value

 

 

 

addr.

MSB

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

RTCH

 

RTC register

D2H

 

 

 

 

 

 

 

 

00[6]

0000 0000

 

 

high

 

 

 

 

 

 

 

 

 

 

 

RTCL

 

RTC register

D3H

 

 

 

 

 

 

 

 

00[6]

0000 0000

 

 

low

 

 

 

 

 

 

 

 

 

 

 

SADDR

 

Serial port

A9H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

address

 

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

SADEN

 

Serial port

B9H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

address enable

 

 

 

 

 

 

 

 

 

 

 

SBUF

 

Serial Port data

99H

 

 

 

 

 

 

 

 

xx

xxxx xxxx

 

 

buffer register

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

9F

9E

9D

9C

9B

9A

99

98

 

 

SCON*

 

Serial port

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

00

0000 0000

 

 

control

 

 

 

 

 

 

 

 

 

 

 

SSTAT

 

Serial port

BAH

DBMOD

INTLO

CIDIS

DBISEL

FE

BR

OE

STINT

00

0000 0000

 

 

extended

 

 

 

 

 

 

 

 

 

 

 

 

 

status register

 

 

 

 

 

 

 

 

 

 

 

SP

 

Stack pointer

81H

 

 

 

 

 

 

 

 

07

0000 0111

SPCTL

 

SPI control

E2H

SSIG

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

04

0000 0100

 

 

register

 

 

 

 

 

 

 

 

 

 

 

SPSTAT

 

SPI status

E1H

SPIF

WCOL

-

-

-

-

-

-

00

00xx xxxx

 

 

register

 

 

 

 

 

 

 

 

 

 

 

SPDAT

 

SPI data

E3H

 

 

 

 

 

 

 

 

00

0000 0000

 

 

register

 

 

 

 

 

 

 

 

 

 

 

TAMOD

 

Timer 0 and 1

8FH

-

-

-

T1M2

-

-

-

T0M2

00

xxx0 xxx0

 

 

auxiliary mode

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit address

8F

8E

8D

8C

8B

8A

89

88

 

 

TCON*

 

Timer 0 and 1

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00

0000 0000

 

 

control

 

 

 

 

 

 

 

 

 

 

 

TCR20*

 

CCU control

C8H

PLEEN

HLTRN

HLTEN

ALTCD

ALTAB

TDIR2

TMOD21

TMOD20

00

0000 0000

 

 

register 0

 

 

 

 

 

 

 

 

 

 

 

TCR21

 

CCU control

F9H

TCOU2

-

-

-

PLLDV.3

PLLDV.2

PLLDV.1

PLLDV.0

00

0xxx 0000

 

 

register 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Semiconductors NXP

manual User P89LPC9321

UM10310

manual User

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Table 2.

Special function registers …continued

 

 

 

 

 

 

 

 

 

* indicates SFRs that are bit addressable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

Description

SFR

Bit functions and addresses

 

 

 

 

 

Reset value

 

 

 

addr.

MSB

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

 

TH0

 

Timer 0 high

8CH

 

 

 

 

 

 

 

 

00

0000 0000

TH1

 

Timer 1 high

8DH

 

 

 

 

 

 

 

 

00

0000 0000

TH2

 

CCU timer high

CDH

 

 

 

 

 

 

 

 

00

0000 0000

TICR2

 

CCU interrupt

C9H

TOIE2

TOCIE2D

TOCIE2C

TOCIE2B

TOCIE2A

-

TICIE2B

TICIE2A

00

0000 0x00

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

TIFR2

 

CCU interrupt

E9H

TOIF2

TOCF2D

TOCF2C

TOCF2B

TOCF2A

-

TICF2B

TICF2A

00

0000 0x00

 

 

flag register

 

 

 

 

 

 

 

 

 

 

 

TISE2

 

CCU interrupt

DEH

-

-

-

-

-

ENCINT.2

ENCINT.1

ENCINT.0

00

xxxx x000

 

 

status encode

 

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

TL0

 

Timer 0 low

8AH

 

 

 

 

 

 

 

 

00

0000 0000

TL1

 

Timer 1 low

8BH

 

 

 

 

 

 

 

 

00

0000 0000

TL2

 

CCU timer low

CCH

 

 

 

 

 

 

 

 

00

0000 0000

TMOD

 

Timer 0 and 1

89H

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00

0000 0000

 

 

mode

 

 

 

 

 

 

 

 

 

 

 

TOR2H

 

CCU reload

CFH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

register high

 

 

 

 

 

 

 

 

 

 

 

TOR2L

 

CCU reload

CEH

 

 

 

 

 

 

 

 

00

0000 0000

 

 

register low

 

 

 

 

 

 

 

 

 

 

 

TPCR2H

 

Prescaler

CBH

-

-

-

-

-

-

TPCR2H.1

TPCR2H.0

00

xxxx xx00

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

 

 

high

 

 

 

 

 

 

 

 

 

 

 

TPCR2L

 

Prescaler

CAH

TPCR2L.7

TPCR2L.6

TPCR2L.5

TPCR2L.4

TPCR2L.3

TPCR2L.2

TPCR2L.1

TPCR2L.0

00

0000 0000

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

 

 

low

 

 

 

 

 

 

 

 

 

 

 

TRIM

 

Internal

96H

RCCLK

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5][6]

 

 

 

oscillator trim

 

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

WDCON

 

Watchdog

A7H

PRE2

PRE1

PRE0

-

-

WDRUN

WDTOF

WDCLK

[4][6]

 

 

 

control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Semiconductors NXP

manual User P89LPC9321

UM10310

manual User

2010 November 1 — 2 .Rev

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Table 2.

Special function registers …continued

 

 

 

* indicates SFRs that are bit addressable.

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

Description

SFR

Bit functions and addresses

 

Reset value

 

 

 

addr.

 

MSB

LSB

Hex

Binary

 

 

 

 

 

WDL

 

Watchdog load

C1H

 

 

 

FF

1111 1111

WFEED1

 

Watchdog

C2H

 

 

 

 

 

 

 

feed 1

 

 

 

 

 

 

WFEED2

 

Watchdog

C3H

 

 

 

 

 

 

 

feed 2

 

 

 

 

 

 

[1]All ports are in input only (high-impedance) state after power-up.

[2]BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3]The RSTSRC register reflects the cause of the UM10310 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000.

[4]After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF.

[5]On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]The only reset sources that affect these SFRs are power-on reset and watchdog reset.

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Table 3. Extended special function registers[1]

Name

Description

SFR

Bit functions and addresses

 

 

 

 

 

Reset value

 

 

addr.

MSB

 

 

 

 

 

 

LSB

Hex

Binary

 

 

 

 

 

 

 

 

 

BODCFG

BOD

FFC8H

-

-

-

-

-

-

BOICFG1

BOICFG0

[2]

 

 

configuration

 

 

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

CLKCON

CLOCK Control

FFDEH

CLKOK

-

-

XTALWD

CLKDBL

FOSC2

FOSC1

FOSC0

[3]

1000 0100

 

register

 

 

 

 

 

 

 

 

 

 

 

PGACON1

PGA1 control

FFE1H

ENPGA1

PGASEL1

PGASEL1

PGATRIM

-

-

PGAG11

PGAG10

00

0000 0000

 

register

 

 

1

0

1

 

 

 

 

 

 

PGACON1B

PGA1 control

FFE4H

-

-

-

-

-

-

-

PGAENO

00

0000 0000

 

register B

 

 

 

 

 

 

 

 

FF1

 

 

PGA1TRIM8X16X

PGA1 trim

FFE3H

16XTRIM3

16XTRIM2

16XTRIM1

16XTRIM0

8XTRIM3

8XTRIM2

8XTRIM1

8XTRIM0

[4]

 

 

register

 

 

 

 

 

 

 

 

 

 

 

PGA1TRIM2X4X

PGA1 trim

FFE2H

4XTRIM3

4XTRIM2

4XTRIM1

4XTRIM0

2XTRIM3

2XTRIM2

2XTRIM1

2XTRIM0

[4]

 

 

register

 

 

 

 

 

 

 

 

 

 

 

RTCDATH

Real-time clock

FFBFH

 

 

 

 

 

 

 

 

00

0000 0000

 

data register

 

 

 

 

 

 

 

 

 

 

 

 

high

 

 

 

 

 

 

 

 

 

 

 

RTCDATL

Real-time clock

FFBEH

 

 

 

 

 

 

 

 

00

0000 0000

 

data register low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[1]Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs.

[2]The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset.

[3]CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.

[4]On power-on reset and watchdog reset, the PGAxTRIM8X16X and PGAxTRIM2X4X registers are initialized with a factory preprogrammed value. Other resets will not cause initialization.

Semiconductors NXP

manual User P89LPC9321

UM10310

NXP Semiconductors

UM10310

 

P89LPC9321 User manual

1.6 Memory organization

 

FF00h

IAP entry-

 

FFEFh

points

ISP CODE 1FFFh (512B)(1)

1E00h

SECTOR 7

1C00h

1BFFh

SECTOR 6

1800h

17FFh

SECTOR 5

1400h

13FFh

SECTOR 4

1000h

0FFFh

SECTOR 3

0C00h

0BFFh

SECTOR 2

0800h

07FFh

SECTOR 1

0400h

03FFh

SECTOR 0

0000h

read-protected IAP calls only

IDATA routines entry points for:

-51 ASM. code -C code

ISP serial loader entry points for:

-UART (auto-baud) -I2C, SPI, etc.(1)

FFEFh

 

 

 

 

 

 

FFh

 

 

 

SPECIAL FUNCTION

IDATA (incl. DATA)

 

 

 

 

 

FF1Fh

entry

 

 

128 BYTES ON-CHIP

 

 

 

REGISTERS

 

 

 

 

DATA MEMORY (STACK

 

 

points

 

 

 

 

(DIRECTLY ADDRESSABLE)

 

FF00h

 

AND INDIR. ADDR.)

80h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

7Fh

1FFFh

 

 

 

 

 

128 BYTES ON-CHIP

 

 

 

 

 

 

DATA MEMORY (STACK,

 

 

 

 

 

 

 

DIRECT AND INDIR. ADDR.)

 

 

 

 

 

 

 

4 REG. BANKS R[7:0]

00h

1E00h

 

 

 

 

 

 

 

 

 

 

 

data memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(DATA, IDATA)

 

 

 

 

 

 

FFFFh

 

 

 

EXTENDED SFRs

 

 

 

 

 

 

 

 

 

 

 

FFB0h

 

 

 

 

RESERVED

 

 

 

 

 

 

 

 

01FFh

 

01FFh

 

 

 

XDATA

 

DATA EEPROM

 

 

 

 

 

 

 

 

 

(512 BYTES)

 

 

(512 BYTES)

 

 

 

 

[SFR ACCESS]

 

 

 

 

 

 

0000h

0000h

 

 

 

 

 

 

data EEPROM

002aae090

Fig 6. P89LPC9321 memory map

The various P89LPC9321 memory spaces are as follows:

DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

XDATA — ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC9321 has 512 bytes of on-chip XDATA memory, plus extended SFRs located in XDATA.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9321 has 8 kB of on-chip Code memory.

The P89LPC9321 also has 512 bytes of on-chip Data EEPROM that is accessed via SFRs (see Section Section 17 “Data EEPROM”).

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Table 4.

Data RAM arrangement

 

 

 

 

 

 

Type

Data RAM

Size (bytes)

 

DATA

Directly and indirectly addressable memory

128

 

 

 

 

 

IDATA

Indirectly addressable memory

256

 

 

 

 

 

XDATA

Auxiliary (‘External Data’) on-chip memory that is accessed using

512

 

 

the MOVX instructions

 

 

 

 

 

2. Clocks

2.1 Enhanced CPU

The P89LPC9321 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitions

The P89LPC9321 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency (see Figure 8 and Section 2.10 “CPU Clock (CCLK) modification: DIVM register”). Note: fosc is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.The clock doubler option, when enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is CCLK2.

2.2.1Oscillator Clock (OSCCLK)

The P89LPC9351 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source.

2.3 External crystal oscillator option

The external crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK and RTC. Low speed oscillator option can be the clock source of WDT.

2.3.1Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

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2.3.2Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.3.3High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.

2.4Clock output

The P89LPC9321 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock and Watchdog Timer are not using the crystal oscillator as their clock source. This allows external devices to synchronize to the P89LPC9321. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

2.5 On-chip RC oscillator option

The P89LPC9321 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. (Note: the initial value is better than 1 %; please refer to the P89LPC9321 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is doubled. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at

8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.

Table 5.

On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

 

 

Bit

7

6

5

4

3

2

1

0

Symbol

RCCLK

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

 

 

 

 

 

 

Reset

0

0

Bits 5:0 loaded with factory stored value during reset.

 

 

 

 

 

 

 

 

 

 

 

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Table 6.

On-chip RC oscillator trim register (TRIM - address 96h) bit description

 

 

 

Bit

Symbol

Description

0

TRIM.0

Trim value. Determines the frequency of the internal RC oscillator. During reset,

 

 

these bits are loaded with a stored factory calibration value. When writing to either

1

TRIM.1

bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value

 

 

2

TRIM.2

by reading this register, modifying bits 6 or 7 as required, and writing the result to

3

TRIM.3

this register.

 

 

 

4

TRIM.4

 

 

 

 

5

TRIM.5

 

 

 

 

6

ENCLK

when = 1, CCLK2 is output on the XTAL2 pin provided the crystal oscillator is not

 

 

being used.

 

 

 

7

RCCLK

when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for

 

 

fast switching between any clock source and the internal RC oscillator without

 

 

needing to go through a reset cycle.

 

 

 

2.6 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to

± 5 % at room temperature. This oscillator can be used to save power when a high clock frequency is not needed.

2.7 External clock input option

In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 Mhz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.

quartz crystal or ceramic resonator

XTAL1

(1)

XTAL2

002aad364

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1)A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).

Fig 7. Using the crystal oscillator.

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XTAL1

HIGH FREQUENCY

 

 

 

RTC

MEDIUM FREQUENCY

 

 

 

XTAL2

 

 

 

LOW FREQUENCY

 

 

 

 

 

 

 

 

 

 

 

 

OSCCLK

DIVM

CCLK

CPU

RC OSCILLATOR

RCCLK

 

 

 

 

 

 

WITH CLOCK DOUBLER

 

 

 

÷2

 

(7.3728 MHz/14.7456 MHz ± 1 %)

 

 

PCLK

 

 

WATCHDOG

 

 

 

 

WDT

 

 

 

 

 

 

 

OSCILLATOR

 

 

 

 

 

 

(400 kHz ± 5 %)

 

PCLK

 

 

32 × PLL

 

 

 

 

 

 

 

TIMER 0 AND

I2C-BUS

SPI

UART

CCU

 

 

TIMER 1

 

 

 

 

 

 

 

002aae108

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).

Fig 8. Block diagram of oscillator control.

2.8 Clock sources switch on the fly

P89LPC9321 can implement clock source switch in any sources of watchdog oscillator, 7/14MHz IRC oscillator, external crystal oscillator and external clock input during code is running. CLKOK bit in register CLKCON is read only and used to indicate the clock switch status. When CLKOK is ‘0’, clock switch is processing, not completed. When CLKOK is ‘1’, clock switch is completed. When start new clock source switch, CLKOK is cleared automatically. Notice that when CLKOK is ‘0’, Writing to CLKCON register is not allowed. During reset, CLKCON register value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.

Table 7.

Clock control register (CLKCON - address FFDEh) bit allocation

 

 

 

Bit

7

6

5

4

3

2

1

0

Symbol

CLKOK

-

-

XTALWD

CLKDBL

FOSC2

FOSC1

FOSC0

 

 

 

 

 

 

 

 

 

Reset

1

0

0

0

x

x

x

x

 

 

 

 

 

Table 8.

Clock control register (CLKCON - address FFDEh) bit description

 

 

 

 

 

 

 

 

 

 

 

Bit

Symbol

Description

 

 

 

 

 

2:0

FOSC2, FOSC1,

CPU oscillator type selection for clock switch. See Section 2 for additional

 

FOSC0

information. Combinations other than those shown in Table 9 are reserved for future

 

 

 

use should not be used.

 

 

 

 

 

 

 

3

CLKDBL

Clock doubler option for clock switch. When set, doubles the output frequency of the

 

 

 

internal RC oscillator.

 

 

 

 

 

 

 

4

XTALWD

Low speed external crystal oscillator as the clock source of watchdog timer. When

 

 

 

= 0, disable the external crystal oscillator as the clock source of watchdog timer.

 

 

 

 

 

 

 

 

 

6:5

-

 

reserved

 

 

 

 

 

 

 

 

7

CLKOK

Clock switch completed flag. When = 1, clock switch is completed. When =0, clock

 

 

 

switch is processing and writing to register CLKCON is not allowed.

 

 

 

 

 

 

 

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Table 9.

Oscillator type selection for clock switch

 

 

 

 

FOSC[2:0]

Oscillator configuration

 

111

External clock input on XTAL1.

 

 

 

 

100

Watchdog Oscillator, 400 kHz ± 5 %.

 

 

 

 

011

Internal RC oscillator, 7.373 MHz ± 1 %.

 

 

 

 

010

Low frequency crystal, 20 kHz to 100 kHz.

 

 

 

 

001

Medium frequency crystal or resonator, 100 kHz to 4 MHz.

 

 

 

 

000

High frequency crystal or resonator, 4 MHz to 18 MHz.

 

 

 

 

2.9 Oscillator Clock (OSCCLK) wake-up delay

The P89LPC9321 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 μs to 100 μs. If the clock source is the internal RC oscillator, the delay is

200 μs to 300 μs. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles.

2.10 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

CCLK frequency = fosc / (2N)

Where: fosc is the frequency of OSCCLK, N is the value of DIVM.

Since N ranges from 0 to 255, the CCLK frequency can be in the range of fosc to fosc/510. (for N = 0, CCLK = fosc).

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

2.11 Low power select

The P89LPC9321 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

3. Interrupts

The P89LPC9321 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC9321’s 15 interrupt sources.

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Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global enable bit, EA, which enables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used for pending requests of the same priority level. Table 11 summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake-up the CPU from a Power-down mode.

3.1 Interrupt priority structure

Table 10. Interrupt priority level

Priority bits

 

 

IPxH

IPx

Interrupt priority level

0

0

Level 0 (lowest priority)

 

 

 

0

1

Level 1

 

 

 

1

0

Level 2

 

 

 

1

1

Level 3

 

 

 

There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt has two bits in IPx and IPxH (x = 0, 1) and can therefore be assigned to one of four levels, as shown in Table 11.

The P89LPC9321 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is triggered by a low level detected at the INTn pin. If ITn = 1, external interrupt n is edge triggered. In this mode if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next cycle, interrupt request flag IEn in TCON is set, causing an interrupt request.

Since the external interrupt pins are sampled once each machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU when the service routine is called.

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If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.

If an external interrupt has been programmed as level-triggered and is enabled when the P89LPC9321 is put into Power-down mode or Idle mode, the interrupt occurrence will cause the processor to wake-up and resume operation. Refer to Section 5.3 “Power reduction modes” for details. Note: the external interrupt must be programmed as level-triggered to wake-up from Power-down mode.

3.2 External Interrupt pin glitch suppression

Most of the P89LPC9321 pins have glitch suppression circuits to reject short glitches (please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter specifications). However, pins SDA/INT0/P1.3 and SCL/T0/P1.2 do not have the glitch suppression circuits. Therefore, INT1 has glitch suppression while INT0 does not.

Table 11. Summary of interrupts

Description

Interrupt flag

Vector

Interrupt enable

Interrupt

Arbitration

Power-

 

bit(s)

address

bit(s)

priority

ranking

down

 

 

 

 

 

 

wake-up

External interrupt 0

IE0

0003h

EX0 (IEN0.0)

IP0H.0, IP0.0

1 (highest)

Yes

 

 

 

 

 

 

 

Timer 0 interrupt

TF0

000Bh

ET0 (IEN0.1)

IP0H.1, IP0.1

4

No

 

 

 

 

 

 

 

External interrupt 1

IE1

0013h

EX1 (IEN0.2)

IP0H.2, IP0.2

7

Yes

 

 

 

 

 

 

 

Timer 1 interrupt

TF1

001Bh

ET1 (IEN0.3)

IP0H.3, IP0.3

10

No

 

 

 

 

 

 

 

Serial port Tx and Rx

TI and RI

0023h

ES/ESR (IEN0.4)

IP0H.4, IP0.4

13

No

 

 

 

 

 

 

 

Serial port Rx

RI

 

 

 

 

 

 

 

 

 

 

 

 

Brownout detect

BOIF

002Bh

EBO (IEN0.5)

IP0H.5, IP0.5

2

Yes

 

 

 

 

 

 

 

Watchdog timer/Real-time

WDOVF/RTCF

0053h

EWDRT (IEN0.6)

IP0H.6, IP0.6

3

Yes

clock

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C interrupt

SI

0033h

EI2C (IEN1.0)

IP0H.0, IP0.0

5

No

KBI interrupt

KBIF

003Bh

EKBI (IEN1.1)

IP0H.0, IP0.0

8

Yes

 

 

 

 

 

 

 

Comparators 1 and 2

CMF1/CMF2

0043h

EC (IEN1.2)

IP0H.0, IP0.0

11

Yes

interrupts

 

 

 

 

 

 

 

 

 

 

 

 

 

SPI interrupt

SPIF

004Bh

ESPI (IEN1.3)

IP1H.3, IP1.3

14

No

 

 

 

 

 

 

 

Capture/Compare Unit

 

005Bh

ECCU(IEN1.4)

IP1H.4, IP1.4

6

No

 

 

 

 

 

 

 

Serial port Tx

TI

006Bh

EST (IEN1.6)

IP0H.0, IP0.0

12

No

 

 

 

 

 

 

 

Data EEPROM write

 

0073h

EAD (IEN1.7)

IP1H.7, IP1.7

15 (lowest)

No

complete

 

 

 

 

 

 

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IE0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EX0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EX1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BOIF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RTCF

 

 

 

 

 

EBO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

KBIF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ERTC

 

 

 

 

 

EKBI

 

 

 

 

 

 

 

 

 

 

 

(RTCCON.1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDOVF

 

 

 

 

 

EWDRT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CMF2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CMF1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA (IE0.7)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TF0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ET0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TF1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ET1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TI & RI/RI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ES/ESR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EI2C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPIF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ESPI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

any CCU interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ECCU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EEIF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EIEE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fig 9. Interrupt sources, interrupt enables, and power-down wake-up sources.

wake-up

(if in power-down)

interrupt to CPU

002aae160

4. I/O ports

The P89LPC9321 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1,and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen (see Table 12).

Table 12. Number of I/O pins available

Clock source

Reset option

Number of I/O

 

 

 

 

pins

On-chip oscillator or watchdog

No external reset (except during power up)

26

oscillator

 

 

 

 

 

 

 

 

External RST pin supported

25

 

External clock input

No external reset (except during power up)

25

 

 

 

 

 

 

External

 

pin supported

24

 

RST

 

 

 

Low/medium/high speed oscillator

No external reset (except during power up)

24

(external crystal or resonator)

 

 

 

 

 

 

 

 

External RST pin supported

23

 

 

 

 

 

 

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4.1 Port configurations

All but three I/O port pins on the P89LPC9321 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 13. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be configured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open drain.

Table 13. Port output configuration settings

PxM1.y

PxM2.y

Port output mode

0

0

Quasi-bidirectional

 

 

 

0

1

Push-pull

 

 

 

1

0

Input only (high-impedance)

 

 

 

1

1

Open drain

 

 

 

4.2 Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch for the pin contains a logic 1. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high.

The quasi-bidirectional port configuration is shown in Figure 10.

Although the P89LPC9321 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to VDD causing extra power consumption. Therefore, applying 5 V to pins configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit

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User manual

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NXP Semiconductors

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UM10310

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P89LPC9321 User manual

(Please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter

specifications).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 CPU

 

 

 

P

 

 

P

 

very

P

 

 

 

 

 

CLOCK DELAY

 

 

 

 

 

strong

 

 

weak

 

 

weak

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

port

pin

port latch data

input

data

002aaa914

glitch rejection

Fig 10. Quasi-bidirectional output.

4.3 Open drain output configuration

The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open drain port configuration is shown in Figure 11.

An open drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

Please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter specifications.

port latch data

Fig 11. Open drain output.

port pin

input data

glitch rejection

002aaa915

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4.4 Input-only configuration

The input port configuration is shown in Figure 12. It is a Schmitt-triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter specifications).

input

port

data

pin

 

glitch rejection

002aaa916

Fig 12. Input only.

4.5 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output.

The push-pull port configuration is shown in Figure 13.

A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC9321 data sheet, Dynamic characteristics for glitch filter specifications).

VDD

P

strong

port pin

port latch

N

data

 

input

data

glitch rejection

002aaa917

Fig 13. Push-pull output.

4.6 Port 0 and Analog Comparator functions

The P89LPC9321 incorporates two Analog Comparators. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both the digital outputs and digital inputs disabled.

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Digital outputs are disabled by putting the port pins into the input-only mode as described in the Port Configurations section (see Figure 12).

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. Bits 1 through 5 in this register correspond to pins P0.1 through P0.5 of Port 0, respectively. Setting the corresponding bit in PT0AD disables that pin’s digital input. Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port.

On any reset, PT0AD bits 1 through 5 default to logic 0s to enable the digital functions.

4.7 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.

After power-up, all I/O pins except P1.5, may be configured by software.

Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open drain.

Every output on the P89LPC9321 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the P89LPC9321 data sheet for detailed specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

Table 14. Port output configuration

Port pin

Configuration SFR bits

 

 

 

PxM1.y

PxM2.y

Alternate usage

Notes

P0.0

P0M1.0

P0M2.0

KBIO, CMP2

 

P0.1

P0M1.1

P0M2.1

KBI1, CIN2B

P0.2

P0M1.2

P0M2.2

KBI2, CIN2A

 

 

 

 

P0.3

P0M1.3

P0M2.3

KBI3, CIN1B

 

 

 

 

P0.4

P0M1.4

P0M2.4

KBI4, CIN1A

 

 

 

 

P0.5

P0M1.5

P0M2.5

KBI5, CMPREF

Refer to Section 4.6 “Port 0 and Analog Comparator functions” for usage as analog inputs.

 

P0.6

P0M1.6

P0M2.6

KBI6, CMP1

 

 

P0.7

P0M1.7

P0M2.7

KBI7, T1

 

 

 

 

 

 

 

 

P1.0

P1M1.0

P1M2.0

TXD

 

 

 

 

 

 

 

 

P1.1

P1M1.1

P1M2.1

RXD

 

 

 

 

 

 

 

 

P1.2

P1M1.2

P1M2.2

T0, SCL

Input-only or open-drain

 

 

 

 

 

 

 

 

 

 

P1.3

P1M1.3

P1M2.3

 

 

 

SDA

input-only or open-drain

INTO,

 

P1.4

P1M1.4

P1M2.4

 

 

 

 

INT1

 

 

P1.5

P1M1.5

P1M2.5

 

 

 

RST

 

 

P1.6

P1M1.6

P1M2.6

OCB

 

 

 

 

 

 

 

 

P1.7

P1M1.7

P1M2.7

OCC

 

 

 

 

 

 

 

 

P2.0

P2M1.0

P2M2.0

ICB

 

 

 

 

 

 

 

 

P2.1

P2M1.1

P2M2.1

OCD

 

 

 

 

 

 

 

 

P2.2

P2M1.2

P2M2.2

MOSI

 

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NXP Semiconductors

 

 

 

 

 

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Table 14. Port output configuration …continued

 

 

 

 

 

 

 

 

 

Port pin

Configuration SFR bits

 

 

 

 

 

PxM1.y

PxM2.y

 

Alternate usage

Notes

 

P2.3

P2M1.3

P2M2.3

MISO

 

 

 

 

 

 

 

 

 

P2.4

P2M1.4

P2M2.4

 

 

 

SS

 

 

P2.5

P2M1.5

P2M2.5

SPICLK

 

 

 

 

 

 

 

 

P2.6

P2M1.6

P2M2.6

OCA

 

 

 

 

 

 

 

 

P2.7

P2M1.7

P2M2.7

ICA

 

 

 

 

 

 

 

 

P3.0

P3M1.0

P3M2.0

CLKOUT, XTAL2

 

 

 

 

 

 

 

 

P3.1

P3M1.1

P3M2.1

XTAL1

 

 

 

 

 

 

 

 

 

5. Power monitoring functions

The P89LPC9321 incorporates power monitoring functions designed to prevent incorrect operation during initial power-on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect.

5.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced BOD has 3 independent functions: BOD reset, BOD interrupt and BOD EEPROM/FLASH.

BOD reset will cause a processor reset and it is always on, except in total power-down mode. It could not be disabled in software. BOD interrupt will generate an interrupt and could be enabled or disabled in software.

BOD reset and BOD interrupt, each has 4 trip voltage levels. BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are used as trip point configuration bits of BOD reset. BOICFG1 bit and BOICFG0 bit in register BODCFG are used as trip point configuration bits of BOD interrupt. BOD reset voltage should be lower than BOD interrupt trip point. Table 15 gives BOD trip points configuration.

In total power-down mode (PMOD1/PMOD0 = '11'), the circuitry for the Brownout Detection is disabled for lowest power consumption. When PMOD1/PMOD0 not equal to '11', BOD reset is always on and BOD interrupt is enabled by setting BOI (PCON.4) bit. Please refer Table 16 for BOD reset and BOD interrupt configuration. BOF bit (RSTSRC.5), BOD reset flag is default as '0' and is set when BOD reset is tripped. BOIF bit (RSTSRC.6), BOD interrupt flag is default as '0' and is set when BOD interrupt is tripped.

BOD EEPROM/FLASH is used for flash/Data EEPROM program/erase protection. BOD EEPROM/FLASH is always on, except in power-down or total power down mode (PCON.1=1). It can not be disabled in software. BOD EEPROM/FLASH has only 1 trip voltage level of 2.4 V. When voltage supply is lower than 2.4 V, the BOD EEPROM/FLASH is tripped and flash/Data EEPROM program/erase is blocked.

If brownout detection is enabled the brownout condition occurs when VDD falls below the brownout trip voltage and is negated when VDD rises above the brownout trip voltage.

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For correct activation of Brownout Detect, certain VDD rise and fall times must be observed. Please see the data sheet for specifications.

Table 15. BOD Trip points configuration

BOE1

BOE0

BOICFG1

BOICFG0

BOD Reset

BOD

(UCFG1.5)

(UCFG1.3)

(BOICFG.1)

(BOICFG.0)

 

Interrupt

0

0

0

0

Reserved

 

 

 

 

 

 

 

0

0

0

1

 

 

 

 

 

 

 

 

0

0

1

0

 

 

 

 

 

 

 

 

0

0

1

1

 

 

 

 

 

 

 

 

0

1

0

0

 

 

 

 

 

 

 

 

0

1

0

1

2.2V

2.4V

 

 

 

 

 

 

0

1

1

0

2.2V

2.6V

 

 

 

 

 

 

0

1

1

1

2.2V

3.2V

 

 

 

 

 

 

1

0

0

0

Reserved

 

 

 

 

 

 

 

1

0

0

1

 

 

 

 

 

 

 

 

1

0

1

0

2.4V

2.6V

 

 

 

 

 

 

1

0

1

1

2.4V

3.2V

 

 

 

 

 

 

1

1

0

0

Reserved

 

 

 

 

 

 

 

1

1

0

1

 

 

 

 

 

 

 

 

1

1

1

0

 

 

 

 

 

 

 

 

1

1

1

1

3.0V

3.2V

 

 

 

 

 

 

Table 16. BOD Reset and BOD Interrupt configuration

PMOD1/PMOD0(PCON[1:0])

BOI

EBO

EA

BOD

BOD

 

(PCON.4)

(IEN0.5)

(IEN0.7)

Reset

Interrupt

11 (total power-down)

X

X

X

N

N

 

 

 

 

 

 

≠ 11 (any mode other than total

0

X

X

Y

N

power down)

 

 

 

 

 

1

0

X

Y

N

 

 

 

 

 

 

 

 

 

X

0

Y

N

 

 

 

 

 

 

 

 

1

1

Y

Y

 

 

 

 

 

 

5.2 Power-on detection

The Power-On Detect has a function similar to the Brownout Detect, but is designed to work as power initially comes up, before the power supply voltage reaches a level where the Brownout Detect can function. The POF flag (RSTSRC.4) is set to indicate an initial power-on condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. BOF (RSTSRC.5) will be set when POF is set.

5.3 Power reduction modes

The P89LPC9321 supports three different power reduction modes as determined by SFR bits PCON[1:0] (see Table 17).

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Table 17. Power reduction modes

 

 

 

 

 

PMOD1

PMOD0

Description

 

(PCON.1)

(PCON.0)

 

 

0

0

Normal mode (default) - no power reduction.

 

 

 

 

0

1

Idle mode. The Idle mode leaves peripherals running in order to allow them to activate the

 

 

processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle

 

 

mode.

 

 

 

 

 

1

0

Power-down mode:

 

 

 

The Power-down mode stops the oscillator in order to minimize power consumption.

The P89LPC9321 exits Power-down mode via any reset, or certain interrupts - external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, and comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit (IEN0.7) is set. External interrupts should be programmed to level-triggered mode to be used to exit Power-down mode.

In Power-down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled.

In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VRAM, therefore it is recommended to wake-up the processor via Reset in this situation. VDD must be raised to within the operating range before the Power-down mode is exited.

When the processor wakes up from Power-down mode, it will start the oscillator immediately and begin execution when the oscillator is stable. Oscillator stability is determined by counting 1024 CPU clocks after start-up when one of the crystal oscillator configurations is used, or 200ms to 300ms after start-up for the internal RC, or 32 OSCCLK cycles after start-up for external clock input.

Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include:

Brownout Detect

Watchdog Timer if WDCLK (WDCON.0) is logic 1.

Comparators (Note: Comparators can be powered down separately with PCONA.5 set to logic 1 and comparators disabled);

Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless RTCPD, i.e., PCONA.7 is logic 1).

1

1

Total Power-down mode: This is the same as Power-down mode except that the Brownout

 

 

Detection circuitry and the voltage comparators are also disabled to conserve additional power.

Note that a brownout reset or interrupt will not occur. Voltage comparator interrupts and Brownout interrupt cannot be used as a wake-up source. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled.

The following are the wake-up options supported:

Watchdog Timer if WDCLK (WDCON.0) is logic 1. Could generate Interrupt or Reset, either one can wake up the device

External interrupts INTO/INT1 (when programmed to level-triggered mode).

Keyboard Interrupt

Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless RTCPD, i.e., PCONA.7 is logic 1).

Note: Using the internal RC-oscillator to clock the RTC during power-down may result in relatively high power consumption. Lower power consumption can be achieved by using an external low frequency clock when the Real-time Clock or watchdog timer is running during power-down.

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Table 18. Power Control register (PCON - address 87h) bit allocation

 

 

 

 

 

 

 

 

 

 

 

 

Bit

7

6

5

4

3

2

1

0

Symbol

SMOD1

SMOD0

-

BOI

GF1

GF0

PMOD1

PMOD0

 

 

 

 

 

 

 

 

 

Reset

0

0

-

0

0

0

0

0

 

 

 

 

Table 19. Power Control register (PCON - address 87h) bit description

 

 

 

 

 

 

 

 

 

 

 

Bit

Symbol

Description

 

 

 

 

 

0

PMOD0

Power Reduction Mode (see Section 5.3)

 

 

 

 

 

 

 

 

 

 

 

1

PMOD1

 

 

 

 

 

 

 

 

 

 

2

GF0

 

General Purpose Flag 0. May be read or written by user software, but has no effect

 

 

 

on operation

 

 

 

 

 

 

 

 

 

3

GF1

 

General Purpose Flag 1. May be read or written by user software, but has no effect

 

 

 

on operation

 

 

 

 

 

4

BOI

 

Brownout Detect Interrupt Enable. When logic 1, Brownout Detection will generate a

 

 

 

interrupt.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

-

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

6

SMOD0

Framing Error Location:

 

 

 

 

When logic 0, bit 7 of SCON is accessed as SM0 for the UART.

When logic 1, bit 7 of SCON is accessed as the framing error status (FE) for the UART

7

SMOD1

Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud

 

 

 

rate source. When logic 1, the Timer 1 overflow rate is supplied to the UART. When

 

 

 

logic 0, the Timer 1 overflow rate is divided by two before being supplied to the

 

 

 

UART. (See Section 9)

 

 

 

 

 

 

 

 

Table 20. Power Control register A (PCONA - address B5h) bit allocation

 

 

 

 

 

 

 

 

 

 

 

 

Bit

7

6

5

4

3

2

1

0

Symbol

RTCPD

DEEPD

VCPD

-

I2PD

SPPD

SPD

CCUPD

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

 

 

 

 

Table 21. Power Control register A (PCONA - address B5h) bit description

 

 

 

 

 

 

 

 

 

 

 

Bit

Symbol

Description

 

 

 

 

 

0

CCUPD

Compare/Capture Unit (CCU) power-down: When logic 1, the internal clock to the

 

 

 

CCU is disabled. Note that in either Power-down mode or Total Power-down mode,

 

 

 

the CCU clock will be disabled regardless of this bit. (Note: This bit is overridden by

 

 

 

the CCUDIS bit in FCFG1. If CCUDIS = 1, CCU is powered down.)

 

 

 

 

 

1

SPD

 

Serial Port (UART) power-down: When logic 1, the internal clock to the UART is

 

 

 

disabled. Note that in either Power-down mode or Total Power-down mode, the

 

 

 

UART clock will be disabled regardless of this bit.

 

 

2

SPPD

 

SPI power-down: When logic 1, the internal clock to the SPI is disabled. Note that in

 

 

 

either Power-down mode or Total Power-down mode, the SPI clock will be disabled

 

 

 

regardless of this bit.

 

 

 

 

 

 

 

 

3

I2PD

 

I2C power-down: When logic 1, the internal clock to the I2C-bus is disabled. Note

 

 

 

that in either Power-down mode or Total Power-down mode, the I2C clock will be

 

 

 

disabled regardless of this bit.

 

 

 

 

 

 

 

 

 

 

 

 

4

-

 

reserved

 

 

 

 

 

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Table 21. Power Control register A (PCONA - address B5h) bit description …continued

 

 

 

Bit

Symbol

Description

5

VCPD

Analog Voltage Comparators power-down: When logic 1, the voltage comparators

 

 

are powered down. User must disable the voltage comparators prior to setting this

 

 

bit.

 

 

 

6

DEEPD

Data EEPROM power-down: When logic 1, the Data EEPROM is powered down.

 

 

Note that in either Power-down mode or Total Power-down mode, the Data

 

 

EEPROM will be powered down regardless of this bit.

 

 

 

7

RTCPD

Real-time Clock power-down: When logic 1, the internal clock to the Real-time

 

 

Clock is disabled.

 

 

 

6. Reset

The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-on sequence, The RPE selection is overridden and this pin will always functions as a reset input. An external circuit connected to this pin should not hold this pin low during a Power-on sequence as this will keep the device in reset. After power-on this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-on reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit.

Note: During a power cycle, VDD must fall below VPOR (see P89LPC9321 data sheet, Static characteristics) before power is reapplied, in order to ensure a power-on reset.

Reset can be triggered from the following sources:

External reset pin (during power-on or if user configured via UCFG1);

Power-on detect;

Brownout detect;

Watchdog timer;

Software reset;

UART break character detect reset.

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit may be set:

During a power-on reset, both POF and BOF are set but the other flag bits are cleared.

A watchdog reset is similar to a power-on reset, both POF and BOF are set but the other flag bits are cleared.

For any other reset, previously set flag bits that have not been cleared will remain set.

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RPE (UCFG1.6)

RST pin

WDTE (UCFG1.7) watchdog timer reset

software reset SRST (AUXR1.3)

chip reset

power-on detect

UART break detect

EBRR (AUXR1.6)

brownout detect reset

002aae129

Fig 14. Block diagram of reset

Table 22. Reset Sources register (RSTSRC - address DFh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

-

BOIF

BOF

POF

R_BK

R_WD

R_SF

R_EX

 

 

 

 

 

 

 

 

 

Reset[1]

x

0

1

1

0

0

0

0

[1]The value shown is for a power-on reset. Other reset sources will set their corresponding bits.

Table 23. Reset Sources register (RSTSRC - address DFh) bit description

Bit Symbol Description

0

R_EX

external reset Flag. When this bit is logic 1, it indicates external pin reset. Cleared by software by writing a

 

 

logic 0 to the bit or a Power-on reset. If RST is still asserted after the Power-on reset is over, R_EX will be set.

 

 

 

1

R_SF

software reset Flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset

 

 

 

2

R_WD

Watchdog Timer reset flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset.(NOTE:

 

 

UCFG1.7 must be = 1)

 

 

 

3

R_BK

break detect reset. If a break detect occurs and EBRR (AUXR1.6) is set to logic 1, a system reset will occur.

 

 

This bit is set to indicate that the system reset is caused by a break detect. Cleared by software by writing a

 

 

logic 0 to the bit or on a Power-on reset.

 

 

 

4

POF

Power-on Detect Flag. When Power-on Detect is activated, the POF flag is set to indicate an initial power-up

 

 

condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. (Note: On a

 

 

Power-on reset, both BOF and this bit will be set while the other flag bits are cleared.)

5

BOF

BOD Reset Flag. When BOD Reset is activated, this bit is set. It will remain set until cleared by software by

 

 

writing a logic 0 to the bit. (Note: On a Power-on reset, both POF and this bit will be set while the other flag

 

 

bits are cleared.)

 

 

 

6

BOIF

BOD Interrupt Flag. When BOD Interrupt is activated, this bit is set. It will remain set until cleared by software

 

 

by writing a logic 0 to the bit.

7

-

reserved

 

 

 

6.1

Reset vector

 

 

Following reset, the P89LPC9321 will fetch instructions from either address 0000h or the

 

Boot address. The Boot address is formed by using the Boot Vector as the high byte of the

 

address and the low byte of the address = 00h. The Boot address will be used if a UART

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break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device has been forced into ISP mode. Otherwise, instructions will be fetched from address 0000H.

7. Timers 0 and 1

The P89LPC9321 has two general-purpose counter/timers which are upward compatible with the 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters (see Table 25). An option to automatically toggle the Tx pin upon timer overflow has been added.

In the ‘Timer’ function, the timer is incremented every PCLK.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition on its corresponding external input pin (T0 or T1). The external input is sampled once during every machine cycle. When the pin is high during one cycle and low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes two machine cycles (four CPU clocks) to recognize a 1-to-0 transition, the maximum count rate is 14 of the CPU clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

The ‘Timer’ or ‘Counter’ function is selected by control bits TnC/T (x = 0 and 1 for Timers 0 and 1 respectively) in the Special Function Register TMOD. Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6), which are selected by bit-pairs (TnM1, TnM0) in TMOD and TnM2 in TAMOD. Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different. The operating modes are described later in this section.

Table 24. Timer/Counter Mode register (TMOD - address 89h) bit allocation

Bit

7

6

 

5

4

3

2

 

1

0

Symbol

T1GATE

T1C/T

 

T1M1

T1M0

T0GATE

T0C/T

 

T0M1

T0M0

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

 

0

0

0

0

 

0

0

 

 

 

 

 

 

 

 

 

 

 

Table 25. Timer/Counter Mode register (TMOD - address 89h) bit description

Bit

Symbol

Description

 

0

T0M0

Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the

 

 

 

 

Timer 0 mode (see Table 27).

 

1

T0M1

 

 

 

 

 

 

 

 

 

 

2

T0C/T

 

 

Timer or Counter selector for Timer 0. Cleared for Timer operation (input from CCLK). Set for Counter

 

 

 

 

 

operation (input from T0 input pin).

 

 

 

 

 

 

3

T0GATE

Gating control for Timer 0. When set, Timer/Counter is enabled only while the

 

pin is high and the TR0

INT0

 

 

 

 

control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set.

 

 

 

 

4

T1M0

Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the

 

 

 

 

Timer 1 mode (see Table 27).

 

5

T1M1

 

 

 

 

 

 

 

 

 

 

6

T1C/T

 

 

Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from CCLK). Set for Counter

 

 

 

 

 

operation (input from T1 input pin).

 

 

 

 

 

 

7

T1GATE

Gating control for Timer 1. When set, Timer/Counter is enabled only while the

 

pin is high and the TR1

INT1

 

 

 

 

control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set.

 

 

 

 

 

 

 

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Table 26. Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation

 

 

 

 

 

 

 

 

 

 

 

Bit

7

6

5

4

3

2

1

0

Symbol

--

-

-

T1M2

-

-

-

T0M2

 

 

 

 

 

 

 

 

 

Reset

x

x

x

0

x

x

x

0

 

 

 

 

 

 

 

 

 

Table 27. Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit description

Bit

Symbol

Description

0

T0M2

Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the

 

 

Timer 0 mode (see Table 27).

 

 

 

1:3

-

reserved

 

 

 

4

T1M2

Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the

 

 

Timer 1 mode (see Table 27).

 

 

The following timer modes are selected by timer mode bits TnM[2:0]:

 

 

000

8048 Timer ‘TLn’ serves as 5-bit prescaler. (Mode 0)

 

 

001

16-bit Timer/Counter ‘THn’ and ‘TLn’ are cascaded; there is no prescaler.(Mode 1)

 

 

010

8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows.

 

 

(Mode 2)

 

 

011 — Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the

 

 

standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text).

 

 

Timer 1 in this mode is stopped. (Mode 3)

 

 

100

Reserved. User must not configure to this mode.

 

 

101

Reserved. User must not configure to this mode.

 

 

110 — PWM mode (see Section 7.5).

 

 

111 — Reserved. User must not configure to this mode.

 

 

 

5:7

-

reserved

 

 

 

 

7.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 15 shows Mode 0 operation.

In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the Timer when TRn = 1 and either TnGATE = 0 or INTn = 1. (Setting TnGATE = 1 allows the Timer to be controlled by external input INTn, to facilitate pulse width measurements).

TRn is a control bit in the Special Function Register TCON (Table 29). The TnGATE bit is in the TMOD register.

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers.

Mode 0 operation is the same for Timer 0 and Timer 1. See Figure 15. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

7.2

Mode 1

 

 

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn)

 

are used. See Figure 16.

 

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7.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 17. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.

7.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 on Timer 0 is shown in Figure 18. TL0 uses the Timer 0 control bits: T0C/T, T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the ‘Timer 1’ interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P89LPC9321 device can look like it has three Timer/Counters.

Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.

7.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks (see Figure 19). Its structure is similar to mode 2, except that:

TFn (n = 0 and 1 for Timers 0 and 1 respectively) is set and cleared in hardware;

The low period of the TFn is in THn, and should be between 1 and 254, and;

The high period of the TFn is always 256−THn.

Loading THn with 00h will force the Tx pin high, loading THn with FFh will force the Tx pin low.

Note that interrupt can still be enabled on the low to high transition of TFn, and that TFn can still be cleared in software like in any other modes.

Table 28. Timer/Counter Control register (TCON) - address 88h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

Table 29. Timer/Counter Control register (TCON - address 88h) bit description

Bit

Symbol

Description

 

0

IT0

Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external

 

 

interrupts.

 

 

 

 

 

 

1

IE0

Interrupt 0

Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by hardware

 

 

when the interrupt is processed, or by software.

 

 

 

 

 

2

IT1

Interrupt 1

Type control bit. Set/cleared by software to specify falling edge/low level triggered external

 

 

interrupts.

 

 

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Table 29. Timer/Counter Control register (TCON - address 88h) bit description …continued

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

Symbol

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

IE1

Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware

 

 

when the interrupt is processed, or by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

TR0

Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

TF0

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the

 

 

processor vectors to the interrupt routine, or by software. (except in mode 6, where it is cleared in hardware)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

TR1

Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

TF1

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the interrupt

 

 

is processed, or by software (except in mode 6, see above, when it is cleared in hardware).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

= 0

 

 

 

 

 

 

overflow

 

 

 

 

 

 

 

 

 

 

 

PCLK

 

 

 

 

 

 

 

 

C/T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TLn

THn

 

 

 

TFn

 

 

 

interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Tn pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(5-bits)

(8-bits)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C/T = 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRn

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

toggle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Tn pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTn pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENTn

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

002aaa919

 

 

 

Fig 15. Timer/counter 0 or 1 in Mode 0 (13-bit counter).

C/T = 0

 

 

overflow

 

 

PCLK

 

TLn

THn

 

interrupt

 

 

TFn

Tn pin

control

(8-bits) (8-bits)

 

 

C/T = 1

 

 

 

 

TRn

 

 

toggle

 

 

 

 

 

 

Tn pin

 

 

 

 

 

Gate

 

 

 

 

 

INTn pin

 

 

 

ENTn

 

 

 

 

 

 

 

 

 

 

002aaa920

 

Fig 16. Timer/counter 0 or 1 in mode 1 (16-bit counter).

C/T = 0

 

 

overflow

 

PCLK

 

TLn

interrupt

 

 

TFn

Tn pin

control

(8-bits)

 

 

C/T = 1

 

 

 

 

 

reload

toggle

 

TRn

 

 

 

 

 

 

Tn pin

 

 

 

 

Gate

 

THn

 

 

 

 

 

 

INTn pin

 

(8-bits)

ENTn

 

 

 

 

 

 

 

 

002aaa921

 

Fig 17. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload).

UM10310

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© NXP B.V. 2010. All rights reserved.

User manual

Rev. 2 — 1 November 2010

42 of 139

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