NXP Semiconductors LPC24XX UM10237 User Manual

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UM10237

LPC24XX User manual

Rev. 04 — 26 August 2009 User manual

Document information

Info

Content

Keywords

LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478,

 

ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.0,

 

Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, PWM, IRC,

 

Microcontroller

Abstract

LPC24XX User manual release

 

 

NXP Semiconductors

UM10237

 

 

LPC24XX User manual

Revision history

 

 

 

 

Rev

Date

Description

 

 

 

04

20090826

LPC24XX user manual release.

 

 

 

 

 

Modifications:

Memory size for LPC2458 external SRAM memory corrected in Table 2–14.

Deep power-down mode functionality added (see Section 4–3.4 “Power control” and Section 26–6.6 “Alarm output”).

Register containing device revision added (implemented starting with revision C, see Section 30–9.11).

 

 

XTAL1 input selection and PCB layout guidelines added (see Section 4–2.2).

 

 

Editorial updates throughout the user manual.

 

 

ISP1302 replaces ISP1301 in Section 15–6.

 

 

UART fractional baud rate generator disabled in auto baud mode (see Section 16–4.10

 

 

 

and Section 17–4.14).

 

 

 

03

20090115

LPC24XX user manual release.

 

 

 

 

 

Modifications:

 

 

Description of AHB1 and AHB2 configuration registers updated.

 

 

 

02

20081219

LPC24XX user manual release.

 

 

 

 

 

Modifications:

 

 

Added parts LPC2420.

 

 

Editorial updates.

 

 

AHB1 and AHB2 configuration registers added.

01

20080718

Initial LPC24XX user manual release. Replaces all draft versions UM10237_1.00 to

 

 

UM10237_1.05.

 

 

 

 

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

2 of 792

UM10237

Chapter 1: LPC24XX Introductory information

Rev. 04 — 26 August 2009 User manual

1. Introduction

NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speed Flash memory. This Flash memory includes a special 128-bit wide memory interface and accelerator architecture that enables the CPU to execute sequential instructions from Flash memory at the maximum 72 MHz system clock rate. This feature is available only on the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both 32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets means Engineers can choose to optimize their application for either performance or code size at the sub-routine level. When the core executes instructions in Thumb state it can reduce code size by more than 30 % with only a small loss in performance while executing instructions in ARM state maximizes core performance.

The LPC2400 microcontrollers are ideal for multi-purpose communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full speed device/host/OTG controller with 4 kB of endpoint RAM, four UARTs, two Controller Area Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I2C interfaces, and an I2S interface. Supporting this collection of serial communications interfaces are the following feature components; an on-chip 4 MHz internal precision oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller (EMC). These features make this device optimally suited for communication gateways and protocol converters. Complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO lines. The LPC2400 connect 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered, interrupts. All of these features make the LPC2400 particularly suitable for industrial control and medical systems.

2. How to read this manual

Important: The term “LPC24XX“ in this user manual will be used as a generic name for all LPC2400 parts. It covers the following parts: LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, and LPC2478.

For information about individual parts refer to Table 1–1 and Table 1–2.

Table 1. LPC24XX overview

 

 

LPC2458

LPC2420/60

LPC2468

LPC2470

LPC2478

 

Features

Section 1–3

Section 1–3

Section 1–3

Section 1–3

Section 1–3

 

 

 

 

 

 

 

 

Ordering options

Section 1–5.1

Section 1–5.2

Section 1–5.3

Section 1–5.4

Section 1–5.5

 

 

 

 

 

 

 

 

Block diagrams

Section 1–9

Section 1–10

Section 1–11

Section 1–12

Section 1–13

 

 

 

 

 

 

UM10237_4

 

 

 

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

3 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

Most features and peripherals are identical for all LPC2400 parts. All differences are listed in Table 1–2.

Table 2. Differences between LPC2400 parts

 

Pins/

Flash

EMC

LCD

 

High-speed

 

 

 

 

GPIO pins

 

 

 

LPC2458

180/136

512 kB

16-bit

no

 

 

 

 

 

LPC2460/20

208/160

flashless

32-bit

no

 

 

 

 

 

LPC2468

208/160

512 kB

32-bit

no

 

 

 

 

 

LPC2470

208/160

flashless

32-bit

yes

 

 

 

 

 

LPC2478

208/160

512 kB

32-bit

yes

 

 

 

 

 

3.LPC2400 features

ARM7TDMI-S processor, running at up to 72 MHz.

98 kB on-chip SRAM includes:

64 kB of SRAM on the ARM local bus for high performance CPU access.

16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

16 kB SRAM for general purpose DMA use also accessible by the USB.

2 kB SRAM data storage powered from the RTC power domain.

LPC2458/68/78 only: 512 kB on-chip Flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.

Dual Advanced High-performance Bus (AHB) system allows memory access by multiple resources and simultaneous program execution with no contention.

EMC provides support for asynchronous static memory devices such as RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM.

Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I2S, and SD/MM interface as well as for memory-to-memory transfers.

LPC2470/78 only: LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays.

Dedicated DMA controller.

Selectable display resolution (up to 1024 × 768 pixels).

Supports up to 24-bit true-color mode.

Serial Interfaces:

Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB bus.

USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller.

Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.

CAN controller with two channels.

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

4 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

SPI controller.

Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.

Three I2C-bus interfaces (one with open-drain and two with standard port pins).

I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.

Other peripherals:

SD/MMC memory card interface.

160 general purpose I/O pins with configurable pull-up/down resistors.

10-bit ADC with input multiplexing among 8 pins.

10-bit DAC.

Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input.

Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs.

Real-Time Clock (RTC) with separate power domain, clock source can be the RTC oscillator or the APB clock.

2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off.

WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.

Standard ARM test/debug interface for compatibility with existing tools.

Emulation trace module supports real-time trace.

Single 3.3 V power supply (3.0 V to 3.6 V).

Four reduced power modes: idle, sleep, power-down, and deep power-down.

Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.

Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt).

Two independent power domains allow fine tuning of power consumption based on needed features.

Each peripheral has its own clock divider for further power saving. These dividers help reducing active power by 20 - 30 %.

Brownout detect with separate thresholds for interrupt and forced reset.

On-chip power-on reset.

On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.

4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run.

On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

5 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

Boundary scan for simplified board testing.

Versatile pin function selections allow more possibilities for using on-chip peripheral functions.

4.Applications

Industrial control

Medical systems

Protocol converter

Communications

5.Ordering options

5.1LPC2458 ordering options

Table 3. LPC2458 ordering information

 

Type number

Package

 

 

 

 

 

 

 

Name

Description

Version

LPC2458FET180

TFBGA180

plastic thin fine-pitch ball grid array package; 180 balls; body 12 x 12 x 0.8 mm

SOT570-2

 

 

 

 

Table 4.

LPC2458 ordering options

 

 

 

 

 

 

 

 

 

 

 

Type number

 

 

Flash

 

 

 

SRAM (kB)

 

External

Ethernet

USB

 

SD/

GP

 

 

Temp

 

 

 

 

(kB)

busLocal

 

bufferEthernet

GP/USB

RTC

Total

bus

 

OTG/

channelsCAN

MMC

DMA

channelsADC

channelsDAC

range

 

 

 

 

 

 

 

 

OHC/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+ 4 kB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2458FET180

512

64

16

16

2

98 16-bit

MII/

yes

2

yes

yes 8

1

−40 °C to

 

 

 

 

 

 

 

 

 

 

 

 

 

RMII

 

 

 

 

 

 

+85 °C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.2 LPC2460 ordering options

 

 

 

 

 

 

 

 

Table 5.

LPC2420/60 ordering information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

 

Package

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

Description

 

 

 

 

 

 

 

 

 

Version

LPC2420FBD208

 

LQFP208

 

 

plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm

 

SOT459-1

 

 

 

 

 

 

 

 

LPC2460FBD208

 

LQFP208

 

 

plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm

 

SOT459-1

 

 

 

 

 

LPC2460FET208

 

TFBGA208

plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 × 0.7 mm

SOT950-1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

6 of 792

NXP Semiconductors

 

 

 

 

 

 

 

 

 

 

UM10237

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chapter 1: LPC24XX Introductory information

Table 6.

LPC2420/60 ordering options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

 

 

Flash

 

 

 

SRAM (kB)

 

External

Ethernet

USB

 

SD/

GP

 

 

Temp

 

 

 

 

(kB)

busLocal

 

bufferEthernet

GP/USB

RTC

Total

bus

 

OTG/

channelsCAN

MMC

DMA

channelsADC

channelsDAC

range

 

 

 

 

 

 

 

 

 

OHCI/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+ 4 kB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2420FBD208

 

 

N/A

64

-

16

2

82

Full 32-bit

-

yes

-

yes

yes

8

1

−40 °C to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+85 °C

LPC2460FBD208

 

 

N/A

64

16

16

2

98

Full 32-bit

MII/RMII

yes

2

yes

yes

8

1

−40 °C to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+85 °C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2460FET208

 

 

N/A

64

16

16

2

98

Full 32-bit

MII/RMII

yes

2

yes

yes

8

1

−40 °C to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+85 °C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.3

LPC2468 ordering options

 

 

 

 

 

 

 

 

Table 7.

LPC2468 ordering information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

 

Package

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

Description

 

 

 

 

 

 

 

 

 

Version

LPC2468FBD208

 

LQFP208

 

 

plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm

 

 

SOT459-1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2468FET208

 

TFBGA208

plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm

SOT950-1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8.

LPC2468 ordering options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

 

 

Flash

 

 

 

SRAM (kB)

 

External

Ethernet

USB

 

SD/

GP

 

 

Temp

 

 

 

 

(kB)

busLocal

 

bufferEthernet

GP/USB

RTC

Total

bus

 

OTG/

channelsCAN

MMC

DMA

channelsADC

channelsDAC

range

 

 

 

 

 

 

 

 

 

OHC/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+ 4 kB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2468FBD208

512

64

16

16

2

98

Full 32-bit

MII/

yes

2

yes

yes

8

1

−40 °C to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RMII

 

 

 

 

 

 

+85 °C

LPC2468FET208

512

64

16

16

2

98

Full 32-bit

MII/

yes

2

yes

yes

8

1

−40 °C to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RMII

 

 

 

 

 

 

+85 °C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.4

LPC2470 ordering options

 

 

 

 

 

 

 

 

Table 9.

LPC2470 ordering information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

 

Package

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

Description

 

 

 

 

 

 

 

 

 

Version

LPC2470FBD208

 

LQFP208

 

 

plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm

 

 

SOT459-1

 

 

 

 

 

 

 

LPC2470FET208

 

TFBGA208

plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 ×

 

 

SOT950-1

 

 

 

 

 

 

 

 

0.7 mm

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

7 of 792

NXP Semiconductors

 

 

 

 

 

 

 

 

 

UM10237

 

 

 

 

 

 

 

 

 

 

Chapter 1: LPC24XX Introductory information

Table 10. LPC2470 ordering options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

 

Flash

 

SRAM (kB)

 

External

Ethernet

USB

 

SD/

GP

 

 

 

 

Temp

 

 

(kB)

 

busLocal

bufferEthernet

GP/USB

RTC

Total

bus

 

OTG/

channelsCAN

MMC

DMA

channelsADC

channelsDAC

 

range

 

 

 

 

 

 

OHC/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+ 4 kB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2470FBD208

 

N/A

64

16

16

2

98

Full

MII/RMII

yes

2

yes

yes

8

1

 

 

−40 °C

 

 

 

 

 

 

 

 

 

32-bit

 

 

 

 

 

 

 

 

 

to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+85 °C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2470FET208

 

N/A

64

16

16

2

98

Full

MII/RMII

yes

2

yes

yes

8

1

 

 

−40 °C

 

 

 

 

 

 

 

 

 

32-bit

 

 

 

 

 

 

 

 

 

to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+85 °C

 

5.5

LPC2478 ordering options

 

 

 

 

 

 

 

 

 

 

Table 11. LPC2478 ordering information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

 

Package

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

Description

 

 

 

 

 

 

 

 

 

 

 

Version

LPC2478FBD208

 

LQFP208

plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm

 

 

 

SOT459-1

 

 

 

 

 

 

 

 

LPC2478FET208

 

TFBGA208

plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 ×

 

 

 

SOT950-1

 

 

 

 

 

0.7 mm

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 12. LPC2478 ordering options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type number

 

Flash

 

SRAM (kB)

 

External

Ethernet

USB

 

SD/

GP

 

 

 

 

Temp

 

 

(kB)

 

busLocal

bufferEthernet

GP/USB

RTC

Total

bus

 

OTG/

channelsCAN

MMC

DMA

channelsADC

channelsDAC

 

range

 

 

 

 

 

 

OHC/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+ 4 kB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2478FBD208

512

64

16

16

2

98

Full

MII/RMII

yes

2

yes

yes

8

1

 

 

−40 °C

 

 

 

 

 

 

 

 

 

32-bit

 

 

 

 

 

 

 

 

 

to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+85 °C

LPC2478FET208

512

64

16

16

2

98

Full

MII/RMII

yes

2

yes

yes

8

1

 

 

−40 °C

 

 

 

 

 

 

 

 

 

32-bit

 

 

 

 

 

 

 

 

 

to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+85 °C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6. Architectural overview

The LPC2400 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high speed access to the majority of on-chip memory, the AMBA AHB interfacing to high speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order.

The LPC2400 implements two AHB buses in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC.

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

8 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. Lower speed peripheral functions are connected to the APB bus. The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

the standard 32-bit ARM set

a 16-bit Thumb set

The Thumb set’s 16-bit instruction length allows it to approach higher density compared to standard ARM code while retaining most of the ARM’s performance.

7. On-chip flash programming memory (LPC2458/68/78)

The LPC2400 incorporates 512 kB Flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades.

The Flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at speeds of 72 MHz.

The LPC2400 provides a minimum of 100000 write/erase cycles and 20 years of data retention.

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

9 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

8. On-chip SRAM

The LPC2400 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM associated with the second AHB bus can be used both for data and code storage, too. Remaining SRAM such as a 4 kB USB FIFO and a 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply.

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

10 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

9. LPC2458 block diagram

 

 

XTAL1

TMS TDI trace signals

XTAL2

VDD(3V3)

 

 

 

VDDA

 

 

 

 

TRST TCK TDO

 

 

RESET

 

 

 

 

 

 

EXTIN0 DBGEN

 

 

 

 

 

 

 

 

 

 

 

LPC2458

 

 

 

 

 

 

 

 

SYSTEM

VREF

P0, P1, P2,

64 kB

512 kB

 

 

EMULATION TRACE MODULE

PLL

 

 

VSSA, VSSIO, VSSCORE

 

TEST/DEBUG

 

 

FUNCTIONS

P3, P4

 

SRAM

FLASH

INTERFACE

 

 

 

 

VDD(DCDC)(3V3)

 

 

 

 

 

 

 

 

 

 

HIGH-SPEED

 

 

 

 

system

 

INTERNAL RC

 

 

 

 

 

 

clock

 

 

 

 

INTERNAL

ARM7TDMI-S

 

 

OSCILLATOR

 

 

GPI/O

 

 

 

 

 

 

 

 

 

 

 

136 PINS

CONTROLLERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TOTAL

SRAM

FLASH

 

 

 

 

 

EXTERNAL

D[15:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 kB

 

 

 

 

 

 

 

VIC

MEMORY

A[19:0]

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

CONTROLLER

control lines

 

 

 

 

 

 

 

 

 

 

 

AHB2

 

AHB

 

AHB

 

 

 

AHB1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BRIDGE

 

BRIDGE

 

 

 

 

 

 

ETHERNET

16 kB

MASTER

AHB TO

SLAVE

 

 

USB DEVICE/

VBUS

MII/RMII

SRAM

PORT

AHB BRIDGE PORT

 

 

HOST/OTG WITH

port 1

MAC WITH

 

 

 

 

 

 

 

 

 

4 kB RAM AND DMA

port 2

 

 

 

 

 

 

 

 

 

DMA

 

 

 

AHB TO

 

 

 

 

 

 

 

 

 

 

 

 

 

GP DMA

 

 

 

 

 

 

APB BRIDGE

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROLLER

 

EINT3 to EINT0

EXTERNAL INTERRUPTS

 

 

 

 

 

 

 

I2SRX_CLK

P0, P2

 

 

 

 

 

 

 

I2STX_CLK

 

 

 

 

 

 

 

 

 

 

2 × CAP0/CAP1/

 

 

 

 

 

 

 

 

I2S INTERFACE

I2SRX_WS

CAPTURE/COMPARE

 

 

 

 

 

I2STX_WS

CAP2/CAP3

TIMER0/TIMER1/

 

 

 

 

 

 

 

I2SRX_SDA

4 × MAT2,

TIMER2/TIMER3

 

 

 

 

 

 

 

I2STX_SDA

2 × MAT3,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCK, SCK0

2 × MAT1/MAT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOSI, MOSI0

6 × PWM0, PWM1

 

 

 

 

 

 

SPI, SSP0 INTERFACE

PWM0, PWM1

 

 

 

 

MISO, MISO0

 

 

 

 

 

 

 

 

1 × PCAP0,

 

 

 

 

 

 

 

 

SSEL, SSEL0

 

 

 

 

 

 

 

 

 

 

2 × PCAP1

 

 

 

 

 

 

 

 

 

 

SCK1

 

 

 

 

 

 

 

 

 

 

 

 

LEGACY GPI/O

 

 

 

 

 

SSP1 INTERFACE

MOSI1

P0, P1

 

 

 

 

 

MISO1

64 PINS TOTAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSEL1

 

 

 

 

 

 

 

 

 

 

 

8 × AD0

A/D CONVERTER

 

 

 

 

 

SD/MMC CARD

MCICLK, MCIPWR

 

 

 

 

 

MCICMD,

 

 

 

 

 

 

 

 

 

INTERFACE

 

 

 

 

 

 

 

 

 

 

 

MCIDAT[3:0]

AOUT

D/A CONVERTER

 

 

 

UART0, UART2, UART3

TXD0, TXD2, TXD3

 

 

 

 

 

 

 

RXD0, RXD2, RXD3

 

 

 

 

 

 

 

 

 

 

 

VBAT

2 kB BATTERY RAM

 

 

 

 

 

 

 

TXD1

 

 

 

 

 

 

 

 

 

 

 

power domain 2

 

 

 

 

 

 

 

 

UART1

RXD1

RTCX1

 

REAL-

 

 

 

 

 

DTR1, RTS1

RTC

 

 

 

 

 

 

 

 

TIME

 

 

 

 

 

 

 

DSR1, CTS1, DCD1,

RTCX2

 

 

 

 

 

 

 

OSCILLATOR

 

 

 

 

 

 

 

CLOCK

 

 

 

 

 

 

 

RI1

 

 

 

 

 

 

 

 

 

ALARM

 

 

 

 

 

 

 

 

CAN1, CAN2

RD1, RD2

 

 

 

 

 

 

 

 

 

TD1, TD2

 

 

 

 

 

 

 

 

 

 

 

 

WATCHDOG TIMER

 

 

 

 

 

 

 

SCL0, SCL1, SCL2

 

 

 

 

 

 

 

 

 

I2C0, I2C1, I2C2

 

 

 

 

 

 

 

 

 

SDA0, SDA1, SDA2

 

 

 

 

 

 

 

 

 

 

 

 

SYSTEM CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

002aad093

 

Fig 1. LPC2458 block diagram

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

11 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

10. LPC2420/60 block diagram

 

 

 

 

 

 

 

 

 

 

 

XTAL1

VDD(3V3)

 

 

 

 

 

TMS

TDI

trace signals

 

 

XTAL2

 

 

 

 

 

TRST TCK TDO

 

 

 

 

 

VDDA

 

 

 

 

 

 

 

 

RESET

 

 

 

 

 

 

 

EXTIN0 DBGEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2420/2460

 

 

 

 

 

 

 

SYSTEM

VREF

P0, P1, P2,

 

 

 

 

PLL

 

 

VSSA, VSSCORE, VSSIO

 

64 kB

TEST/DEBUG

EMULATION TRACE MODULE

 

 

FUNCTIONS

 

P3, P4

 

SRAM

INTERFACE

 

 

 

 

 

 

VDD(DCDC)(3V3)

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH-SPEED

 

 

 

 

system

 

INTERNAL RC

 

 

 

 

 

 

 

clock

 

 

 

 

 

INTERNAL

ARM7TDMI-S

 

 

OSCILLATOR

 

 

 

GPI/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

160 PINS

SRAM

 

 

 

 

 

 

 

 

 

 

 

TOTAL

CONTROLLER

 

 

 

 

 

EXTERNAL

D[31:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 kB

 

 

 

 

 

 

 

 

VIC

MEMORY

A[23:0]

 

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

 

CONTROLLER

control lines

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB2

AHB

 

 

AHB

 

 

 

AHB1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BRIDGE

 

 

BRIDGE

 

 

 

 

 

 

 

 

ETHERNET

16 kB

MASTER

AHB TO

 

SLAVE

 

 

USB DEVICE/

VBUS

 

MII/RMII

SRAM

PORT AHB BRIDGE PORT

 

 

HOST/OTG WITH

port1

 

MAC WITH

 

 

 

(1)

 

 

 

 

 

 

4 kB RAM AND DMA

port2

 

 

 

 

 

 

 

 

 

 

DMA(1)

 

 

AHB TO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GP DMA

 

 

 

 

 

 

 

APB BRIDGE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROLLER

 

EINT3 to EINT0

EXTERNAL INTERRUPTS

 

 

 

 

 

 

 

 

 

I2SRX_CLK

 

P0, P2

 

 

 

 

 

 

 

 

 

I2STX_CLK

 

 

 

 

 

 

 

 

 

 

 

 

2 × CAP0/CAP1/

 

 

 

 

 

 

 

 

I2S INTERFACE

 

I2SRX_WS

CAPTURE/COMPARE

 

 

 

 

 

 

 

I2STX_WS

CAP2/CAP3

TIMER0/TIMER1/

 

 

 

 

 

 

 

 

 

I2SRX_SDA

4 × MAT2/MAT3,

TIMER2/TIMER3

 

 

 

 

 

 

 

 

 

I2STX_SDA

 

2 × MAT0,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCK, SCK0

 

3 × MAT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOSI, MOSI0

6 × PWM0/PWM1

 

 

 

 

 

 

SPI, SSP0 INTERFACE

PWM0, PWM1

 

 

 

 

MISO, MISO0

1 × PCAP0,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSEL, SSEL0

2 × PCAP1

 

 

 

 

 

 

 

 

 

 

 

SCK1

 

 

LEGACY GPI/O

 

 

 

 

 

 

 

 

 

 

P0, P1

 

 

 

 

 

SSP1 INTERFACE

MOSI1

 

64 PINS TOTAL

 

 

 

 

 

 

 

 

 

 

 

MISO1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSEL1

 

8 × AD0

A/D CONVERTER

 

 

 

 

 

 

SD/MMC CARD

 

MCICLK, MCIPWR

 

 

 

 

 

 

 

 

 

 

 

MCICMD,

 

 

 

 

 

 

 

 

 

 

INTERFACE

 

 

AOUT

D/A CONVERTER

 

 

 

 

 

 

 

 

 

MCIDAT[3:0]

 

 

 

 

 

 

 

 

 

 

TXD0, TXD2, TXD3

 

 

 

 

 

 

 

 

UART0, UART2, UART3

 

 

 

 

 

 

 

 

RXD0, RXD2, RXD3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VBAT

2 kB BATTERY RAM

 

 

 

 

 

 

 

 

 

 

power domain 2

 

 

 

 

 

 

 

 

 

 

 

TXD1

 

 

 

 

 

 

 

 

 

 

 

RXD1

 

 

 

REAL-

 

 

 

 

 

 

UART1

 

 

RTCX1

RTC

 

 

 

 

 

 

 

DTR1, RTS1

 

RTCX2

TIME

 

 

 

 

 

 

 

 

 

 

 

OSCILLATOR

 

 

 

 

 

 

 

 

 

DSR1, CTS1, DCD1,

 

CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RI1

 

ALARM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD1, RD2

 

 

 

 

 

 

 

 

 

CAN1(1), CAN2(1)

 

 

WATCHDOG TIMER

 

 

 

 

 

TD1, TD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C0, I2C1, I2C2

 

SCL0, SCL1, SCL2

 

 

SYSTEM CONTROL

 

 

 

 

 

 

 

SDA0, SDA1, SDA2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

002aad313

 

(1)

LPC2460 only.

 

 

 

 

 

 

 

 

 

 

 

Fig 2.

LPC2460 block diagram

 

 

 

 

 

 

 

 

 

 

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

12 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

11. LPC2468 block diagram

 

 

XTAL1

TMS TDI trace signals

XTAL2

VDD(3V3)

 

 

 

VDDA

 

 

 

 

TRST TCK TDO

 

 

 

RESET

 

 

 

 

 

 

EXTIN0 DBGEN

 

 

 

 

 

 

 

 

 

 

 

 

LPC2468

 

 

 

 

 

 

 

 

SYSTEM

VREF

P0, P1, P2,

64 kB

512 kB

 

 

EMULATION TRACE MODULE

PLL

 

 

VSSA, VSSIO, VSSCORE

 

TEST/DEBUG

 

 

FUNCTIONS

P3, P4

 

SRAM

FLASH

INTERFACE

 

 

 

 

VDD(DCDC)(3V3)

 

 

 

 

 

 

 

 

 

 

HIGH-SPEED

 

 

 

 

system

 

INTERNAL RC

 

 

 

 

 

 

clock

 

 

 

 

INTERNAL

ARM7TDMI-S

 

 

OSCILLATOR

 

 

GPI/O

 

 

 

 

 

 

 

 

 

 

 

160 PINS

CONTROLLERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TOTAL

SRAM

FLASH

 

 

 

 

 

EXTERNAL

D[31:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 kB

 

 

 

 

 

 

 

VIC

MEMORY

A[23:0]

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

CONTROLLER

control lines

 

 

 

 

 

 

 

 

 

 

 

AHB2

 

AHB

 

AHB

 

 

 

AHB1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BRIDGE

 

BRIDGE

 

 

 

 

 

 

ETHERNET

16 kB

MASTER

AHB TO

SLAVE

 

 

USB DEVICE/

VBUS

MII/RMII

SRAM

PORT

AHB BRIDGE PORT

 

 

HOST/OTG WITH

port1

MAC WITH

 

 

 

 

 

 

 

 

 

4 kB RAM AND DMA

port2

 

 

 

 

 

 

 

 

 

DMA

 

 

 

AHB TO

 

 

 

 

 

 

 

 

 

 

 

 

 

GP DMA

 

 

 

 

 

 

APB BRIDGE

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROLLER

 

EINT3 to EINT0

EXTERNAL INTERRUPTS

 

 

 

 

 

 

 

I2SRX_CLK

P0, P2

 

 

 

 

 

 

 

I2STX_CLK

 

 

 

 

 

 

 

 

 

 

2 × CAP0/CAP1/

 

 

 

 

 

 

 

 

I2S INTERFACE

I2SRX_WS

CAPTURE/COMPARE

 

 

 

 

 

I2STX_WS

CAP2/CAP3

TIMER0/TIMER1/

 

 

 

 

 

 

 

I2SRX_SDA

4 × MAT2/MAT3,

TIMER2/TIMER3

 

 

 

 

 

 

 

I2STX_SDA

2 × MAT0,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCK, SCK0

3 × MAT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOSI, MOSI0

6 × PWM0/PWM1

 

 

 

 

 

 

SPI, SSP0 INTERFACE

PWM0, PWM1

 

 

 

 

MISO, MISO0

1 × PCAP0,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSEL, SSEL0

2 × PCAP1

 

 

 

 

 

 

 

 

 

 

SCK1

 

LEGACY GPI/O

 

 

 

 

 

 

 

 

P0, P1

 

 

 

 

 

SSP1 INTERFACE

MOSI1

64 PINS TOTAL

 

 

 

 

 

 

 

 

 

 

MISO1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSEL1

8 × AD0

A/D CONVERTER

 

 

 

 

 

SD/MMC CARD

MCICLK, MCIPWR

 

 

 

 

 

 

 

 

 

MCICMD,

 

 

 

 

 

 

 

 

 

INTERFACE

AOUT

D/A CONVERTER

 

 

 

 

 

 

 

MCIDAT[3:0]

 

 

 

 

 

 

 

TXD0, TXD2, TXD3

 

 

 

 

 

 

 

UART0, UART2, UART3

 

 

 

 

 

 

 

RXD0, RXD2, RXD3

 

 

 

 

 

 

 

 

 

 

 

VBAT

2 kB BATTERY RAM

 

 

 

 

 

 

 

 

power domain 2

 

 

 

 

 

 

 

 

 

 

TXD1

 

 

 

 

 

 

 

 

 

 

RXD1

 

 

REAL-

 

 

 

 

 

UART1

RTCX1

RTC

 

 

 

 

 

DTR1, RTS1

RTCX2

TIME

 

 

 

 

 

 

 

 

OSCILLATOR

 

 

 

 

 

 

 

DSR1, CTS1, DCD1,

CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RI1

ALARM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD1, RD2

 

 

 

 

 

 

 

 

 

CAN1, CAN2

 

WATCHDOG TIMER

 

 

 

 

 

TD1, TD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C0, I2C1, I2C2

SCL0, SCL1, SCL2

 

SYSTEM CONTROL

 

 

 

 

 

SDA0, SDA1, SDA2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

002aac721

 

Fig 3. LPC2468 block diagram

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

13 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

12. LPC2470 block diagram

 

 

XTAL1

TMS TDI trace signals

XTAL2

VDD(3V3)

 

 

 

VDDA

 

 

 

TRST TCK TDO

 

 

 

RESET

 

 

 

 

 

EXTIN0 DBGEN

 

 

 

 

 

 

 

 

 

 

 

LPC2470

 

 

 

 

 

 

 

SYSTEM

VREF

P0, P1, P2,

64 kB

 

 

EMULATION TRACE MODULE

PLL

 

 

VSSA, VSSCORE, VSSIO

 

TEST/DEBUG

 

 

FUNCTIONS

P3, P4

 

SRAM

INTERFACE

 

 

 

 

VDD(DCDC)(3V3)

 

 

 

 

 

 

 

 

 

HIGH-SPEED

 

 

 

system

 

INTERNAL RC

 

 

 

 

 

clock

 

 

 

 

INTERNAL

ARM7TDMI-S

 

 

OSCILLATOR

 

 

GPI/O

 

 

 

 

 

 

 

 

 

 

 

160 PINS

SRAM

 

 

 

 

 

 

 

 

TOTAL

CONTROLLER

 

 

 

 

EXTERNAL

D[31:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

16 kB

 

 

 

 

 

 

VIC

MEMORY

A[23:0]

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

CONTROLLER

control lines

 

 

 

 

 

 

 

 

 

 

AHB2

AHB

 

AHB

 

 

 

AHB1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BRIDGE

 

BRIDGE

 

 

 

 

 

 

ETHERNET

16 kB

MASTER

AHB TO

SLAVE

 

 

USB DEVICE/

VBUS

MII/RMII

SRAM

PORT

AHB BRIDGE PORT

 

 

HOST/OTG WITH

port1

MAC WITH

 

 

 

 

 

 

 

 

4 kB RAM AND DMA

port2

 

 

 

 

 

 

 

 

DMA

 

 

AHB TO

 

 

 

 

 

 

 

 

 

 

 

 

GP DMA

 

 

 

 

 

APB BRIDGE

 

 

 

 

 

 

 

 

 

 

 

 

CONTROLLER

 

EINT3 to EINT0

EXTERNAL INTERRUPTS

 

 

 

 

 

LCD INTERFACE

8 × LCD control

P0, P2

 

 

 

 

 

LCDVD[23:0]

 

 

 

 

 

 

 

 

WITH DMA

 

 

 

 

 

 

 

 

 

LCDCLKIN

2 × CAP0/CAP1/

 

 

 

 

 

 

 

 

 

CAPTURE/COMPARE

 

 

 

 

 

 

 

 

CAP2/CAP3

 

 

 

 

 

 

 

 

TIMER0/TIMER1/

 

 

 

 

 

 

 

 

4 × MAT2/MAT3,

 

 

 

 

 

 

 

 

TIMER2/TIMER3

 

 

 

 

 

 

 

3 × I2SRX

2 × MAT0,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2S INTERFACE

3 × MAT1

 

 

 

 

 

 

 

3 × I2STX

 

 

 

 

 

 

 

 

 

6 × PWM0/PWM1

PWM0, PWM1

 

 

 

 

 

 

 

SCK, SCK0

1 × PCAP0,

 

 

 

 

 

 

 

 

 

 

 

 

SPI, SSP0 INTERFACE

MOSI, MOSI0

2 × PCAP1

 

 

 

 

 

MISO, MISO0

 

LEGACY GPI/O

 

 

 

 

 

 

 

SSEL, SSEL0

P0, P1

 

 

 

 

 

 

 

 

64 PINS TOTAL

 

 

 

 

 

 

 

SCK1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSP1 INTERFACE

MOSI1

 

 

 

 

 

 

 

MISO1

8 × AD0

A/D CONVERTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSEL1

 

 

 

 

 

 

 

 

 

 

AOUT

D/A CONVERTER

 

 

 

 

 

SD/MMC CARD

MCICLK, MCIPWR

 

 

 

 

 

MCICMD,

 

 

 

 

 

INTERFACE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCIDAT[3:0]

VBAT

2 kB BATTERY RAM

 

 

 

UART0, UART2, UART3

TXD0, TXD2, TXD3

 

 

 

 

 

 

RXD0, RXD2, RXD3

power domain 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RTCX1

RTC

REAL-

 

 

 

 

 

 

 

TXD1, DTR1, RTS1

TIME

 

 

 

 

 

UART1

RTCX2

 

 

 

 

 

OSCILLATOR

 

 

 

 

 

RXD1, DSR1, CTS1,

CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCD1, RI1

ALARM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD1, RD2

 

 

 

 

 

 

 

 

CAN1, CAN2

 

WATCHDOG TIMER

 

 

 

 

 

TD1, TD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C0, I2C1, I2C2

SCL0, SCL1, SCL2

 

SYSTEM CONTROL

 

 

 

 

 

SDA0, SDA1, SDA2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

002aad317

 

Fig 4. LPC2470 block diagram

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

14 of 792

NXP Semiconductors

UM10237

 

Chapter 1: LPC24XX Introductory information

13. LPC2478 block diagram

 

 

XTAL1

TMS TDI trace signals

XTAL2

VDD(3V3)

 

 

 

VDDA

 

 

 

 

TRST TCK TDO

 

 

 

RESET

 

 

 

 

 

 

EXTIN0 DBGEN

 

 

 

 

 

 

 

 

 

 

 

 

LPC2478

 

 

 

 

 

 

 

 

SYSTEM

VREF

P0, P1, P2,

64 kB

512 kB

 

 

EMULATION TRACE MODULE

PLL

 

 

VSSA, VSSIO, VSSCORE

 

TEST/DEBUG

 

 

FUNCTIONS

P3, P4

 

SRAM

FLASH

INTERFACE

 

 

 

 

VDD(DCDC)(3V3)

 

 

 

 

 

 

 

 

 

 

HIGH-SPEED

 

 

 

 

system

 

INTERNAL RC

 

 

 

 

 

 

clock

 

 

 

 

INTERNAL

ARM7TDMI-S

 

 

OSCILLATOR

 

 

GPI/O

 

 

 

 

 

 

 

 

 

 

 

160 PINS

CONTROLLERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TOTAL

SRAM

FLASH

 

 

 

 

 

EXTERNAL

D[31:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 kB

 

 

 

 

 

 

 

VIC

MEMORY

A[23:0]

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

CONTROLLER

control lines

 

 

 

 

 

 

 

 

 

 

 

AHB2

 

AHB

 

AHB

 

 

 

AHB1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BRIDGE

 

BRIDGE

 

 

 

 

 

 

ETHERNET

16 kB

MASTER

AHB TO

SLAVE

 

 

USB DEVICE/

VBUS

MII/RMII

SRAM

PORT

AHB BRIDGE PORT

 

 

HOST/OTG WITH

port1

MAC WITH

 

 

 

 

 

 

 

 

 

4 kB RAM AND DMA

port2

 

 

 

 

 

 

 

 

 

DMA

 

 

 

AHB TO

 

 

 

 

 

 

 

 

 

 

 

 

 

GP DMA

 

 

 

 

 

 

APB BRIDGE

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROLLER

 

EINT3 to EINT0

EXTERNAL INTERRUPTS

 

 

 

 

 

LCD INTERFACE

8 × LCD control

P0, P2

 

 

 

 

 

LCDVD[23:0]

 

 

 

 

 

 

 

 

 

WITH DMA

 

 

 

 

 

 

 

 

 

 

LCDCLKIN

2 × CAP0/CAP1/

 

 

 

 

 

 

 

 

 

 

CAPTURE/COMPARE

 

 

 

 

 

 

 

 

CAP2/CAP3

 

 

 

 

 

 

 

 

TIMER0/TIMER1/

 

 

 

 

 

 

 

 

4 × MAT2/MAT3,

 

 

 

 

 

 

 

 

TIMER2/TIMER3

 

 

 

 

 

 

 

3 × I2SRX

2 × MAT0,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2S INTERFACE

3 × MAT1

 

 

 

 

 

 

 

 

3 × I2STX

 

 

 

 

 

 

 

 

 

 

6 × PWM0/PWM1

PWM0, PWM1

 

 

 

 

 

 

 

 

SCK0, SCK

1 × PCAP0,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSP0/SPI INTERFACE

MOSI0, MOSI

2 × PCAP1

 

 

 

 

 

 

MISO0, MISO

 

LEGACY GPI/O

 

 

 

 

 

 

 

 

SSEL0, SSEL

P0, P1

 

 

 

 

 

 

 

 

 

64 PINS TOTAL

 

 

 

 

 

 

 

 

SCK1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSP1 INTERFACE

MOSI1

 

 

 

 

 

 

 

 

MISO1

8 × AD0

A/D CONVERTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSEL1

 

 

 

 

 

 

 

 

 

 

 

AOUT

D/A CONVERTER

 

 

 

 

 

SD/MMC CARD

MCICLK, MCIPWR

 

 

 

 

 

MCICMD,

 

 

 

 

 

INTERFACE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCIDAT[3:0]

VBAT

2 kB BATTERY RAM

 

 

 

UART0, UART2, UART3

TXD0, TXD2, TXD3

 

 

 

 

 

 

 

RXD0, RXD2, RXD3

power domain 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RTCX1

RTC

REAL-

 

 

 

 

 

 

 

TXD1, DTR1, RTS1

TIME

 

 

 

 

 

UART1

RTCX2

 

 

 

 

 

OSCILLATOR

 

 

 

 

 

RXD1, DSR1, CTS1,

CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCD1, RI1

ALARM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD1, RD2

 

 

 

 

 

 

 

 

 

CAN1, CAN2

 

WATCHDOG TIMER

 

 

 

 

 

TD1, TD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C0, I2C1, I2C2

SCL0, SCL1, SCL2

 

SYSTEM CONTROL

 

 

 

 

 

SDA0, SDA1, SDA2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

002aac805

 

Fig 5. LPC2478 block diagram

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

15 of 792

UM10237

Chapter 2: LPC24XX Memory mapping

Rev. 04 — 26 August 2009 User manual

1. How to read this chapter

The memory addressing and mapping for different LPC2400 parts depends on flash size, EMC size, and the LCD peripheral, see Table 2–13.

Table 13. LPC2400 memory options and addressing

 

Flash

LCD

EMC

Memory map

 

Table 2–19;

Figure 2–8

 

 

 

Table 2–21

 

 

 

LPC2458

512 kB

no

16-bit

Table 2–14

 

 

 

 

 

LPC2420

flashless

no

32-bit

Table 2–15

 

 

 

 

 

LPC2460

flashless

no

32-bit

Table 2–15

 

 

 

 

 

LPC2468

512 kB

no

32-bit

Table 2–16

 

 

 

 

 

LPC2470

flashless

yes

32-bit

Table 2–15

 

 

 

 

 

LPC2478

512 kB

yes

32-bit

Table 2–16

 

 

 

 

 

2. Memory map and peripheral addressing

ARM processors have a single 4 GB address space. The following table shows how this space is used on NXP embedded ARM devices.

Table 14. LPC2458 memory usage and details

Address range

General use

Address range details and description

 

0x0000 0000 to

On-chip non-volatile

0x0000 0000 - 0x0007 FFFF

Flash Memory (512 kB)

0x3FFF FFFF

memory and Fast I/O

 

 

0x3FFF C000 - 0x3FFF FFFF

Fast GPIO registers

 

 

 

 

 

 

0x4000 0000 to

On-chip RAM

0x4000 0000 - 0x4000 FFFF

RAM (64 kB)

0x7FFF FFFF

 

 

 

 

0x7FE0 0000 - 0x7FE0 3FFF

Ethernet RAM (16 kB)

 

 

 

 

 

 

 

 

0x7FD0 0000 - 0x7FD0 3FFF

USB RAM (16 kB)

 

 

 

 

0x8000 0000 to

Off-Chip Memory

Two static memory banks, 1 MB each

 

0xDFFF FFFF

 

 

 

 

0x8000 0000 - 0x800F FFFF

Static memory bank 0

 

 

 

 

 

 

 

 

0x8100 0000 - 0x810F FFFF

Static memory bank 1

 

 

 

 

 

Two dynamic memory banks, 256 MB each

 

 

 

 

 

 

0xA000 0000 - 0xAFFF FFFF

Dynamic memory bank 0

 

 

 

 

 

 

0xB000 0000 - 0xBFFF FFFF

Dynamic memory bank 1

 

 

 

 

0xE000 0000 to

APB Peripherals

36 peripheral blocks, 16 kB each

 

0xEFFF FFFF

 

 

 

 

 

 

 

0xF000 0000 to

AHB peripherals

 

 

0xFFFF FFFF

 

 

 

 

 

 

 

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

16 of 792

NXP Semiconductors

 

UM10237

 

 

Chapter 2: LPC24XX Memory mapping

Table 15. LPC2420/60/70 memory usage and details

 

 

 

 

 

Address range

General use

Address range details and description

 

0x0000 0000 to

Fast I/O

0x0000 0000 - 0x0007 FFFF

Reserved (flashless parts)

0x3FFF FFFF

 

 

 

 

0x3FFF C000 - 0x3FFF FFFF

Fast GPIO registers

 

 

 

 

 

 

0x4000 0000 to

On-chip RAM

0x4000 0000 - 0x4000 FFFF

RAM (64 kB)

0x7FFF FFFF

 

 

 

 

0x7FE0 0000 - 0x7FE0 3FFF

Ethernet RAM (16 kB) (LPC2460

 

 

 

 

 

only)

 

 

 

 

 

 

0x7FD0 0000 - 0x7FD0 3FFF

USB RAM (16 kB)

 

 

 

 

0x8000 0000 to

Off-Chip Memory

Four static memory banks, 16 MB each

 

0xDFFF FFFF

 

 

 

 

0x8000 0000 - 0x80FF FFFF

Static memory bank 0

 

 

 

 

 

 

 

 

0x8100 0000 - 0x81FF FFFF

Static memory bank 1

 

 

 

 

 

 

0x8200 0000 - 0x82FF FFFF

Static memory bank 2

 

 

 

 

 

 

0x8300 0000 - 0x83FF FFFF

Static memory bank 3

 

 

 

 

 

Four dynamic memory banks, 256 MB each

 

 

 

 

 

 

0xA000 0000 - 0xAFFF FFFF

Dynamic memory bank 0

 

 

 

 

 

 

0xB000 0000 - 0xBFFF FFFF

Dynamic memory bank 1

 

 

 

 

 

 

0xC000 0000 - 0xCFFF FFFF

Dynamic memory bank 2

 

 

 

 

 

 

0xD000 0000 - 0xDFFF FFFF

Dynamic memory bank 3

 

 

 

 

0xE000 0000 to

APB Peripherals

36 peripheral blocks, 16 kB each

 

0xEFFF FFFF

 

 

 

0xF000 0000 to

AHB peripherals

 

 

0xFFFF FFFF

 

 

 

 

 

Table 16. LPC2468/78 memory usage and details

 

 

 

 

 

Address range

General use

Address range details and description

 

0x0000 0000 to

On-chip non-volatile

0x0000 0000 - 0x0007 FFFF

Flash Memory (512 kB)

0x3FFF FFFF

memory and Fast I/O

 

 

0x3FFF C000 - 0x3FFF FFFF

Fast GPIO registers

 

 

 

 

 

 

0x4000 0000 to

On-chip RAM

0x4000 0000 - 0x4000 FFFF

RAM (64 kB)

0x7FFF FFFF

 

 

 

 

0x7FE0 0000 - 0x7FE0 3FFF

Ethernet RAM (16 kB)

 

 

 

 

 

 

 

 

0x7FD0 0000 - 0x7FD0 3FFF

USB RAM (16 kB)

 

 

 

 

0x8000 0000 to

Off-Chip Memory

Four static memory banks, 16 MB each

 

0xDFFF FFFF

 

 

 

 

0x8000 0000 - 0x80FF FFFF

Static memory bank 0

 

 

 

 

 

 

 

 

0x8100 0000 - 0x81FF FFFF

Static memory bank 1

 

 

 

 

 

 

0x8200 0000 - 0x82FF FFFF

Static memory bank 2

 

 

 

 

 

 

0x8300 0000 - 0x83FF FFFF

Static memory bank 3

 

 

 

 

 

Four dynamic memory banks, 256 MB each

 

 

 

 

 

 

0xA000 0000 - 0xAFFF FFFF

Dynamic memory bank 0

 

 

 

 

 

 

0xB000 0000 - 0xBFFF FFFF

Dynamic memory bank 1

 

 

 

 

 

 

0xC000 0000 - 0xCFFF FFFF

Dynamic memory bank 2

 

 

 

 

 

 

0xD000 0000 - 0xDFFF FFFF

Dynamic memory bank 3

 

 

 

 

0xE000 0000 to

APB Peripherals

36 peripheral blocks, 16 kB each

 

0xEFFF FFFF

 

 

 

 

 

 

 

0xF000 0000 to

AHB peripherals

 

 

0xFFFF FFFF

 

 

 

 

 

 

 

UM10237_4

 

 

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

17 of 792

NXP Semiconductors

UM10237

 

Chapter 2: LPC24XX Memory mapping

3. Memory maps

The LPC2400 incorporates several distinct memory regions, shown in the following figures. Figure 2–6 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.

4.0 GB

 

0xFFFF FFFF

 

 

AHB PERIPHERALS

3.75 GB

 

0xF000 0000

 

APB PERIPHERALS

3.5 GB

 

0xE000 0000

EXTERNAL STATIC AND DYNAMIC MEMORY

2.0 GB

 

0x8000 0000

 

 

0x7FFF FFFF

 

BOOT ROM AND BOOT FLASH

RESERVED ADDRESS SPACE

1.0 GB

ON-CHIP STATIC RAM

 

0x4000 0000

 

 

0x3FFF FFFF

 

SPECIAL REGISTERS

 

 

0x3FFF 8000

 

RESERVED ADDRESS SPACE

 

 

 

 

ON-CHIP NON-VOLATILE MEMORY OR RESERVED

0.0 GB

 

0x0000 0000

Fig 6. LPC2400 system memory map

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Chapter 2: LPC24XX Memory mapping

4.0 GB

 

0xFFFF FFFF

 

 

 

 

AHB PERIPHERALS

4.0 GB - 2 MB

 

0xFFE0 0000

 

0xFFDF FFFF

 

 

RESERVED

3.75 GB

 

0xF000 0000

 

 

0xEFFF FFFF

RESERVED

3.5 GB + 2 MB

 

0xE020 0000

 

 

0xE01F FFFF

 

APB PERIPHERALS

3.5 GB

 

0xE000 0000

Fig 7. Peripheral memory map

Figure 8 and Table 2–17 show different views of the peripheral address space. Both the AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral.

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Chapter 2: LPC24XX Memory mapping

All peripheral register addresses are word aligned (to 32 bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8 bit) or half-word (16 bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.

VECTORED INTERRUPT CONTROLLER

(AHB PERIPHERAL #126)

NOT USED

(AHB PERIPHERAL #5)

LCD(1)

(AHB PERIPHERAL #4)

USB CONTROLLER (AHB PERIPHERAL #3)

EXTERNAL MEMORY CONTROLLER

(AHB PERIPHERAL #2)

GENERAL PURPOSE DMA CONTROLLER

(AHB PERIPHERAL #1)

ETHERNET CONTROLLER (AHB PERIPHERAL #0)

(1) LPC247x only.

Fig 8. AHB peripheral map

0xFFFF F000 (4G - 4K)

0xFFFF C000

0xFFFF 8000

0xFFE1 8000

0xFFE1 4000

0xFFE1 0000

0xFFE0 C000

0xFFE0 8000

0xFFE0 4000

0xFFE0 0000

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Chapter 2: LPC24XX Memory mapping

4. APB peripheral addresses

The following table shows the APB address map. No APB peripheral uses all of the 16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple locations within each 16 kB range.

Table 17. APB peripherals and base addresses

 

APB Peripheral

Base Address

Peripheral Name

0

0xE000 0000

Watchdog Timer

 

 

 

 

1

0xE000 4000

Timer 0

 

 

 

 

2

0xE000 8000

Timer 1

 

 

 

 

3

0xE000 C000

UART0

 

 

 

 

4

0xE001 0000

UART1

 

 

 

 

5

0xE001 4000

PWM0

 

 

 

 

6

0xE001 8000

PWM1

 

 

 

 

 

7

0xE001 C000

I2C0

8

0xE002 0000

SPI

 

 

 

 

9

0xE002 4000

RTC

 

 

 

 

10

0xE002 8000

GPIO

 

 

 

 

11

0xE002 C000

Pin Connect Block

 

 

 

 

12

0xE003 0000

SSP1

 

 

 

 

13

0xE003 4000

ADC

 

 

 

 

14

0xE003 8000

CAN Acceptance Filter RAM

 

 

 

 

15

0xE003 C000

CAN Acceptance Filter Registers

 

 

 

 

16

0xE004 0000

CAN Common Registers

 

 

 

 

17

0xE004 4000

CAN Controller 1

 

 

 

 

18

0xE004 8000

CAN Controller 2

 

 

 

 

 

19 to 22

0xE004 C000 to 0xE005 8000

Not used

 

 

 

 

 

23

0xE005 C000

I2C1

24

0xE006 0000

Not used

 

 

 

 

25

0xE006 4000

Not used

 

 

 

 

26

0xE006 8000

SSP0

 

 

 

 

27

0xE006 C000

DAC

 

 

 

 

28

0xE007 0000

Timer 2

 

 

 

 

29

0xE007 4000

Timer 3

 

 

 

 

30

0xE007 8000

UART2

 

 

 

 

31

0xE007 C000

UART3

 

 

 

 

 

32

0xE008 0000

I2C2

33

0xE008 4000

Battery RAM

 

 

 

 

 

34

0xE008 8000

I2S

35

0xE008 C000

SD/MMC Card Interface

 

 

 

 

 

36 to 126

0xE009 0000 to 0xE01F BFFF

Not used

 

 

 

 

127

0xE01F C000

System Control Block

 

 

 

 

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Chapter 2: LPC24XX Memory mapping

5. LPC2400 memory re-mapping and boot ROM

5.1 Memory map concepts and operating modes

The basic concept on the LPC2400 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.

Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C, as shown in Table 2–18 below), a small portion of the Boot ROM and SRAM spaces need to be re-mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 2–19. Re-mapping of the interrupts is accomplished via the Memory Mapping Control feature (Section 2–6 “Memory mapping control” on page 24).

Table 18. ARM exception vector locations

Address

Exception

0x0000

0000

Reset

 

 

 

0x0000

0004

Undefined Instruction

 

 

 

0x0000

0008

Software Interrupt

 

 

 

0x0000

000C

Prefetch Abort (instruction fetch memory fault)

 

 

 

0x0000

0010

Data Abort (data access memory fault)

 

 

 

0x0000

0014

Reserved

 

 

Note: Identified as reserved in ARM documentation, this location is used

 

 

by the Boot Loader as the Valid User Program key when booting from

 

 

on-chip flash memory. This is described in detail in Section 30–5.1.1.

 

 

 

0x0000

0018

IRQ

 

 

 

0x0000

001C

FIQ

 

 

 

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Chapter 2: LPC24XX Memory mapping

 

Table 19. LPC2400 Memory mapping modes

 

 

 

 

 

Mode

Activation

Usage

 

Boot

Hardware

The Boot Loader always executes after any reset. The Boot ROM

 

Loader

activation by

interrupt vectors are mapped to the bottom of memory to allow

 

mode

any Reset

handling exceptions and using interrupts during the Boot Loading

 

 

 

process. A sector of the flash memory (the Boot flash) is available to

 

 

 

hold part of the Boot Code.

 

 

 

 

 

User

Software

For LPC2400 parts with flash only. Activated by the Boot Loader when

 

Flash

activation by

a valid User Program Signature is recognized in memory and Boot

 

mode

Boot code

Loader operation is not forced. Interrupt vectors are not re-mapped

 

 

 

and are found in the bottom of the flash memory.

 

 

 

 

 

User RAM

Software

Activated by a User Program as desired. Interrupt vectors are

 

mode

activation by

re-mapped to the bottom of the Static RAM.

 

 

User program

 

 

 

 

 

 

User

Software

For LPC2400 parts with flash. Interrupt vectors are re-mapped to

 

External

activation by

external memory bank 0.[1]

 

memory

user code

 

 

mode

 

 

 

Software

For flashless parts LPC2420/60/70 only. Interrupt vectors are

 

 

 

 

activation by

re-mapped to external memory bank 0.[2]

 

 

boot code

 

 

 

 

 

[1]See EMCControl register address mirror bit in Table 5–68 for address of external memory bank 0.

[2]Connect external boot memory to chip select 1. During boot from external memory, the address mirror bit is set and memory bank addresses 0 and 1 are swapped.

5.2Memory re-mapping

In order to allow for compatibility with future derivatives, the entire Boot ROM is mapped to the top of the on-chip memory space. In this manner, the use of larger or smaller flash modules will not require changing the location of the Boot ROM (which would require changing the Boot Loader code itself) or changing the mapping of the Boot ROM interrupt vectors. Memory spaces other than the interrupt vectors remain in fixed locations. Figure 2–9 shows the on-chip memory mapping in the modes defined above.

The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an additional 32 bytes for a total of

64 bytes, that facilitates branching to interrupt handlers at distant physical addresses. The remapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical user program in the flash memory can place the entire FIQ handler at address

0x0000 001C without any need to consider memory boundaries. The vector contained in the SRAM, external memory, and Boot ROM must contain branches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers.

There are three reasons this configuration was chosen:

1.To give the FIQ handler in the flash memory the advantage of not having to take a memory boundary caused by the remapping into account.

2.Minimize the need to for the SRAM and Boot ROM vectors to deal with arbitrary boundaries in the middle of code space.

3.To provide space to store constants for jumping beyond the range of single word branch instructions.

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Chapter 2: LPC24XX Memory mapping

Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to appear in their original location in addition to the re-mapped address.

Details on re-mapping and examples can be found in Section 2–6 “Memory mapping control” on page 24.

6. Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. This allows code running in different memory spaces to have control of the interrupts.

6.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)

Whenever an exception handling is necessary, the microcontroller will fetch an instruction residing on exception corresponding address as described in Table 2–18 “ARM exception vector locations” on page 22. The MEMMAP register determines the source of data that will fill this table.

Table 20. Memory mapping control registers

Name

Description

Access

Reset

Address

 

 

 

value

 

MEMMAP

Memory mapping control. Selects whether the

R/W

0x00

0xE01F C040

 

ARM interrupt vectors are read from the Boot

 

 

 

 

ROM, User Flash, or RAM.

 

 

 

 

 

 

 

 

Table 21. Memory Mapping control register (MEMMAP - address 0xE01F C040) bit description

Bit

Symbol

Value

Description

Reset

 

 

 

 

value

1:0

MAP

00

Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.

00

 

 

 

 

 

 

 

01

User Flash Mode. Interrupt vectors are not re-mapped and reside

 

 

 

 

in Flash.

 

 

 

 

Remark: This mode is for parts with flash only. Value 01 is

 

 

 

 

reserved for flashless parts LPC2420/60/70.

 

 

 

 

 

 

 

 

10

User RAM Mode. Interrupt vectors are re-mapped to Static RAM.

 

 

 

 

 

 

 

 

11

User External Memory Mode. Interrupt vectors are re-mapped to

 

 

 

 

external memory bank 0.

 

Warning: Improper setting of this value may result in incorrect operation of the device.

7:2 -

-

Reserved, user software should not write ones to reserved bits.

NA

 

 

The value read from a reserved bit is not defined.

 

 

 

 

 

6.2 Memory mapping control usage notes

Memory Mapping Control simply selects one out of three available sources of data (sets of 64 bytes each) necessary for handling ARM exceptions (interrupts).

For example, whenever a Software Interrupt request is generated, ARM core will always fetch 32 bit data "residing" on 0x0000 0008 see Table 2–18 “ARM exception vector locations” on page 22. This means that when MEMMAP[1:0] = 10 (User RAM Mode),

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Chapter 2: LPC24XX Memory mapping

read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of MEMMAP[1:0] = 00 (Boot Loader Mode), read/fetch from 0x0000 0008 will provide data available also at 0x7FFF E008 (Boot ROM remapped from on-chip Bootloader).

2.0 GB

2.0GB - 8 kB

2.0GB - 64 kB

2.0 GB - 72 kB

1.0 GB

0.0 GB

EXTERNAL MEMORY INTERRUPT VECTORS

8 kB BOOT ROM

(BOOT ROM INTERRUPT VECTORS)

8 kB BOOT FLASH

(RE-MAPPED FROM TOP OF FLASH MEMORY)

RESERVED ADDRESS SPACE

64 kB STATIC RAM

(SRAM INTERRUPT VECTORS)

FAST GPIO REGISTERS

PARTCFG REGISTERS

RESERVED FOR ADDRESS SPACE

BOOT FLASH

512 kB FLASH MEMORY

ACTIVE INTERRUPT VECTORS

(FROM FLASH, SRAM, BOOT ROM, OR EXT MEMORY)

0x8000 0000 0x7FFF FFFF

0x7FFF E000 0x7FFE FFFF

0x7FFE E000

0x4001 0000

0x4000 FFFF

0x4000 0000 0x3FFF FFFF 0x3FFF C000 0x3FFF BFFF

0x3FFF 8000

0x0008 0000

0x0007 FFFF

0x0000 0000

Fig 9. Map of lower memory is showing re-mapped and re-mappable areas for a

LPC2400 part with flash

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Chapter 2: LPC24XX Memory mapping

7. Prefetch abort and data abort exceptions

The LPC2400 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are:

Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2400, these are:

Address space between On-Chip Non-Volatile Memory and the Special Register space. Labelled "Reserved for On-Chip Memory" in Figure 2–6.

Address space between On-Chip Static RAM and the Boot ROM. Labelled "Reserved Address Space" in Figure 2–6.

External Memory

Reserved regions of the AHB and APB spaces. See Figure 2–7.

Unassigned AHB peripheral spaces. See Figure 2–8.

Unassigned APB peripheral spaces. See Table 2–17.

For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or APB peripheral address, or to the Special Register space located just below the SRAM at addresses 0x3FFF8000 through 0x3FFFFFFF.

Within the address space of an existing APB peripheral, a data abort exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself. For example, an access to address 0xE000 D000 (an undefined address within the UART0 space) may result in an access to the register defined at address 0xE000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC2400 documentation and are not a supported feature.

If software executes a write directly to the flash memory, the MAM generates a data abort exception. Flash programming must be accomplished by using the specified flash programming interface provided by the Boot Code.

Note that the ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary.

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Chapter 3: LPC24XX System control

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1. Summary of system control block functions

The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include:

Reset

Brown-Out Detection

External Interrupt Inputs

Miscellaneous System Controls and Status

Code Security vs. Debugging

Each type of function has its own register(s) if any are required and unneeded bits are defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses

2. Pin description

Table 3–22 shows pins that are associated with system control block functions.

Table 22.

Pin summary

 

 

Pin name

Pin

Pin description

 

 

 

direction

 

 

EINT0

Input

External Interrupt Input 0 - An active low/high level or

 

 

 

 

falling/rising edge general purpose interrupt input. This pin may be

 

 

 

 

used to wake up the processor from Idle or Power-down modes.

 

 

 

 

 

EINT1

Input

External Interrupt Input 1 - See the EINT0 description above.

 

 

 

 

 

EINT2

Input

External Interrupt Input 2 - See the EINT0 description above.

 

 

 

 

 

EINT3

Input

External Interrupt Input 3 - See the EINT0 description above.

 

 

 

 

 

 

 

 

Input

External Reset input - A LOW on this pin resets the chip, causing

 

RESET

 

 

 

 

I/O ports and peripherals to take on their default states, and the

 

 

 

 

processor to begin execution at address 0x0000 0000.

 

 

 

 

 

3. Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

Table 23. Summary of system control registers

 

Name

Description

Access

Reset value[1]

Address

 

External interrupts

 

 

 

 

 

 

 

 

 

 

EXTINT

External Interrupt Flag Register

R/W

0x00

0xE01F C140

 

 

 

 

 

 

 

EXTMODE

External Interrupt Mode register

R/W

0x00

0xE01F C148

 

 

 

 

 

 

 

EXTPOLAR

External Interrupt Polarity Register

R/W

0x00

0xE01F C14C

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Chapter 3: LPC24XX System control

 

Table 23. Summary of system control registers

 

 

 

 

 

 

 

 

 

 

Name

Description

Access

Reset value[1]

Address

 

Reset

 

 

 

 

 

 

 

 

 

 

 

RSID

Reset Source Identification

R/W

see text

0xE01F C180

 

 

Register

 

 

 

 

 

 

 

 

 

AHB priority scheduling registers

 

 

 

 

 

 

 

 

 

 

AHBCFG1

Configures the AHB1 arbiter

R/W

0x0000 0145

0xE01F C188

 

 

 

 

 

 

 

AHBCFG2

Configures the AHB2 arbiter

R/W

0x0000 0145

0xE01F C18C

 

 

 

 

 

 

Syscon miscellaneous registers

 

 

 

 

 

 

 

 

 

 

SCS

System Control and Status

R/W

0x00

0xE01F C1A0

 

 

 

 

 

 

[1]Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

3.1External interrupt inputs

The LPC2400 includes four External Interrupt Inputs as selectable pin functions. In addition, external interrupts have the ability to wake up the CPU from Power-down mode. This is controlled by the register INTWAKE, which is described in the Clocking and Power Control chapter under the Power Control heading

3.1.1Register description

The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.

Table 24. External Interrupt registers

Name

Description

Access

Reset

Address

 

 

 

value[1]

 

EXTINT

The External Interrupt Flag Register contains

R/W

0x00

0xE01F C140

 

interrupt flags for EINT0, EINT1, EINT2 and

 

 

 

 

EINT3. See Table 3–25.

 

 

 

 

 

 

 

 

EXTMODE

The External Interrupt Mode Register controls

R/W

0x00

0xE01F C148

 

whether each pin is edgeor level-sensitive.

 

 

 

 

See Table 3–26.

 

 

 

EXTPOLAR

The External Interrupt Polarity Register controls

R/W

0x00

0xE01F C14C

 

which level or edge on each pin will cause an

 

 

 

 

interrupt. See Table 3–27.

 

 

 

 

 

 

 

 

[1]Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

3.1.2External Interrupt flag register (EXTINT - 0xE01F C140)

When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in this register. This asserts the corresponding interrupt request to the VIC, which will cause an interrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive state.

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Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise event that was just triggered by activity on the EINT pin will not be recognized in future.

Important: whenever a change of external interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), corresponding bit in the EXTINT register must be cleared! For details see Section 3–3.1.3 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” and Section 3–3.1.4 “External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.

For example, if a system wakes up from power-down using low level on external interrupt 0 pin, its post-wakeup code must reset EINT0 bit in order to allow future entry into the power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke power-down mode will fail. The same goes for external interrupt handling.

More details on power-down mode will be discussed in the following chapters.

Table 25. External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description

Bit

Symbol

Description

Reset

 

 

 

value

0

EINT0

In level-sensitive mode, this bit is set if the EINT0 function is selected for its

0

 

 

pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if

 

 

 

the EINT0 function is selected for its pin, and the selected edge occurs on

 

 

 

the pin.

 

 

 

This bit is cleared by writing a one to it, except in level sensitive mode when

 

 

 

the pin is in its active state.[1]

 

1

EINT1

In level-sensitive mode, this bit is set if the EINT1 function is selected for its

0

 

 

pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if

 

 

 

the EINT1 function is selected for its pin, and the selected edge occurs on

 

 

 

the pin.

 

 

 

This bit is cleared by writing a one to it, except in level sensitive mode when

 

 

 

the pin is in its active state.[1]

 

2

EINT2

In level-sensitive mode, this bit is set if the EINT2 function is selected for its

0

 

 

pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if

 

 

 

the EINT2 function is selected for its pin, and the selected edge occurs on

 

 

 

the pin.

 

 

 

This bit is cleared by writing a one to it, except in level sensitive mode when

 

 

 

the pin is in its active state.[1]

 

3

EINT3

In level-sensitive mode, this bit is set if the EINT3 function is selected for its

0

 

 

pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if

 

 

 

the EINT3 function is selected for its pin, and the selected edge occurs on

 

 

 

the pin.

 

 

 

This bit is cleared by writing a one to it, except in level sensitive mode when

 

 

 

the pin is in its active state.[1]

 

7:4

-

Reserved, user software should not write ones to reserved bits. The value

NA

 

 

read from a reserved bit is not defined.

 

 

 

 

 

[1]Example: If the EINTx is selected to be low level sensitive and low level is present on corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high.

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3.1.3External Interrupt Mode register (EXTMODE - 0xE01F C148)

The bits in this register select whether each EINT pin is levelor edge-sensitive. Only pins that are selected for the EINT function (see Section 9–5.5) and enabled in the VICIntEnable register (Section 7–3.4 “Interrupt Enable Register (VICIntEnable -

0xFFFF F010)”) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions).

Note: Software should only change a bit in this register when its interrupt is disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the mode and not having the EXTINT cleared.

Table 26. External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit description

Bit

Symbol

Value

Description

Reset

 

 

 

 

 

 

 

value

0

EXTMODE0

0

Level-sensitivity is selected for

 

 

0

EINT0.

 

 

 

 

 

 

 

 

1

 

is edge sensitive.

 

 

 

EINT0

 

 

 

 

 

 

 

 

1

EXTMODE1

0

Level-sensitivity is selected for

 

 

0

EINT1.

 

 

 

 

 

 

 

 

1

 

is edge sensitive.

 

 

 

EINT1

 

 

 

 

 

 

 

 

2

EXTMODE2

0

Level-sensitivity is selected for

 

 

0

EINT2.

 

 

 

 

 

 

 

 

1

 

is edge sensitive.

 

 

 

EINT2

 

 

 

 

 

 

 

 

3

EXTMODE3

0

Level-sensitivity is selected for

 

 

0

EINT3.

 

 

 

 

 

 

 

 

1

 

is edge sensitive.

 

 

 

EINT3

 

 

 

 

 

 

7:4

-

-

Reserved, user software should not write ones to reserved

NA

 

 

 

bits. The value read from a reserved bit is not defined.

 

3.1.4External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)

In level-sensitive mode, the bits in this register select whether the corresponding pin is highor low-active. In edge-sensitive mode, they select whether the pin is risingor falling-edge sensitive. Only pins that are selected for the EINT function (see

Section 9–5.5) and enabled in the VICIntEnable register (Section 7–3.4 “Interrupt Enable Register (VICIntEnable - 0xFFFF F010)”) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions).

Note: Software should only change a bit in this register when its interrupt is disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could be set by changing the polarity and not having the EXTINT cleared.

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Table 27. External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit

 

 

description

 

 

 

 

 

Bit

Symbol

Value

Description

Reset

 

 

 

 

 

 

 

value

0

EXTPOLAR0

0

 

 

is low-active or falling-edge sensitive (depending on

0

EINT0

 

 

 

 

EXTMODE0).

 

 

 

 

 

 

 

 

 

 

 

1

 

 

is high-active or rising-edge sensitive (depending on

 

 

 

 

EINT0

 

 

 

 

 

EXTMODE0).

 

 

 

 

 

 

 

 

1

EXTPOLAR1

0

 

 

is low-active or falling-edge sensitive (depending on

0

EINT1

 

 

 

 

EXTMODE1).

 

 

 

 

1

 

 

is high-active or rising-edge sensitive (depending on

 

 

 

 

EINT1

 

 

 

 

 

EXTMODE1).

 

 

 

 

 

 

 

 

2

EXTPOLAR2

0

 

 

is low-active or falling-edge sensitive (depending on

0

EINT2

 

 

 

 

EXTMODE2).

 

 

 

 

 

 

 

 

 

 

 

1

 

 

is high-active or rising-edge sensitive (depending on

 

 

 

 

EINT2

 

 

 

 

 

EXTMODE2).

 

3

EXTPOLAR3

0

 

 

is low-active or falling-edge sensitive (depending on

0

EINT3

 

 

 

 

EXTMODE3).

 

 

 

 

 

 

 

 

 

 

 

1

 

 

is high-active or rising-edge sensitive (depending on

 

 

 

 

EINT3

 

 

 

 

 

EXTMODE3).

 

 

 

 

 

 

 

7:4

-

-

Reserved, user software should not write ones to reserved

NA

 

 

 

 

bits. The value read from a reserved bit is not defined.

 

3.2 Reset

Reset has four sources on the LPC2400: the RESET pin, the Watchdog Reset, Power On Reset (POR) and the Brown Out Detection circuit (BOD). The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wakeup Timer (see description in Section 4–5 “Wakeup timer” in this chapter), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. The reset logic is shown in Figure 3–10.

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external

C

Reset to the

 

on-chip circuitry

 

reset

 

 

 

 

watchdog

Q

 

 

 

 

 

reset

S

Reset to

 

 

 

POR

 

PCON.PD

 

 

 

 

BOD

 

 

 

 

 

WAKEUP TIMER

 

power-

 

START

 

 

 

 

down

 

COUNT 2 n

C

 

internal RC

 

Q

EINT0 wakeup

oscillator

 

S

EINT1 wakeup

 

 

 

 

 

EINT2 wakeup

 

write “1”

 

 

from APB

 

EINT3 wakeup

 

 

 

 

 

RTC wakeup

 

reset

 

BOD wakeup

 

 

 

Ethernet MAC wakeup

 

 

APB read of

USB need_clk wakeup

 

 

 

 

PDBIT

CAN wakeup

 

 

 

 

in PCON

GPIO0 port wakeup

 

 

 

 

 

GPIO2 port wakeup

 

 

FOSC

 

 

 

 

 

 

to other

 

 

 

blocks

Fig 10. Reset block diagram including the wakeup timer

 

 

On the assertion of any of reset sources (POR, BOD reset, External reset and Watchdog reset), the following two sequences start simultaneously:

1.After IRC-start-up time (maximum of 60 μs on power-up), IRC provides stable clock output, the reset signal is latched and synchronized on the IRC clock. The 2-bit IRC wakeup timer starts counting when the synchronized reset is de-asserted. The boot code in the ROM starts when the 2-bit IRC wakeup timer times out. The boot code performs the boot tasks and may jump to the flash. If the flash is not ready to access, the MAM will insert wait cycles until the flash is ready.

2.After IRC-start-up time (maximum of 60 μs on power-up), IRC provides stable clock output, the reset signal is synchronized on the IRC clock. The flash wakeup-timer (9-bit) starts counting when the synchronized reset is de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it times out, the flash initialization sequence is started, which takes about 250 cycles. When it’s done, the MAM will be granted access to the flash.

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

Figure 3–11 shows an example of the relationship between the RESET, the IRC, and the processor status when the LPC2400 starts up after reset. For the start-up sequence of the main oscillator if enabled by the user code, see Section 4–2.2 “Main oscillator”.

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IRC

IRC

 

 

starts

stable

 

 

IRC status

 

 

 

RESET

 

 

 

VDD(3V3)

 

 

 

 

valid threshold

 

 

GND

30 μs

 

 

 

 

 

 

1 μs; IRC stability count

 

supply ramp-up

 

boot time

user code

time

 

 

 

 

8 μs

170 μs

160 μs

processor status

 

 

 

 

flash read

flash read

boot code

 

starts

finishes

execution

 

 

 

finishes;

 

 

 

user code starts

 

 

 

002aad482

Fig 11. Example of start-up after reset

 

 

 

The various Resets have some small differences. For example, a Power On Reset causes the value of certain pins to be latched to configure the part.

For more details on Reset, PLL and startup/boot code interaction see Section 4–3.2.2 “PLL and startup/boot code interaction”.

3.2.1Reset Source Identification Register (RSIR - 0xE01F C180)

This register contains one bit for each source of Reset. Writing a 1 to any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below.

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Table 28. Reset Source Identification register (RSID - address 0xE01F C180) bit description

 

 

 

 

 

 

 

 

Bit

Symbol

Description

Reset

 

 

 

 

 

 

value

0

POR

Assertion of the POR signal sets this bit, and clears all of the other bits in

See text

 

 

 

this register. But if another Reset signal (e.g., External Reset) remains

 

 

 

 

asserted after the POR signal is negated, then its bit is set. This bit is not

 

 

 

 

affected by any of the other sources of Reset.

 

 

 

 

 

 

 

 

1

EXTR

Assertion of the

 

signal sets this bit. This bit is cleared by POR,

See text

RESET

 

 

 

but is not affected by WDT or BOD reset.

 

2

WDTR

This bit is set when the Watchdog Timer times out and the WDTRESET

See text

 

 

 

bit in the Watchdog Mode Register is 1. It is cleared by any of the other

 

 

 

 

sources of Reset.

 

 

 

 

 

 

3

BODR

This bit is set when the 3.3 V power reaches a level below 2.6 V.

See text

 

 

 

If the VDD(DCDC)(3V3) voltage dips from 3.3 V to 2.5 V and backs up, the

 

 

 

 

BODR bit will be set to 1.

 

 

 

 

If the VDD(DCDC)(3V3) voltage dips from 3.3 V to 2.5 V and continues to

 

 

 

 

decline to the level at which POR is asserted (nominally 1 V), the BODR

 

 

 

 

bit is cleared.

 

 

 

 

if the VDD(DCDC)(3V3) voltage rises continuously from below 1 V to a level

 

 

 

 

above 2.6 V, the BODR will be set to 1.

 

 

 

 

This bit is not affected by External Reset nor Watchdog Reset.

 

 

 

 

Note: Only in case when a reset occurs and the POR = 0, the BODR bit

 

 

 

 

indicates if the VDD(DCDC)(3V3) voltage was below 2.6 V or not.

 

7:4

-

Reserved, user software should not write ones to reserved bits. The

NA

 

 

 

value read from a reserved bit is not defined.

 

 

 

 

 

 

 

 

3.3 AHB Configuration

The AHB configuration register allows changing AHB scheduling and arbitration strategies.

Table 29. AHB configuration register map

Name

Description

Access

Reset value

Address

AHBCFG1

Configures the AHB1 arbiter.

R/W

0x0000 0145

0xE01F

C188

 

 

 

 

 

 

AHBCFG2

Configures the AHB2 arbiter.

R/W

0x0000 0145

0xE01F

C18C

 

 

 

 

 

 

3.3.1AHB Arbiter Configuration register 1 (AHBCFG1 - 0xE01F C188)

By default, the AHB1 access is scheduled round-robin (bit 0 = 1). For round-robin scheduling, the default priority sequence will be CPU, DMA, AHB1, USB and LCD.

The AHB1 access priority can be configured as priority scheduling (bit 0 = 0) and priority of the each of the AHB1 bus masters can be set by writing the priority value (highest priority = 5, lowest priority = 1).

Masters with the same priority value are scheduled on a round-robin basis.

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Table 30. AHB Arbiter Configuration register 1 (AHBCFG1 - address 0xE01F C188) bit

 

 

description

 

 

 

 

Bit

Symbol

Value

Description

Reset

 

 

 

 

 

value

0

scheduler

0

Priority scheduling.

1

 

 

 

 

 

 

 

 

 

1

Uniform (round-robin) scheduling.

 

 

 

 

 

 

 

2:1

break_burst

00

Break all defined length bursts (the CPU does not create

10

 

 

 

 

defined bursts).

 

 

 

 

 

 

 

 

 

 

01

Break all defined length bursts greater than four-beat.

 

 

 

 

 

 

 

 

 

 

10

Break all defined length bursts greater than eight-beat.

 

 

 

 

 

 

 

 

 

 

11

Never break defined length bursts.

 

 

 

 

 

 

 

3

quantum_type

0

A quantum is an AHB clock.

0

 

 

 

 

 

 

 

 

 

1

A quantum is an AHB bus cycle.

 

 

 

 

 

 

 

7:4

quantum_size

 

Controls the type of arbitration and the number of quanta

0100

 

 

 

 

before re-arbiration occurs.

 

 

 

 

 

 

 

 

 

 

0000

Preemptive, re-arbitrate after 1 AHB quantum.

 

 

 

 

 

 

 

 

 

 

0001

Preemptive, re-arbitrate after 2 AHB quanta.

 

 

 

 

 

 

 

 

 

 

0010

Preemptive, re-arbitrate after 4 AHB quanta.

 

 

 

 

 

 

 

 

 

 

0011

Preemptive, re-arbitrate after 8 AHB quanta.

 

 

 

 

 

 

 

 

 

 

0100

Preemptive, re-arbitrate after 16 AHB quanta.

 

 

 

 

 

 

 

 

 

 

0101

Preemptive, re-arbitrate after 32 AHB quanta.

 

 

 

 

 

 

 

 

 

 

0110

Preemptive, re-arbitrate after 64 AHB quanta.

 

 

 

 

 

 

 

 

 

 

0111

Preemptive, re-arbitrate after 128 AHB quanta.

 

 

 

 

 

 

 

 

 

 

1000

Preemptive, re-arbitrate after 256 AHB quanta.

 

 

 

 

 

 

 

 

 

 

1001

Preemptive, re-arbitrate after 512 AHB quanta.

 

 

 

 

 

 

 

 

 

 

1010

Preemptive, re-arbitrate after 1024 AHB quanta.

 

 

 

 

 

 

 

 

 

 

1011

Preemptive, re-arbitrate after 2048 AHB quanta.

 

 

 

 

 

 

 

 

 

 

1100

Preemptive, re-arbitrate after 4096 AHB quanta.

 

 

 

 

 

 

 

 

 

 

1101

Preemptive, re-arbitrate after 8192 AHB quanta.

 

 

 

 

 

 

 

 

 

 

1110

Preemptive, re-arbitrate after 16384 AHB quanta.

 

 

 

 

 

 

 

 

 

 

1111

Nonpreemptive, infinite AHB quanta.

 

 

 

 

 

 

 

 

10:8

default_master

nnn[1]

Master 1 (CPU) is the default master.

001

11

-

-

Reserved.

-

 

 

 

 

 

 

 

14:12

EP1

nnn[1]

External priority for master 1 (CPU).

000

15

-

-

Reserved.

-

 

 

 

 

 

 

 

18:16

EP2

nnn[1]

External priority for master 2 (GPDMA).

000

19

-

-

Reserved.

-

 

 

 

 

 

 

 

22:20

EP3

nnn[1]

External priority for master 3 (AHB1).

000

23

-

-

Reserved.

-

 

 

 

 

 

 

 

26:24

EP4

nnn[1]

External priority for master 4 (USB).

000

27

-

--

Reserved.

-

 

 

 

 

 

 

 

30:28

EP5

nnn[1]

External priority for master 5 (LCD).

000

31

-

-

Reserved.

-

 

 

 

 

 

 

[1]Allowed values for nnn are: 101 (highest priority), 100, 011, 010, 001 (lowest priority).

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Chapter 3: LPC24XX System control

3.3.1.1Examples of AHB1 settings

The following examples use the LPC2478 to illustrate how to select the priority of each AHB1 master based on different system requirements.

Table 31. Priority sequence (bit 0 = 0): LCD, CPU, GPDMA, AHB1, USB

Bit

Symbol

Description

Priority value nnn

Priority sequence

14:12

EP1

CPU

100 (4)

2

 

 

 

 

 

18:16

EP2

GPDMA

011 (3)

3

 

 

 

 

 

22:20

EP3

AHB1

010 (2)

4

 

 

 

 

 

26:24

EP4

USB

001 (1)

5

 

 

 

 

 

30:28

EP5

LCD

101 (5)

1

 

 

 

 

 

Table 32. Priority sequence (bit 0 = 0): USB, AHB1, CPU, GPDMA, LCD

Bit

Symbol

Description

Priority value nnn

Priority sequence

14:12

EP1

CPU

011 (3)

3

 

 

 

 

 

18:16

EP2

GPDMA

010 (2)

4

 

 

 

 

 

22:20

EP3

AHB1

100 (4)

2

 

 

 

 

 

26:24

EP4

USB

101 (5)

1

 

 

 

 

 

30:28

EP5

LCD

001 (1)

5

 

 

 

 

 

Table 33. Priority sequence (bit 0 = 0): GPDMA, AHB1, CPU, LCD, USB

Bit

Symbol

Description

Priority value nnn

Priority sequence

14:12

EP1

CPU

011 (3)

3

 

 

 

 

 

18:16

EP2

GPDMA

100 (4)

1[1]

22:20

EP3

AHB1

100 (4)

2[1]

26:24

EP4

USB

001 (1)

5

 

 

 

 

 

30:28

EP5

LCD

010 (2)

4

 

 

 

 

 

[1]Sequence based on round-robin.

Table 34. Priority sequence (bit 0 = 0): USB, LCD, AHB1, CPU, GPDMA

Bit

Symbol

Description

Priority value nnn

Priority sequence

14:12

EP1

CPU

000

4[1]

18:16

EP2

GPDMA

000

5[1]

22:20

EP3

AHB1

011 (3)

1

 

 

 

 

 

26:24

EP4

USB

001 (1)

3

 

 

 

 

 

30:28

EP5

LCD

010 (2)

2

 

 

 

 

 

[1]Sequence based on round-robin.

3.3.2AHB Arbiter Configuration register 2 (AHBCFG2 - 0xE01F C18C)

By default, the AHB2 access is scheduled round-robin (bit 0 = 1). For round-robin scheduling, the default priority sequence will be Ethernet and CPU.

The AHB2 access priority can be configured as priority scheduling (bit 0 = 0) and priority of the each of the AHB2 bus masters can be set by writing the priority value (highest priority = 2, lowest priority = 1).

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Masters with the same priority value are scheduled on a round-robin basis.

Table 35. AHB Arbiter Configuration register 2 (AHBCFG2 - address 0xE01F C18C) bit description

Bit

Symbol

Value

Description

Reset

 

 

 

 

value

0

scheduler

0

Priority scheduling.

1

 

 

 

 

 

 

 

1

Uniform (round-robin) scheduling.

 

 

 

 

 

 

2:1

break_burst

00

Break all defined length bursts (the CPU does not create

10

 

 

 

defined bursts).

 

 

 

 

 

 

 

 

01

Break all defined length bursts greater than four-beat.

 

 

 

 

 

 

 

 

10

Break all defined length bursts greater than eight-beat.

 

 

 

 

 

 

 

 

11

Never break defined length bursts.

 

 

 

 

 

 

3

quantum_type

0

A quantum is an AHB clock.

0

 

 

 

 

 

 

 

1

A quantum is an AHB bus cycle.

 

 

 

 

 

 

7:4

quantum_size

 

Controls the type of arbitration and the number of quanta

0100

 

 

 

before re-arbiration occurs.

 

 

 

 

 

 

 

 

0000

Preemptive, re-arbitrate after 1 AHB quantum.

 

 

 

 

 

 

 

 

0001

Preemptive, re-arbitrate after 2 AHB quanta.

 

 

 

 

 

 

 

 

0010

Preemptive, re-arbitrate after 4 AHB quanta.

 

 

 

 

 

 

 

 

0011

Preemptive, re-arbitrate after 8 AHB quanta.

 

 

 

 

 

 

 

 

0100

Preemptive, re-arbitrate after 16 AHB quanta.

 

 

 

 

 

 

 

 

0101

Preemptive, re-arbitrate after 32 AHB quanta.

 

 

 

 

 

 

 

 

0110

Preemptive, re-arbitrate after 64 AHB quanta.

 

 

 

 

 

 

 

 

0111

Preemptive, re-arbitrate after 128 AHB quanta.

 

 

 

 

 

 

 

 

1000

Preemptive, re-arbitrate after 256 AHB quanta.

 

 

 

 

 

 

 

 

1001

Preemptive, re-arbitrate after 512 AHB quanta.

 

 

 

 

 

 

 

 

1010

Preemptive, re-arbitrate after 1024 AHB quanta.

 

 

 

 

 

 

 

 

1011

Preemptive, re-arbitrate after 2048 AHB quanta.

 

 

 

 

 

 

 

 

1100

Preemptive, re-arbitrate after 4096 AHB quanta.

 

 

 

 

 

 

 

 

1101

Preemptive, re-arbitrate after 8192 AHB quanta.

 

 

 

 

 

 

 

 

1110

Preemptive, re-arbitrate after 16384 AHB quanta.

 

 

 

 

 

 

 

 

1111

Nonpreemptive, infinite AHB quanta.

 

 

 

 

 

 

9:8

default_master

nn

Master 2 (Ethernet) is the default master.

01

 

 

 

 

 

11:10

-

-

Reserved.

-

 

 

 

 

 

13:12

EP1

nn

External priority for master 1 (CPU).

00

 

 

 

 

 

15:14

-

-

Reserved.

-

 

 

 

 

 

17:16

EP2

nn

External priority for master 2 (Ethernet).

00

 

 

 

 

 

31:18

-

-

Reserved. User software should not write ones to

NA

 

 

 

reserved bits. The value read from a reserved bit is not

 

 

 

 

defined.

 

 

 

 

 

 

[1]Allowed values for nn are: 10 (high priority) and 01 (low priority).

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Chapter 3: LPC24XX System control

3.3.2.1Examples of AHB2 settings

Table 36. Priority sequence (bit 0 = 0): Ethernet, CPU

Bit

Symbol

Description

Priority value nn

Priority sequence

13:12

EP1

CPU

10 (2)

1

 

 

 

 

 

17:16

EP2

Ethernet

01 (1)

2

 

 

Table 37. Priority sequence (bit 0 = 0): Ethernet, CPU

 

 

 

 

 

 

Bit

Symbol

Description

Priority value nn

Priority sequence

13:12

EP1

CPU

00

2[1]

17:16

EP2

Ethernet

00

1[1]

[1]Sequence based on round-robin.

3.4Other system controls and status flags

Some aspects of controlling LPC2400 operation that do not fit into peripheral or other registers are grouped here.

3.4.1 System Controls and Status register (SCS - 0xE01F C1A0)

Table 38. System Controls and Status register (SCS - address 0xE01F C1A0) bit description

Bit

Symbol

Value

Description

Access

Reset

 

 

 

 

 

value

0

GPIOM

 

GPIO access mode selection.

R/W

0

 

 

 

 

 

 

 

 

0

GPIO ports 0 and 1 are accessed via APB addresses in a fashion

 

 

 

 

 

compatible with previous LPC2000 devices.

 

 

 

 

 

 

 

 

 

 

1

High speed GPIO is enabled on ports 0 and 1, accessed via addresses in

 

 

 

 

 

the on-chip memory range. This mode includes the port masking feature

 

 

 

 

 

described in the GPIO chapter.

 

 

1

EMC Reset

 

External Memory Controller Reset Disable.

R/W

0

 

Disable[1]

 

 

 

 

 

0

Both EMC resets are asserted when any type of reset event occurs. In this

 

 

 

 

 

 

 

 

 

mode, all registers and functions of the EMC are initialized upon any reset

 

 

 

 

 

condition.

 

 

 

 

 

 

 

 

 

 

1

Many portions of the EMC are only reset by a power-on or brown-out event,

 

 

 

 

 

in order to allow the EMC to retain its state through a warm reset (external

 

 

 

 

 

reset or watchdog reset). If the EMC is configured correctly, auto-refresh can

 

 

 

 

 

be maintained through a warm reset.

 

 

 

 

 

 

 

 

2

EMC Burst

 

External Memory Controller burst control (implemented on device revisions

R/W

0

 

Control

 

C and higher).

 

 

 

 

0

Burst enabled.

 

 

 

 

 

 

 

 

 

 

1

Burst disabled.

 

 

 

 

 

 

 

 

3

MCIPWR

 

MCIPWR pin control.

R/W

0

 

Active

 

 

 

 

 

0

The MCIPWR pin is low.

 

 

 

Level[1]

 

 

 

 

 

 

 

 

1

The MCIPWR pin is high.

 

 

 

 

 

 

 

 

 

 

 

 

4

OSCRANGE

 

Main oscillator range select.

R/W

0

 

 

 

 

 

 

 

 

0

The frequency range of the main oscillator is 1 MHz to 20 MHz.

 

 

 

 

 

 

 

 

 

 

1

The frequency range of the main oscillator is 15 MHz to 25 MHz.

 

 

UM10237_4

 

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Chapter 3: LPC24XX System control

Table 38. System Controls and Status register (SCS - address 0xE01F C1A0) bit description

 

 

 

 

 

 

 

 

 

 

Bit

Symbol

Value

Description

 

Access

Reset

 

 

 

 

 

 

value

5

OSCEN

 

Main oscillator enable.

 

R/W

0

 

 

 

 

 

 

 

 

 

0

The main oscillator is disabled.

 

 

 

 

 

 

 

 

 

 

 

 

1

The main oscillator is enabled, and will start up if the correct external

 

 

 

 

 

 

circuitry is connected to the XTAL1 and XTAL2 pins.

 

 

 

 

 

 

 

 

 

 

6

OSCSTAT

 

Main oscillator status.

 

RO

0

 

 

 

 

 

 

 

 

 

0

The main oscillator is not ready to be used as a clock source.

 

 

 

 

 

 

 

 

 

 

 

 

1

The main oscillator is ready to be used as a clock source. The main

 

 

 

 

 

 

oscillator must be enabled via the OSCEN bit.

 

 

 

31:7

-

-

Reserved. User software should not write ones to reserved bits. The value -

NA

 

 

 

read from a reserved bit is not defined.

 

 

 

 

 

 

 

 

 

 

[1]The state of this bit is preserved through a software reset, and only a POR or a BOD event will reset it to its default value.

4. Brown-out detection

The LPC2400 includes 2-stage monitoring of the voltage on the VDD(DCDC)(3V3) pins. If this voltage falls below 2.95 V, the Brown-Out Detector (BOD) asserts an interrupt signal to

the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC (see Section 7–3.4 “Interrupt Enable Register (VICIntEnable - 0xFFFF F010)”) in order to cause a CPU interrupt; if not, software can monitor the signal by reading the Raw Interrupt Status Register (see Section 7–3.3 “Raw Interrupt Status Register (VICRawIntr - 0xFFFF F008)”).

The second stage of low-voltage detection asserts Reset to inactivate the LPC2400 when

the voltage on the VDD(DCDC)(3V3) pins falls below 2.65 V. This Reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become

unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the Power-On Reset circuitry maintains the overall Reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition.

But when Brown-Out Detection is enabled to bring the LPC2400 out of Power-Down mode (which is itself not a guaranteed operation -- see Section 4–3.4.7 “Power Mode Control register (PCON - 0xE01F C0C0)”), the supply voltage may recover from a transient before the Wakeup Timer has completed its delay. In this case, the net result of the transient BOD is that the part wakes up and continues operation after the instructions that set Power-Down Mode, without any interrupt occurring and with the BOD bit in the RSID being 0. Since all other wakeup conditions have latching flags (see Section 3–3.1.2 “External Interrupt flag register (EXTINT - 0xE01F C140)” and Section 26–6.2), a wakeup of this type, without any apparent cause, can be assumed to be a Brown-Out that has gone away.

UM10237_4

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User manual

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Chapter 3: LPC24XX System control

5. Code security vs. debugging

Applications in development typically need the debugging and tracing facilities in the LPC2400. Later in the life cycle of an application, it may be more important to protect the application code from observation by hostile or competitive eyes. The following feature of the LPC2400 allows an application to control whether it can be debugged or protected from observation.

Details on the way Code Read Protection works can be found in Section 30–8 “Code Read Protection (CRP)”.

Remark: CRP is not available for flashless LPC2400 parts.

UM10237_4

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User manual

Rev. 04 — 26 August 2009

40 of 792

UM10237

Chapter 4: LPC24XX Clocking and power control

Rev. 04 — 26 August 2009 User manual

1. Summary of clocking and power control functions

This section describes the generation of the various clocks needed by the LPC2400 and options of clock source selection, as well as power control and wakeup from reduced power modes. Functions described in the following subsections include:

Oscillators

Clock source selection

PLL

Clock dividers

APB divider

Power control

Wakeup timer

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User manual

Rev. 04 — 26 August 2009

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NXP Semiconductors

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Chapter 4: LPC24XX Clocking and power control

 

 

 

 

 

 

 

 

EXTERNAL

 

 

 

 

 

 

 

 

ETHERNET

 

 

 

 

 

 

 

 

PHY

 

 

 

 

 

 

USB

usbclk

 

 

 

 

 

 

 

(48 MHz)