PicoGate and MicroPak
The logical solution for miniaturization
The logical solution for miniaturization
NXP PicoGate and MicroPak™ packages are roughly ten to fifteen times
smaller than conventional SO14 packages and provide significant
miniaturization in space-constrained applications. Available in a wide
range of logic functions, they provide an equally wide range of choices
and deliver the right levels of performance.
Addressing today’s most critical
design issues:
• Miniaturization, for board-space
savings
• ASIC fixes and glue logic,
for faster time-to-market
• Simpler PCB routing,
for more cost-effective designs
• ASIC output drive,
for reduced ASIC chip size
• Voltage translation,
for 1.2-to-3.3-V interface
Offering the most popular functions
for a very wide range of applications:
• Laptops, notebooks, docking
stations, PC cards
• Mobile phones, PDAs, pagers
• Portable radios, portable CD
and MP3 players
• LCD TV and set-top box
• Cameras
• Disk memory drivers
• High-temperature (-40 to +125 °C)
automotive and military applications
Faster time-to-market, simpler layouts
These devices make it simple to implement last-minute changes yet
minimize the impact on board layouts. With an ASIC design, for example,
engineering teams can fine-tune performance without re-spinning silicon,
since it’s easy to add discrete logic functions like gates or inverters.
By simplifying routing and eliminating dependencies in intricate linelayout patterns, these devices improve the cost-effectiveness of crowded
layouts. Also, since configurable logic functions can replace up to four
devices, using PicoGate and MicroPak devices can reduce inventory, too.
Better selection, more choice
PicoGate and MicroPak devices include single-, dual-, and triple-gate
functions and are housed in 5-, 6-, and 8-pin packages, so you get just
the functions you need. To support the widest range of applications,
every product in the portfolio is specified for high-temperature operation
(-40 to +125 °C). And, since they perform the most popular functions
and either meet or exceed competitive specifications, they put an end to
single-source problems.
PicoGate and MicroPak2
0.95
mm
2.8 mm
8.1 mm2 area
2.9
mm
1.0
mm
SOT753
0.65
mm
2.1 mm
4.2 mm2 area
2.0
mm
1.0
mm
SOT363
0.65
mm
2.1 mm
4.2 mm2 area
2.0
mm
1.0
mm
SOT353
Package size comparisons (nominal values) and suffixes
0.95
mm
2.8 mm
8.1 mm2 area
2.9
mm
1.0
mm
SOT753
0.5 mm
3.1 mm
2.0
mm
1.0
mm
6.2 mm2 area
SOT765
0.65
mm
4.0 mm
12 mm2 area
3.0
mm
1.1
mm
SOT505-2
0.65
mm
2.1 mm
4.2 mm2 area
2.0
mm
1.0
mm
SOT363
0.65
mm
2.1 mm
4.2 mm2 area
2.0
mm
1.0
mm
SOT353
0.95
mm
2.8 mm
8.1 mm2 area
2.9
mm
1.0
mm
SOT457
0.35 mm
1.0 mm
1.0
mm
0.5
mm
0.95
mm
2.8 mm
8.1 mm2 area
2.9
mm
1.0
mm
SOT753
0.5 mm
3.1 mm
2.0
mm
1.0
mm
6.2 mm2 area
1.0 mm2 area SOT891
SOT765
0.65
mm
4.0 mm
12 mm2 area
3.0
mm
1.1
mm
SOT505-2
0.65
mm
2.1 mm
4.2 mm2 area
2.0
mm
1.0
mm
SOT363
0.65
mm
2.1 mm
4.2 mm2 area
2.0
mm
1.0
mm
SOT353
0.95
mm
2.8 mm
8.1 mm2 area
2.0 mm2 area SOT833
2.9
mm
1.0
mm
SOT457
0.5 mm
1.0 mm
2.0
mm
0.5
mm
0.55 mm
1.6
mm
0.5
mm
2.56 mm2 area SOT902
1.6 mm
0.5 mm
1.0 mm
1.5
mm
0.5
mm
1.5 mm2 area SOT886
GW
Package type:
Package type:
GW
Package type: GV Package type: DPPackage type: DC
Package type: GV
Package type:
GM
Drawings not to scale.
GM
Package type: GFPackage type: GTPackage type:
PicoGate and MicroPak 3
Function Description
1G00 Single t wo-input NAND gate 5 • • • • • • • • •
1G02
1G04 Single inverter 5 • • • • • • • • •
1G06 Single inverter (open-drain output) 5 • • • • • • •
1G07 Single inverter (open-drain output) 5 • • • • • • •
1G08 Single t wo-input AND gate 5 • • • • • • •
1G0832
1G125
1G126
1G132
1G11 Single three-input AND gate 5 • • • •
1G14 Single Schmit t-trigger inverter 5 • • • • • • • • •
1G175 D-type flip-flop with reset 6 • • • • • •
1G157 Single t wo-input multiplexer 6 • • • •
1G158 Single t wo-input multiplexer 6 • • • •
1G17 Single Schmit t-trigger buffer 6 • • •
1G18 Non-inverting demultiplexer 5 • • • • •
1G19 Decoder/demultiplexer 5 • • • • •
1G240
1G3157 Single 2-channel analog multiplexer/demultiplexer (SPDT switch) 5 • • •
1G32
1G3208
1G34 Single buffer 5 • • • • •
1G384 Single analog switch 6 • • •
1G386 Three-input Exclusive-OR gate 5 • • • • •
1G38 Single t wo-input NAND gate with open-drain outputs 5 • • •
1G66 Analog switch 5 • • • • • • •
1G53 Two-channel analog mux/demux 8 • • • •
1G57 Single low-power configurable multi-function gate 5 • • • •
1G58 Single low-power configurable multi-function gate 5 • • •
1G74 D-type flip-flop 8 • • • • • • •
1G79 D-type flip-flop, positive-edge trigger 8 • • • •
1G80 D-type flip-flop, positive-edge trigger 5 • • •
1G86 Single t wo-input Exclusive-OR gate 5 • • • • • • • •
1G97 Configurable multi-func tion gate 8 • • • • •
1G98 Configurable multi-func tion gate 8 • • • • •
1GU04 Single inverter (unbuffered) 5 • • • • • • • •
1GX04 3.3-V crystal driver 5 • • •
1T34 Dual supply translating buffer 5 • • • •
2G00
2G02
2G04 Dual inverter 6 • • • • • • • • •
2G06
2G07
2G08
2G125
2G126
2G14
2G17
2G240
2G241
2G32
2G34
2G38 Dual two-input NAND buffer, Ocs 8 • • • • • • • •
2G53
2G58
2G66
2G74
V2G66
2G86
2GU04
3G04 Triple inver ter 8 • • • • • • • •
3G06 Triple inver ter (open- drain output) 8 • • • • • • •
3G07 Triple buf fer (open-drain output) 8 • • • • • • •
3G14 Triple Schmitt-trigger inver ter 8 • • • • • • • •
3G17 Triple Schmitt-trigger buf fer 8 • • • • • • • •
3G34 Triple buf fer gate 8 • • • • • • • •
3GU04 Triple inver ter (unbuf fered) 8 • • • • • • •
Single-gate Technology Package options
Single t wo-input NOR gate 5 • • • • • • • • •
Three-input AND -OR gate 6 • • • •
Single 3-state buffer 5 • • • • • • • •
Single 3-state buffer 5 • • • • • • • •
Two-input NAND Schmit t-trigger 5 • • • •
Buffer/line driver (3-state) 5 • • • •
Single t wo-input OR gate 5 • • • • • • • • • •
Three-input OR-AND gate 6 • • •
Dual-gate Technology Package options
Dual two-input NOR gate 8 • • • • • • • •
Dual two-input NOR gate 8 • • • • • • • •
Dual inverter (open drain) 6 • • • • • • • •
Dual buffer (open drain) 6 • • • • • • • •
Dual two-input AND gate 8 • • • • • • • •
Dual 3-state buf fer 8 • • • • • • • •
Dual 3-state buf fer 8 • • • • • • • •
Dual Schmitt-trigger inverter 6 • • • • • • • • •
Dual Schmitt-trigger buffer 6 • • • • • • •
Dual buffer, inverter, 3-state 8 • • • • • • • •
Dual buffer, 3-state 8 • • • • • • • •
Dual two-input OR gate 8 • • • • • • • •
Dual buffer 6 • • • • • • • • •
Dual analog multiplexer/demultiplexer 8 • • • • •
Single low-power configurable multi-function gate 8 •
Dual bilateral analog switch 8 • • • • • • •
Single D -type flip-flop with ser/reset 8 • • • • •
Dual over-voltage-tolerant bilateral analog switch 8 • • •
Dual Exclusive-OR gate 8 • • • • • • • •
Dual inverter (unbuffered) 6 • • • • • • •
Triple-gate Technology Package options
Pins
HC/T
AHC/ T
LVC
AUC
AUP
SOT353
SOT753
SOT363
SOT457
SOT505-2
SOT765
SOT886
SOT833
SOT902
SOT891
1G125 74CBTLV1G125 single-bus switch • • •
PicoGate and MicroPak4
Technology Package options
The NXP portfolio of PicoGate and MicroPak logic
74LVC74A 74LVC00A
Before PicoGate/MicroPak logic
LEGACY ASIC
NEEDS 1/2
CLOCK
FREQ AND
INVERTED AND
CLOCKED DATA
Latched
data in
CK
NEEDS
LATCHED
DATA
ASIC
CLOCK SOURCE
DATA SOURCE
˜ ˜
˜ ˜
With PicoGate/MicroPak logic
LEGACY ASIC
NEEDS 1/2
CLOCK
FREQ AND
INVERTED AND
CLOCKED DATA
74LVC1G79
Latched
data in
CK
NEEDS
LATCHED
DATA
ASIC
CLOCK SOURCE
DATA SOURCE
PicoGate and MicroPak logic devices are available in our HC/T, AHC/T, LVC, AUC, and AUP families
HC/T family Cost-effective functions optimized for 5-V operating conditions
AHC/T family Single-, dual-, and triple-gate functions that deliver low noise and low power in the 2- to 6-V supply range
LVC family 5-V-tolerant functions that achieve performance similar to an equivalent 3.3-V LVC gate and provide low voltage, low noise,
and low power in the 1.2- to 5.5-V range
AUC family Functions that deliver low operating voltage (VCC down to 0.8 V), propagation delays of less than 2.0 ns TPD, and I
power-down
AUP family 1.1- to 3.6-V functions that offer power-down consumption rates that are 30% lower than competing logic families
Simplified routing and less board space
OFF
PicoGate and MicroPak 5
Rf
R1
C1
X1
C2
74LVC1GU04
R
NE5534A
Low-noise op amp
74LVC1G66
Bilateral
switch
1/2R
R
LVC1G14
D Q
CP
1G00
CP
Reset
Local
reset
D Q
CP
CP
1/2 CK
LVC1G14
3.3 V
10 k Ω
LOW DRIVE
ASIC SIGNAL
74LVC1G07
74LVC1G57 74LVC1G58
74LVC1G97 74LVC1G98
Sample applications of PicoGate/MicroPak logic
Crystal oscillator using a U04 Gain control using an analog switch Simple RC oscillator using a Schmitt-trigger
1G14
Asynchronous enable with synchronous.
Removal recommended for high-speed logic
designs
Common PicoGate/MicroPak logic
applications include increased drive
capability, voltage-level shifting, and signal
shaping
1G79 and 1G04 inverter form clock divider Switch debounce using a Schmitt-trigger
1G14
Multi-function configurable gates Multi-function configurable gatesLED driver
Product naming convention
1G Single
2G Dual
3G Triple
74 XXX XG XXX XX
HC High-speed
HCT High-speed TTL-compatible
AHC Advanced high-speed
AHCT Advanced high-speed TTL-compatible
LVC Low-voltage CMOS
AUC Advanced ultra-low-voltage CMOS
AUP Advanced ultra-low-power CMOS
CBTLV Cross BAR technology low-voltage
Function
PicoGate and MicroPak6
GW SOT353 5-lead
GW SOT363 6-lead
GV SOT753 5-lead
GV SOT457 6-lead
DC SOT765 8-lead
DP SOT505-2 8-lead
GM SOT886 6-lead
GM SOT902 8-lead
GT SOT833 8-lead
GF SOT891 6-lead
Competitive cross-reference: family
Direction of feed
P
in 1
Direction of feed
Pin 1
Family Device
type
HC(T) series Single-gate 74HC(T)1Gxxx NC7S(T )xxx MC74HC1Gxx x TC7Sxx x
Dual-gate 74HC(T)2Gxxx
Triple-gate 74HC(T)3Gx xx
AHC(T) series Single-gate 74AHC(T )1Gxxx SN74AHC(T)1Gxxx MC74VHC1Gxxx TC7S(H/ET)xxx 74V1G/Txxx
Dual-gate 74AHC(T)2Gx xx TC7WHxxx 74V2G/Txxx
Triple-gate 74AHC(T)3Gxx x TC7NHxx x 74V3G/Txxx
LVC series Single-gate 74LVC1Gxxx SN74LVC1Gxxx NC7SZxxx NL17SZxx x TC7SZxxx 74LX1G/Txxx
Dual-gate 74LVC2Gxxx SN74LVC2Gxxx NC7WZxxx NL27WZxxx TC7WZxxx
Triple-gate 74LVC3Gxxx SN74LVC3Gxx x NC7NZxxx NL37NZxxx TC7NZxx x
Translators 74LVC1Txxx SN74LVC1Txxx
AUC series Single-gate 74AUC1Gxxx SN74AUC1Gxxx NC7SVxxx TC7SLxx x
Dual-gate 74AUC2Gxxx SN74AUC2Gxxx NC7WVxxx
Triple-gate 74AUC3Gxxx SN74AUC3Gxxx NC7NVx xx
AUP series Single-gate 74AUP1Gxxx SN74AUP1Gxxx NC7SPxxx
Dual-gate 74AUP2Gxxx SN74AUP2Gxxx NC7WPxxx
Triple-gate 74AUP3Gxxx NC7NPxxx
Translators 74AUP1Txxx SN74AUP1Txxx
NXP Texas Instruments Fairchild
Semiconductor
ON
Semiconductor
Toshiba ST
Microelec tronics
74H1G66
TC74Wxxx
TC7Wxxx
Competitive cross-reference: packaging
Family Pin count NXP Pack method Texas
Instruments
SOT353 5 GW Reverse DCK P5 DFT FU CTR
SOT753 5 GV Reverse DBV M5 DTT F STR
SOT363 6 GW Reverse DCK P6 DFT FU
SOT457 6 GV Reverse DBV M6 DTT F
SOT765 8 DC Reverse DCU K8 US8 FK
SOT505-2
SOT886 6 GM Conventional &
8 DP Reverse DCT FU STR
YZP L6
reverse
SOT902
8 GM Reverse L8
SOT833 8 GT Conventional YZP
SOT891 6 GF Conventional
Fairchild
Semiconductor
ON
Semiconductor
Toshiba ST
Microelec tronics
MicroPak pack method
Conventional 12NC xx xx-xxxx-x118 Reverse 12NC xxxx-xx xx-x132
PicoGate and MicroPak 7
www.nxp.com
NXP Semiconductors is in t he process of being established as a separate legal entit y in
vario us countries worldwide. This process will be finalized in the co urse of 2006.
© 2006 Konink lijke Phil ips Electronics N.V.
All rights reserved. Reproduction in whole or in par t is p rohib ited without the prior written
conse nt of the copyright owner. The infor mation presented in this document does not form
part of any quotation or contract, is believed to be accur ate and re liable and may be changed
witho ut notice. No lia bilit y will be accepted by the publisher for any consequence of i ts u se.
Public ation thereof does not convey nor imply any license under patent or other ind ustrial or
intellectual proper ty rights .
Date of re lease: S eptember 20 06
Document order number: 9397 750 15677
Printed in the USA
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