NXP PH7030L Schematic [ru]

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.

1.2 Features and benefits

PH7030L

N-channel TrenchMOS logic level FET

Rev. 05 — 29 June 2009 Product data sheet

 Higher operating power due to low

thermal resistance

 Suitable for logic level gate drive

sources

 Low conduction losses due to low

on-state resistance

1.3 Applications

 DC-to-DC convertors
 Notebook computers

 Portable equipment
 Switched-mode power supplies

1.4 Quick reference data

Table 1. Quick reference

Symbol Parameter Conditions Min Typ Max Unit

V

DS

I

D

P

tot

Dynamic characteristics

Q

GD

Static characteristics

R

DSon

drain-source voltage Tj≥ 25 °C; Tj≤ 150 °C - - 30 V
drain current Tmb=25°C; VGS=10V;

see Figure 1

total power
dissipation

gate-drain charge VGS=5V; ID=20A;

drain-source
on-state resistance

Tmb= 25 °C; see Figure 2 - - 62.5 W

VDS=10V; Tj=25°C;
see Figure 11

VGS=10V; ID=10A;

= 25 °C; see Figure 9;

T

j

see Figure 10

; see Figure 3

--68A

-3.2-nC

-6.97.9mΩ

NXP Semiconductors

m

2. Pinning information

PH7030L

N-channel TrenchMOS logic level FET

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1S source
2S source
3S source

mb

D

G

4G gate

S

mb D mounting base; connected to

drain

1234

bb076

SOT669

(LFPAK)

3. Ordering information

Table 3. Ordering information

Type number Package

PH7030L LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669

Name Description Version

4. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

Avalanche ruggedness

E

DS(AL)S

drain-source voltage Tj≥ 25 °C; Tj≤ 150 °C - 30 V
gate-source voltage -20 20 V
drain current VGS=10V; Tmb=25°C; see Figure 1; see Figure 3 -68A

peak drain current tp≤ 10 µs; pulsed; Tmb=25°C; see Figure 3 -220A
total power dissipation Tmb=25°C; see Figure 2 -62.5W
storage temperature -55 150 °C
junction temperature -55 150 °C

source current Tmb=25°C - 52 A
peak source current tp≤ 10 µs; pulsed; Tmb=25°C - 150 A

non-repetitive
drain-source avalanche
energy

=10V; Tmb= 100 °C; see Figure 1 -43A

V

GS

VGS=10V; T
unclamped; t

=25°C; ID=33.9A; V

j(init)

=0.15ms

p

sup

≤ 30 V;

-115mJ

PH7030L_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 29 June 2009 2 of 12

NXP Semiconductors

PH7030L

N-channel TrenchMOS logic level FET

120

I

der

(%)

80

40

0

0 20015050 100

03aa23

Tmb (°C)

Fig 1. Normalized continuous drain current as a

function of mounting base temperature

3

10

I

D

(A)

10

2

Limit R

DSon

= VDS / I

D

120

P

der

(%)

80

40

0

0 20015050 100

03aa15

Tmb (°C)

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

003aaa385

tp = 10 μs

100 μs

10

1

10

DC

-1

-1

10

1 10 10

1 ms

10 ms

100 ms

VDS (V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

2

PH7030L_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 29 June 2009 3 of 12

NXP Semiconductors

5. Thermal characteristics

PH7030L

N-channel TrenchMOS logic level FET

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-mb)

thermal resistance from junction to

see Figure 4 --2K/W

mounting base

003aaa386

t

p

δ =

T

t

p

T

t

1

t

(s)

p

Z

th(j-mb )

(K/W)

10

1

10

10

δ = 0.5

0.2

0.1

0.05

-1

0.02

single pulse

-2

-5

10

-4

10

-3

10

-2

10

P

-1

10

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

PH7030L_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 29 June 2009 4 of 12