NXP PH5030AL Schematic [ru]
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing and consumer applications.
1.2 Features and benefits
PH5030AL
N-channel TrenchMOS logic level FET
Rev. 03 — 12 January 2010 Product data sheet
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Consumer applications
Desktop Voltage Regulator Module
(VRM)
Notebook Voltage Regulator Module
(VRM)
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
V
DS
I
D
P
tot
Dynamic characteristics
Q
GD
Q
G(tot)
Static characteristics
R
DSon
drain-source voltage Tj≥ 25 °C; Tj≤ 175 °C - - 30 V
drain current Tmb=25°C; VGS=10V;
see Figure 1
total power
dissipation
gate-drain charge VGS= 4.5 V; ID=10A;
total gate charge VGS= 4.5 V; ID=10A;
drain-source
on-state resistance
Tmb= 25 °C; see Figure 2 --61W
VDS= 12 V; see Figure 14
and 15
= 12 V; see Figure 14
V
DS
VGS=10V; ID=15A;
Tj=25°C
--91A
-3.8-nC
- 14.1 - nC
-3.635mΩ
NXP Semiconductors
m
2. Pinning information
PH5030AL
N-channel TrenchMOS logic level FET
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1S source
2S source
3S source
mb
D
G
4G gate
S
mb D mounting base; connected to
drain
1234
bb076
SOT669 (LFPAK)
3. Ordering information
Table 3. Ordering information
Type number Package
PH5030AL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
Name Description Version
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
Avalanche ruggedness
E
DS(AL)S
drain-source voltage Tj≥ 25 °C; Tj≤ 175 °C - 30 V
drain-gate voltage Tj≥ 25 °C; Tj≤ 175 °C; RGS=20kΩ -30V
gate-source voltage -20 20 V
drain current VGS=10V; Tmb= 100 °C; see Figure 1 -64A
peak drain current tp≤ 10 µs; pulsed; Tmb=25°C; see Figure 3 -336A
total power dissipation Tmb=25°C; see Figure 2 -61W
storage temperature -55 175 °C
junction temperature -55 175 °C
source current Tmb=25°C - 84 A
peak source current tp≤ 10 µs; pulsed; Tmb=25°C - 336 A
non-repetitive
drain-source avalanche
energy
=10V; Tmb=25°C; see Figure 1 -91A
V
GS
VGS=10V; T
=25°C; ID=84A; V
j(init)
sup
≤ 30 V;
-32mJ
RGS=50Ω; unclamped
PH5030AL_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 12 January 2010 2 of 14
NXP Semiconductors
PH5030AL
N-channel TrenchMOS logic level FET
100
I
D
(A)
80
60
40
20
0
0 50 100 150 200
003aac553
T
(°C)
mb
Fig 1. Continuous drain current as a function of
mounting base temperature
3
10
I
10
D
(A)
2
Limit R
DSon
= VDS / I
D
120
P
der
(%)
80
40
0
0 20015050 100
03aa16
Tmb (°C)
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aac588
10 μs
100 μs
10
1 ms
1
10
DC
-1
-1
10
1 10 10
10 ms
100 ms
VDS (V)
Fig 3. Safe operating area; continuous and peak drain cur rents as a function of drain-source voltage
2
PH5030AL_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 12 January 2010 3 of 14
NXP Semiconductors
5. Thermal characteristics
PH5030AL
N-channel TrenchMOS logic level FET
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-mb)
thermal resistance from junction to
see Figure 4 -1.392K/W
mounting base
10
Z
th(j-mb )
(K/W)
1
10
10
δ = 0.5
0.2
0.1
-1
0.05
0.02
single shot
-2
-6
10
-5
10
-4
10
-3
10
-2
10
P
-1
10
003aac558
t
p
δ =
T
t
p
T
t
t
(s)
p
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PH5030AL_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 12 January 2010 4 of 14
NXP Semiconductors
6. Characteristics
PH5030AL
N-channel TrenchMOS logic level FET
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V
(BR)DSS
V
GS(th)
drain-source
breakdown voltage
gate-source threshold
voltage
ID=20A; VGS=0V; Tj=25°C; tav = 100
35 - - V
ns
=250µA; VGS=0V; Tj=25°C 30 - - V
I
D
=250µA; VGS=0V; Tj=-55°C 27 - - V
I
D
ID=1mA; VDS = VGS; Tj=25°C;
see Figure 11
I
=1mA; VDS = VGS; Tj= 150 °C;
D
and 12
1.3 1.7 2.15 V
0.65 - - V
see Figure 12
=1mA; VDS = VGS; Tj=-55°C;
I
D
--2.45V
see Figure 12
I
DSS
I
GSS
R
DSon
drain leakage current VDS=30V; VGS=0V; Tj=25°C --1µA
=30V; VGS=0V; Tj= 150 °C - - 100 µA
V
DS
gate leakage current VGS=16V; VDS=0V; Tj= 25 °C - - 100 nA
=-16V; VDS=0V; Tj= 25 °C - - 100 nA
V
GS
drain-source on-state
resistance
VGS=4.5V; ID=15A; Tj= 25 °C - 5.08 6.7 mΩ
=10V; ID=15A; Tj= 150 °C;
V
GS
--8.7mΩ
see Figure 13
V
=10V; ID=15A; Tj= 25 °C - 3.63 5 mΩ
GS
R
G
gate resistance f = 1 MHz - 0.69 1.5 Ω
Dynamic characteristi cs
Q
G(tot)
total gate charge ID=10A; VDS=12V; VGS=4.5V;
- 14.1 - nC
see Figure 14
Q
Q
GS
GS(th)
=10A; VDS=12V; VGS=10V;
I
D
see Figure 14
I
=0A; VDS=0V; VGS=10V - 27 - nC
D
and 15
gate-source charge ID=10A; VDS=12V; VGS=4.5V;
pre-threshold
see Figure 14 and 15
-29-nC
-4.3-nC
-2.9-nC
gate-source charge
Q
GS(th-pl)
post-threshold
-1.4-nC
gate-source charge
Q
V
GD
GS(pl)
gate-drain charge - 3.8 - nC
gate-source plateau
VDS=12V; see Figure 14 and 15 -2.5-V
voltage
C
iss
C
oss
C
rss
input capacitance VDS=12V; VGS= 0 V; f = 1 MHz;
output capacitance - 373 - pF
Tj=25°C; see Figure 16
reverse transfer
- 1760 - pF
- 171 - pF
capacitance
t
d(on)
t
r
t
d(off)
t
f
PH5030AL_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 12 January 2010 5 of 14
turn-on delay time VDS=12V; RL=0.5Ω; VGS=4.5V;
R
=4.7Ω
rise time - 35 - ns
G(ext)
turn-off delay time - 29 - ns
fall time - 12 - ns
-19-ns
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