NXP PH5030AL Schematic [ru]

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing and consumer applications.

1.2 Features and benefits

PH5030AL

N-channel TrenchMOS logic level FET

Rev. 03 — 12 January 2010 Product data sheet

 High efficiency due to low switching

and conduction losses

 Suitable for logic level gate drive

sources

1.3 Applications

 Consumer applications  Desktop Voltage Regulator Module

(VRM)

 Notebook Voltage Regulator Module

(VRM)

1.4 Quick reference data

Table 1. Quick reference

Symbol Parameter Conditions Min Typ Max Unit

tot

Dynamic characteristics

G(tot)

Static characteristics

DSon

drain-source voltage Tj≥ 25 °C; Tj≤ 175 °C - - 30 V drain current Tmb=25°C; VGS=10V;

see Figure 1

total power dissipation

gate-drain charge VGS= 4.5 V; ID=10A;

total gate charge VGS= 4.5 V; ID=10A;

drain-source on-state resistance

Tmb= 25 °C; see Figure 2 --61W

VDS= 12 V; see Figure 14 and 15

= 12 V; see Figure 14

VGS=10V; ID=15A; Tj=25°C

--91A

-3.8-nC

- 14.1 - nC

-3.635mΩ

NXP Semiconductors

2. Pinning information

PH5030AL

N-channel TrenchMOS logic level FET

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1S source 2S source 3S source

4G gate

mb D mounting base; connected to

drain

1234

bb076

SOT669 (LFPAK)

3. Ordering information

Table 3. Ordering information

Type number Package

PH5030AL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669

Name Description Version

4. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

DGR

tot

stg

Source-drain diode

Avalanche ruggedness

DS(AL)S

drain-source voltage Tj≥ 25 °C; Tj≤ 175 °C - 30 V drain-gate voltage Tj≥ 25 °C; Tj≤ 175 °C; RGS=20kΩ -30V gate-source voltage -20 20 V drain current VGS=10V; Tmb= 100 °C; see Figure 1 -64A

peak drain current tp≤ 10 µs; pulsed; Tmb=25°C; see Figure 3 -336A total power dissipation Tmb=25°C; see Figure 2 -61W storage temperature -55 175 °C junction temperature -55 175 °C

source current Tmb=25°C - 84 A peak source current tp≤ 10 µs; pulsed; Tmb=25°C - 336 A

non-repetitive drain-source avalanche energy

=10V; Tmb=25°C; see Figure 1 -91A

VGS=10V; T

=25°C; ID=84A; V

j(init)

sup

≤ 30 V;

-32mJ

RGS=50Ω; unclamped

Product data sheet Rev. 03 — 12 January 2010 2 of 14

NXP Semiconductors

PH5030AL

N-channel TrenchMOS logic level FET

100

(A)

0 50 100 150 200

003aac553

(°C)

Fig 1. Continuous drain current as a function of

mounting base temperature

(A)

Limit R

DSon

= VDS / I

120

der

(%)

0 20015050 100

03aa16

Tmb (°C)

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

003aac588

10 μs

100 μs

1 ms

-1

1 10 10

10 ms 100 ms

VDS (V)

Fig 3. Safe operating area; continuous and peak drain cur rents as a function of drain-source voltage

Product data sheet Rev. 03 — 12 January 2010 3 of 14

NXP Semiconductors

5. Thermal characteristics

PH5030AL

N-channel TrenchMOS logic level FET

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

th(j-mb)

thermal resistance from junction to

see Figure 4 -1.392K/W

mounting base

th(j-mb )

(K/W)

δ = 0.5

0.2

0.1

-1

0.05

0.02

single shot

-2

-6

-5

-4

-3

-2

-1

003aac558

δ =

(s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

Product data sheet Rev. 03 — 12 January 2010 4 of 14

NXP Semiconductors

6. Characteristics

PH5030AL

N-channel TrenchMOS logic level FET

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

(BR)DSS

GS(th)

drain-source breakdown voltage

gate-source threshold voltage

ID=20A; VGS=0V; Tj=25°C; tav = 100

35 - - V

=250µA; VGS=0V; Tj=25°C 30 - - V

=250µA; VGS=0V; Tj=-55°C 27 - - V

ID=1mA; VDS = VGS; Tj=25°C; see Figure 11

=1mA; VDS = VGS; Tj= 150 °C;

and 12

1.3 1.7 2.15 V

0.65 - - V

see Figure 12

=1mA; VDS = VGS; Tj=-55°C;

--2.45V

see Figure 12

DSS

GSS

DSon

drain leakage current VDS=30V; VGS=0V; Tj=25°C --1µA

=30V; VGS=0V; Tj= 150 °C - - 100 µA

gate leakage current VGS=16V; VDS=0V; Tj= 25 °C - - 100 nA

=-16V; VDS=0V; Tj= 25 °C - - 100 nA

drain-source on-state resistance

VGS=4.5V; ID=15A; Tj= 25 °C - 5.08 6.7 mΩ

=10V; ID=15A; Tj= 150 °C;

--8.7mΩ

see Figure 13 V

=10V; ID=15A; Tj= 25 °C - 3.63 5 mΩ

gate resistance f = 1 MHz - 0.69 1.5 Ω

Dynamic characteristi cs

G(tot)

total gate charge ID=10A; VDS=12V; VGS=4.5V;

- 14.1 - nC

see Figure 14

Q Q

GS GS(th)

=10A; VDS=12V; VGS=10V;

see Figure 14 I

=0A; VDS=0V; VGS=10V - 27 - nC

and 15

gate-source charge ID=10A; VDS=12V; VGS=4.5V; pre-threshold

see Figure 14 and 15

-29-nC

-4.3-nC

-2.9-nC

gate-source charge

GS(th-pl)

post-threshold

-1.4-nC

gate-source charge Q V

GS(pl)

gate-drain charge - 3.8 - nC

gate-source plateau

VDS=12V; see Figure 14 and 15 -2.5-V

voltage C

iss

oss

rss

input capacitance VDS=12V; VGS= 0 V; f = 1 MHz;

output capacitance - 373 - pF

Tj=25°C; see Figure 16

reverse transfer

- 1760 - pF

- 171 - pF

capacitance t

d(on)

d(off)

Product data sheet Rev. 03 — 12 January 2010 5 of 14

turn-on delay time VDS=12V; RL=0.5Ω; VGS=4.5V;

=4.7Ω

rise time - 35 - ns

G(ext)

turn-off delay time - 29 - ns

fall time - 12 - ns

-19-ns

NXP Semiconductors

PH5030AL

N-channel TrenchMOS logic level FET

Table 6. Characteristics

…continued

Symbol Parameter Conditions Min Typ Max Unit

Source-drain diode

source-drain voltage IS=25A; VGS=0V; Tj=25°C;

- 0.84 1.2 V

see Figure 17

reverse recovery time IS=20A; dIS/dt = -100 A/µs; VGS=0V;

=20V

recovered charge - 21 - nC

[1] Tested to JEDEC standards where applicable.

120

(A)

100

4.5

0246810

VGS (V) = 3.2

003aac548

2.8

2.6

2.4

2.2

(V)

DSon

(mΩ)

VGS (V) = 3.2 V

0204060

-30-ns

003aac550

4.5

(A)

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

25 °C

003aac552

(V)

(A)

Tj = 150 °C

01234

Fig 7. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

Fig 6. Drain-source on-state resistance as a function

of drain current; typical values

(S)

010203040

003aac555

(A)

Fig 8. Forward transconductance as a function of

drain current; typical values

Product data sheet Rev. 03 — 12 January 2010 6 of 14

NXP Semiconductors

003aa c337

PH5030AL

N-channel TrenchMOS logic level FET

3000

iss

003aac556

(pF)

2000

rss

1000

0246810

(V)

Fig 9. Input and reverse transfer capacitances as a

function of gate-source voltage; typical values

(A)

-1

-2

-3

003aab271

maxtypmin

003aac549

DSon

(mΩ)

246810

(V)

Fig 10. Drain-source on-state resistance as a function

of gate-source voltage; typical values

GS(th)

(V)

max

typ

-4

min

-5

-6

0123

Fig 11. Su b-threshold drain current as a function of

(V)

Fig 12. G ate-source threshold voltage as a function of

gate-source voltage

-60 0 60 120 180 T

(°C)

junction temperature

Product data sheet Rev. 03 — 12 January 2010 7 of 14

NXP Semiconductors

003aaa508

PH5030AL

N-channel TrenchMOS logic level FET

03aa27

(°C)

1.5

0.5

−60 0 60 120 180

Fig 13. Normalized drain-source on-state resistance

factor as a function of junction temperature

003aac551

(V)

VDS = 12 (V)

VDS = 19 (V)

GS(pl)

GS(th)

GS1QGS2

G(tot)

Fig 14. Gate charge waveform definitions

2500

(pF)

2000

1500

iss

oss

003aac557

010203040

(nC)

Fig 15. G ate-source voltage as a function of gate

charge; typical values

1000

500

rss

-1

1 10 10

VDS (V)

Fig 16. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical values

Product data sheet Rev. 03 — 12 January 2010 8 of 14

NXP Semiconductors

PH5030AL

N-channel TrenchMOS logic level FET

(A)

Tj = 150 °C

0.0 0.2 0.4 0.6 0.8 1.0

003aac554

25 °C

(V)

Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values

Product data sheet Rev. 03 — 12 January 2010 9 of 14

NXP Semiconductors

7. Package outline

PH5030AL

N-channel TrenchMOS logic level FET

lastic single-ended surface-mounted package (LFPAK); 4 leads

234

1/2 e

mounting

base

SOT66

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE

VERSION

0.15

1.20

0.00

1.01

SOT669 MO-235

1.10

0.95

bcA e

0.25 4.20 1.27 0.25 0.1

IEC JEDEC JEITA

0.50

0.35

4.41

3.62

2.2

2.0

0.9

0.25

0.7

0.19

REFERENCES

0.30

0.24

(1)

4.10

3.80

max

detail X

(1)

5.0

4.8

(1)

3.3

3.1

6.2

0.85

5.8

0.40

EUROPEAN

PROJECTION

1.3

0.8

1.3

0.8

(A )

ISSUE DATE

04-10-13 06-03-16

8° 0°

Fig 18. Package outline SOT669 (LFPAK)

Product data sheet Rev. 03 — 12 January 2010 10 of 14

NXP Semiconductors

8. Revision history

PH5030AL

N-channel TrenchMOS logic level FET

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PH5030AL_3 20100112 Product data sheet - PH5030AL_2 Modifications: PH5030AL_2 20090121 Product data sheet - PH5030AL_1 PH5030AL_1 20080909 Preliminary data sheet - -

• Various changes to content.

Product data sheet Rev. 03 — 12 January 2010 11 of 14

NXP Semiconductors

PH5030AL

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com

[1][2]

Product status

[3]

Definition

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full dat a sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied u pon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

9.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be lia ble for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonabl y be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred t o as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a def ault of t he Application and the product. NXP Semiconductors does not accept any liability in this respect.

Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteri stics sections of this document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is ope n for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

, unless otherwise

Product data sheet Rev. 03 — 12 January 2010 12 of 14

NXP Semiconductors

PH5030AL

N-channel TrenchMOS logic level FET

Export control — This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior authorization from national authorities.

Non-automotive qualified products — Unless the data sheet of an NXP Semiconductors product expressly states that t he product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testin g o r ap plication requ iremen t s. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applicati ons. In the event that customer uses the product for design-in and use in automot ive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 03 — 12 January 2010 13 of 14

NXP Semiconductors

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13

10 Contact information. . . . . . . . . . . . . . . . . . . . . .13

PH5030AL

N-channel TrenchMOS logic level FET

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 January 2010

Document identifier: PH5030AL_3

NXP PH5030AL Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Product profile

1.1 General description

1.2 Features and benefits

1.3 Applications

1.4 Quick reference data

2. Pinning information

3. Ordering information

4. Limiting values

5. Thermal characteristics

6. Characteristics

7. Package outline

8. Revision history

9. Legal information

9.1 Data sheet status

9.2 Definitions

9.3 Disclaimers

9.4 Trademarks

10. Contact information

11. Contents