NXP PEMD12, PUMD12 Schematic [ru]

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

Rev. 4 — 21 November 2011 Product data sheet

1. Product profile

1.1 General description

NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted Device (SMD) plastic packages.

Table 1. Product overview

Type number Package PNP/PNP

PEMD12 SOT666 - PEMB2 PEMH2 ultra small and flat

PUMD12 SOT363 SC-88 PUMB2 PUMH2 very small

NXP JEITA

complement

NPN/NPN complement

Package configuration

lead

1.2 Features and benefits

 100 mA output current capability  Reduces component count  Built-in bias resistors  Reduces pick and place costs  Simplifies circuit design  AEC-Q101 qualified

1.3 Applications

 Low current peripheral driver  Control of IC inputs  Replaces general-purpose transistors in digital applications

1.4 Quick reference data

Table 2. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

CEO

R1 bias resistor 1 (input) 33 47 61 k R2/R1 bias resistor ratio 0.8 1 1.2

collector-emitter voltage open base - - 50 V output current - - 100 mA

NXP Semiconductors

001aab555

6 45

1 32

65 4

TR1

TR2

R2 R1

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2. Pinning information

Table 3. Pinning

Pin Description Simplified outline Graphic symbol

1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 output (collector) TR1

3. Ordering information

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

4. Marking

Table 4. Ordering information

Type number Package

Name Description Version

PEMD12 - plastic surface-mounted package; 6 leads SOT666 PUMD12 SC-88 plastic surface-mounted package; 6 leads SOT363

Table 5. Marking codes

Type number Marking code

[1]

PEMD12 D2 PUMD12 D*1

[1] * = placeholder for manufacturing site code

Product data sheet Rev. 4 — 21 November 2011 2 of 16

NXP Semiconductors

5. Limiting values

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

CBO

CEO

EBO

tot

Per device

tot

amb

stg

[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard

footprint.

[2] Reflow soldering is the only recommended soldering method.

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

collector-base voltage open emitter - 50 V collector-emitter voltage open base - 50 V emitter-base voltage open collector - 10 V input voltage TR1

positive - +40 V negative - 10 V

input voltage TR2

positive - +10 V

negative - 40 V output current - 100 mA peak collector current single pulse;

 1ms

total power dissipation T

amb

 25 C PEMD12 (SOT666) PUMD12 (SOT363)

total power dissipation T

amb

 25 C PEMD12 (SOT666) PUMD12 (SOT363)

junction temperature - 150 C ambient temperature 65 +150 C storage temperature 65 +150 C

-100mA

[1][2]

-200mW

[1]

-200mW

[1][2]

-300mW

[1]

-300mW

Product data sheet Rev. 4 — 21 November 2011 3 of 16

NXP Semiconductors

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

FR4 PCB, standard footprint

Fig 1. Per device: Power derating curve for SOT363 (SC-88) and SOT666

6. Thermal characteristics

Table 7. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Per transistor

th(j-a)

Per device

th(j-a)

thermal resistance from junction to ambient

PEMD12 (SOT666) PUMD12 (SOT363)

thermal resistance from junction to ambient

PEMD12 (SOT666) PUMD12 (SOT363)

400

tot

(mW)

300

200

100

-75 17512525 75-25

in free air

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(°C)

amb

[1][2]

[1]

[1][2]

[1]

- - 625 K/W

- - 417 K/W

[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method.

Product data sheet Rev. 4 — 21 November 2011 4 of 16

NXP Semiconductors

006aac750

-5

1010

-2

-4

-1

tp (s)

-3

th(j-a)

(K/W)

duty cycle = 1

0.75

0.5

0.33

0.2

0.1

0.05

0.02

0.01

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

006aac751

tp (s)

th(j-a)

(K/W)

duty cycle = 1

0.75

0.33

0.1

0.05

0.02

0.01

-5

0.5

0.2

-4

-3

-2

-1

1010

FR4 PCB, standard footprint

Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for

PEMD12 (SOT666); typical values

FR4 PCB, standard footprint

Fig 3. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for

PUMD12 (SOT363); typical values

Product data sheet Rev. 4 — 21 November 2011 5 of 16

NXP Semiconductors

7. Characteristics

Table 8. Characteristics

amb

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

CBO

CEO

EBO

CEsat

I(off)

I(on)

R1 bias resistor 1 (input) 33 47 61 k R2/R1 bias resistor ratio 0.8 1 1.2 C

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

=25C unless otherwise specified.

collector-base cut-off current

collector-emitter cut-off current

emitter-base cut-off current

DC current gain VCE=5V; IC=5mA 80 - collector-emitter

saturation voltage off-state input voltage VCE=5V; IC= 100 A- 1.20.8V on-state input voltage VCE=0.3V; IC=2mA 3 1.6 - V

collector capacitance VCB=10V;

TR1 (NPN) - - 2.5 pF TR2 (PNP) - - 3 pF

transition frequency VCE=5V; IC=10mA;

TR1 (NPN) - 230 - MHz TR2 (PNP) - 180 - MHz

VCB=50V; IE= 0 A - - 100 nA

VCE=30V; IB=0A --1A

=30V; IB=0A;

= 150 C

--5A

VEB=5V; IC=0A --90A

IC=10mA;

=0.5mA

--150mV

IE=ie=0A; f=1MHz

[1]

f=100MHz

[1] Characteristics of built-in transistor

Product data sheet Rev. 4 — 21 November 2011 6 of 16

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