NXP AN13215 Application Note

AN13215

Introduction to Boundary Scan of i.MX8/i.MX8X

Rev. 0 — 04/2021

by: NXP Semiconductors

Contents

1 Introduction

The i.MX 8/i.MX 8X families provide the boundary scan feature according to the
IEEE1149.1 specification via the JTAG controller.

The boundary scan is a method for checking the interconnections on PCBs and
internal IC sub-blocks. The mechanism is defined in the IEEE1149.1 standard.

2 Purpose

This application note shows how to use a Boundary Scan Description Language (BSDL) file associated with a Lauterbach
debugger to set all i.MX8 IOs into a known state through the boundary scan. When this is achieved, the proper IO state can be
checked using a multimeter to ensure there is no issue with the board.

This document focuses on entering the boundary scan mode for the board-level test. It provides the setup sequence and script
examples to ensure first-pass success.

1 Introduction......................................1

2 Purpose...........................................1

3 Overview......................................... 1

4 Software setup................................ 2

5 Hardware setup...............................3

6 Boundary scan using i.MX 8/i.MX 8

BSDL file and Lauterbach JTAG

debugger......................................... 6

7 Revision history.............................10

Application Note

The engineers should be familiar with the standard for the test access port and boundary scan architecture from the IEEE

1149.1 specification.

3 Overview

3.1 Boundary scan

The boundary scan technique allows the signals at component boundaries to be controlled and observed through the shift-register
stage associated with each pad. Each stage is a part of a larger boundary scan register cell, and cells for each pad are
interconnected serially to form a shift-register chain around the border of the design. This register can be used to read and write
port states.

In the normal mode, these cells are transparent and the core is connected to the ports. In the boundary scan mode, the core is
isolated from the ports and the port signals are controlled by the JTAG interface.

Figure 1 shows the JTAG controller block with the associated signals and exported registers. For more details, see the IEEE

1149.1 specification and the i.MX 8/i/MX 8X reference manuals.

NXP Semiconductors

Figure 1. JTAG (IEEE 1149.1) block diagram

Software setup

3.2 Test Access Port (TAP) JTAG

The TAP is a general-purpose port and it can provide access to many test support functions built into the component. The JTAG
controller uses the TAP to access registers and it can be shared with other TAP controllers on the MCU. It has four or five signals,
as described in Table 1.

Table 1. TAP JTAG

Signal name I/O type Description

TCK Input The test clock input provides the clock

for the test logic.

TMS Input The value of the signal present at the

TMS during a rising edge at the TCK
determines the next state of the TAP
controller.

TDI Input Serial test instructions and data are

received by the test logic.

TDO Output This serial output is used for test

instructions and data from the test logic.

TRST_N Input This is an optional active-low signal to

reset the TAP controller.

4 Software setup

The TRACE32 installation package is available on the Lauterbach webpage. Download the proper version of TRACE32 for
your host operating system and get support for the used target by navigating to the "Download" menu option and then into the
"TRACE32 Software" menu option.

Introduction to Boundary Scan of i.MX8/i.MX8X, Rev. 0, 04/2021

Application Note 2 / 11

NXP Semiconductors

Hardware setup

5 Hardware setup

The TRACE32 debugger hardware always consists of the following:

• Universal debugger hardware

• Debug cable specific to the processor architecture

To connect to the i.MX 8QM/i.MX 8QXP processor, LA3500 DEBUG USB 3.0 with LA-3743 cable with ARMv8 and ARMv7
licenses is used.

Figure 2 shows a generic JTAG setup using the Lauterbach probe.

Figure 2. JTAG Lauterbach setup diagram

The following is recommended:

• To prevent damage to the debuggers or target, do not plug or unplug the debugger while the target is powered on.

The recommended sequence for powering the debugger and target on or off is as follows:

• Power on: debugger > target

• Power off: target > debugger

— Make sure that the debugger connector orientation is correct when plugging it to the board to prevent damage to the

i.MX part.

For example, see how the Lauterbach probe is connected to the i.MX8QXP MEK board in Figure 3.

1. Connect the Lauterbach JTAG debugger to the EVK board through the 10-pin JTAG interface.

Introduction to Boundary Scan of i.MX8/i.MX8X, Rev. 0, 04/2021

Application Note 3 / 11

NXP Semiconductors

Hardware setup

2. Connect the Lauterbach JTAG debugger to the PC through the USB cable and then power on the debugger using a 5-V
power adapter.

3. Connect the MEK board to the power supply.

Figure 3. Lauterbach connected to i.MX8QXP MEK

5.1 Board setup for boundary scan

Each NXP SoC has the boundary scan conditions detailed in the hardware developer's guide document. The dedicated SoC BSDL
files describe the conditions to determine the SoC to enter the boundary scan mode.

For example, the i.MX8QXP BSDL file shows that the COMPLIANCE_PATTERNS needed for the boundary scan conditions are
as follows:

• Attribute COMPLIANCE_PATTERNS of MX8QXP: entity is "(TEST_MODE_SELECT, POR_B) (01)";

Under these conditions, the TEST_MODE signal must be set to low and the POR_B must be set to high. The boot selecting DIP
switches must be set to the "Serial Download Mode".

Introduction to Boundary Scan of i.MX8/i.MX8X, Rev. 0, 04/2021

Application Note 4 / 11