NXP AN13202 Application Note
AN13202
EMC Design Recommendation on i.MXRT Series
Rev. 0 — 03/2021
1 Introduction
Electromagnetic Compatibility (EMC) plays an important role in the
contemporary product performance, so it is the prime reliability problem for
electronic equipment. Bad design may cause huge problems, so EMC is
valued at the first stage of a design. This document introduces how to make
EMC design reasonable based on i.MXRT series and helps users to maintain
robustness of the EMC performance in their products.
2 Overview
2.1 Basic knowledge of EMC theory
Electromagnetic interference is one of the major problems in modern electronic
systems. Designers need to pay attention on it at the early stages of the design
to prevent schedule delay issues caused by EMC problem.
To achieve electromagnetic compatibility, enough EMC knowledge and good
practice in EMC implementation are needed in all design phases.
A simple EMI model consists of EMI source, coupling path and receptor, as
shown in Figure 1.
Application Note
Contents
1 Introduction......................................1
2 Overview......................................... 1
2.1 Basic knowledge of EMC theory
.....................................................1
2.2 Basic rules for EMC design..........2
3 Schematic design............................3
3.1 Crystal circuit............................... 3
3.2 Reset circuit................................. 3
3.3 Unused pins.................................4
3.4 Board-to-board interfaces............ 4
3.5 Communication interfaces........... 6
3.6 Sensitive signals impacted by
ground bounce.............................8
3.7 Power supply topology.................8
4 Layout design..................................9
4.1 Power supply routing and
grounding.....................................9
4.2 Placement..................................10
4.3 Bypass and decoupling..............11
4.4 DCDC circuit.............................. 11
4.5 Crystal oscillator circuit.............. 12
4.6 High speed signal...................... 12
4.7 Shield connection...................... 13
4.8 Isolation......................................14
4.9 Signal return path...................... 14
5 Software design............................ 15
5.1 Location of code running........... 15
5.2 Filter setting for some peripherals
...................................................15
5.3 IO drive strength........................ 16
5.4 Clock spread spectrum.............. 16
6 EMC test........................................18
6.1 Introduction................................ 18
6.2 EMC test results.........................19
7 Conclusion.....................................20
8 Reference......................................20
9 Revision history.............................20
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Overview
Figure 1. EMI elements
As shown in Figure 1, reducing noise from EMI source, altering coupling path and improving the immunity of the receptor can
eliminate the EMI issues in the system.
• Reducing noise from EMI source may include:
— Reducing loops area from the noise source
— Using of slower rising and falling edge repetition signal in noise source
— Reducing driving signal
— Adding filtering
— Shielding noise source circuitry
— Driving signal strength
— Filtering circuit
• Eliminating coupling path may include:
— Moving victim far away from the noise source
— Avoiding PCB traces coupling and power domains coupling between receptor and noise source
• Increasing immunity of victim may include:
— Reducing loops area from the PCB trace which is related to the victim
— Providing low impedance return path and reference power domains plane for signal traces related to the victim
2.2 Basic rules for EMC design
To better understand how to achieve the immunity (susceptibility) and emission requirements, some guidelines as below can help
designers to eliminate potential risks of redesigning system.
• There are different susceptibility requirements in electronic system but Radiated Immunity (RI) and Electrostatic Discharge
(ESD) test are basically same in modern electronic system.
• In RI test, the test system, EUT, will be exposed to high energy and very high frequency, so the circuit components,
in EUT, will be affected in some way. The basic design approach is to keep the sensitive component, microcontroller,
contamination out of the signal and power lines with predefined spectrum range (e.g. 10 - 900 MHz) .
• ESD generates short duration and high energy pluses (e.g. DC – 300 MHz) that will be introduced into EUT. It may cause
damage to some sensitive components in EUT. The basic design approach is to prevent sensitive circuit interfered by the
ESD high frequency components. Therefore, a system tends to provide high impedance with respect to chassis ground on
signal and power lines to eliminate the ESD current and energy input to the sensitive component.
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Schematic design
• For the emission, EUT provides assurance to a certain extent that it will not produce electromagnetic emissions to affect
other equipments. In general, many basic design techniques used in RI and ESD can be applied to solve emission issues.
The basic approach is to eliminate the high frequency interference voltage and current generation from EUT.
Some basic techniques, like component selection and PCB layout in
(document AN2321), can be applied to immunity and emission area mentioned above.
Designing for Board Level Electromagnetic Compatibility
3 Schematic design
The circuits listed below are more critical to affect EMC/EMI/ESD performance.
• Crystal circuit
• Reset circuit
• Unused pins disposition
• Interface of board to board
• Communication interface
• Power topology
This chapter introduces the detailed design aspects. It takes a concentrator board using i.MX RT1060 processor as an example
to introduce the design rules related to these aspects.
3.1 Crystal circuit
For i.MXRT series, an external 24 MHz crystal is required for the primary clock reference. The reference clocks with external clock
sources, such as active oscillators, are acceptable. An external oscillator has better ESD performance than a crystal. According
to our experiments, the performance of the systems using oscillator as a reference, compared to using crystal, improves about 2
KV ESD.
Using internal clock as reference clock can improve EMC performance, but for RT10XX series, internal clock doesn't support to
be PLL reference clock, and any other part that supports this feature will be taken as an EMC improvement.
3.2 Reset circuit
The chip has a System Reset Controller (SRC) managing the various reset signals. The external reset signal is routed to SRC via
a reset pin named POR_B.
A voltage supervisor IC is recommend to control POR_B. It provides reliable reset signal and monitors the power supply for low
voltage detection, which can help to avoid the potential EMC issue.
To avoid the noise Interference in poor EMC condition, place a RC circuit close to POR_B pins, which can decouple noise and
improve EMC performance.
Figure 2 shows one POR circuit as reference.
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Figure 2. Chip POR circuit
As the POR_B is driven by multiple sources, either of the below is required:
1. The output of the supervisor IC is open-drain output type.
2. An inverse diode connected into the supervisor IC’s output if it has a push-pull output.
POR_B is in SNVS power domain of the processor, so it needs to be pulled up to the power supply of SNVS.
Schematic design
3.3 Unused pins
Unused pins possibly impact EMC performance. They probably increase power consumption and the related GPIO status may
be changed under poor EMC conditions. For instance, a pin with High-Z impedance input, under poor EMC conditions, probably
frequently switches status, which increases the power consumption and causes other EMC issues.
Do not connect unused pins directly to GND, as the GPIO configuration registers may be changed under poor EMC conditions.
If the output is high in this case, big current will be generated and the pin may be damaged.
Generally, the datasheet provides the recommendations for unused pins connections. Follow the below rules:
• Refer to the datasheet to determine whether the unused pins are allowed to be floating or not.
• If a pin is allowed to be floating, configure it as GPIO and outputs 0 or 1.
• If a pin isn’t allowed to be floating, it is suggested to pull-down to GND with a resistor like 10 kΩ.
3.4 Board-to-board interfaces
Check signal loop for some signals being across board-to-board connection. Big signal/power loop possibly gets the poor EMC
performance and gets EMC issue. Figure 3 shows a bad example.
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Schematic design
Figure 3. Example of board to board connection
The system has two boards, the power board and the processor control board. The AC signal is from the power board to the
processor control board, so the signal loop with high impedance from VDDA through operational amplifier（U28）to AGND is so
long. It will couple more noise and input into the processor.
There are two solutions to shorten signal loops in the design shown in Figure 3.
1. Move PT1 to the processor control board, and input signal loop of amplifying is shortened a lot. The EMC performance
with Direct Contact Discharge is improved from from 4 KV to 8 KV.
2. Move the operational amplifier circuit to the power board and connect VDDA and AGND to the power board. It gets a
small loop among the ADC signal, VDDA, and AGND, to improve EMC performance.
For a processor IO directly connecting to a connector, introduce a TVS component as ESD protection. Another low-cost solution is
to add RC components as shown in Figure 4. For the R/C values, consider the IO operating frequency and set the RC time constant
far less than the signal period.
Figure 4. Example of IO interface
If there are high-speed signals or clock signals in board-to-board interface, it possibly gets EMI issue due to long signal loop and
big harmonic energy. To reduce the signal loop and harmonic energy, place the GND signals close to high-speed signals and
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Schematic design
reserve the serial resistor on board. If the signals support to change drive strength by software, lower drive strength to reduce
harmonic energy.
3.5 Communication interfaces
Regarding the communication interfaces, take below actions to improve the EMI and ESD performance.
• Connect TVS diodes for all signals from/to the connectors for transient voltage suppression.
• Connect a ferrite bead between power supplies of connectors and the power supplies of the board to isolate high
frequency noise.
• Connect a common mode choke between a pair of differential signals to remove high frequency common mode noise.
• Connect parallel RC or ferrite bead components between the connector’s metal shield and the board GND.
3.5.1 USB
Take below solutions to improve EMC performance.
• TVS arrays is recommended for ESD protection on VBUS, D+, D-, and ID.
• To improve EMI performance, connect the common mode choke to USB signal.
• Ferrite beads on power pin (VBUS,GND) are introduced to isolate high frequency noise.
• To improve ESD performance, take RC or Ferrite bead to isolate USB shield and board GND.
Figure 5 is an example circuit used in i.MXRT1060 concentrator board.
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Schematic design
Figure 5. USB circuit
3.5.2 Ethernet
For Ethernet design, a recommend design from EMC view as below:
• Use the TVS arrays for ESD protection on signals TXP, TXN, RXP, and RXN.
• Use the ferrite bead to isolate high frequency noise from the transformer.
• To improve ESD performance, use RC or Ferrite bead to isolate Ethernet shield and board GND.
Figure 6 is an example circuit used in i.MXRT1060 concentrator board.
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