NXP AN13148, I.MXRT1170 Application Note

AN13148

I.MXRT1170 Low-Power Modes

Rev. 0 — 03/2021

Contents

1 Introduction

This document describes the i.MX RT1170 power architecture design, clock
architecture, and how the low-power modes can be used and configured. i.MX
RT1170 introduces a completely new low-power architecture design when
compared to the previous i.MX RT10xx devices.

2 Clock and power architecture components

Centralized clock generation, power generation, and distribution are
implemented by the blocks listed in Table 1. All these blocks are interconnected into a functional unit which provides enhanced
possibilities of configuration and allows to implement the low power according to the application requirements. i.MX RT1170
introduces new power and clock architecture design, which is not backwards compatible with previous i.MX RT10xx family MCUs.

Table 1. Clock and power architecture components

IP module Description

1 Introduction......................................1

2 Clock and power architecture

components.....................................1

3 Low-power modes...........................2

4 Peripherals settings.........................6

5 Creating low-power mode

configuration..................................28

6 Setpoint and CPU mode transition

...................................................... 58

Application Note

Crystal OSC (XTALOSC) The XTALOSC controls the 24-MHz and 32-kHz oscillators. The 24-MHz

crystal oscillator is the primary clock source for all of the PLLs and clock
generation for the CPU and high-speed interfaces. The 32-kHz crystal
oscillator is the primary clock source for the RTC as well as the low-speed
clock source for CCM/SRC/GPC. See the Crystal Oscillator (XTALOSC)
chapter for details on the XTALOSC block.

Clock Control Module (CCM) The CCM module provides control for the clock generation, division,

distribution, synchronization, and coarse-level gating. The CCM contains
also the PLLs and PFDs block, the Clock Root blocks and the Low Peripheral
Clock Gating (LPCG) blocks. The PLLs and their associated PFDs generate
the clocks with various frequencies required to feed the CCM clock generator
that supplies the different functional blocks. The LPCG distributes the clocks
to all blocks in the SoC and handles the automated clock gating and the block
level software-controllable clock gating.

General Power Controller (GPC) The GPC module controls the power state of the whole chip. The GPC

handles the power gating under low-power modes and manages the power­up/power-down sequences.

Power Management Unit (PMU) The PMU module generates internal power supplies distributed to the entire

chip. It controls internal LDOs and body bias options.

Power Gating and Memory Controller (PGMC) The PGMC module controls the power gating of each power domain and the

power state of internal memories.

Table continues on the next page...

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Low-power modes

Table 1. Clock and power architecture components (continued)

IP module Description

DCDC Converter (DCDC) The DCDC is a synchronous buck-mode DC-DC converter with two outputs.

The DCDC is used to generate the power supply for the whole chip logic.

System Reset Controller (SRC) The SRC module generates the reset signals for all modules in the

entire chip. The SRC appropriately asserts the reset signals for the power
transitions, entry, and exit.

State Save and Restore Controller (SSARC) The SSARC saves the registers of functional modules in memory before

power down and restores the registers from memory after the module is
powered up.

3 Low-power modes

As mentioned in the previous chapter, i.MX RT1170 provides new power and clock architecture design. Compared to the previous
i.MX RT10xx family MCUs, the i.MX RT1170 power and clock state can be controlled by software, hardware, or combination of
both ways.

Each module can be controlled by software or hardware. For most of the modules, a combination of hardware and software control
is allowed (PGMC, SRC, CCM and PMU). The rest of the modules allows exclusive control by software or hardware (DCDC).
More details are provided later on in this document. See Table 2 for the control options summary. Figure 2 shows the entire
control interconnection.

Table 2. Hardware/Software control options overview

Module Module functionality

Enable/Disable √ √

RUN/Low Power mode √ √ √

DCDC

Analog output voltage √ √

Digital output voltage √ √

Power domain
enable/disable

PGMC

Memory low-

power level

SRC

Slice reset

enable/disable

Hardware control mode

CPU mode

control CM7

domain

√ √ √ √

√ √ √ √

√ √ √ √

CPU mode

control CM4

domain

Setpoint

mode control

Standby

mode control

Software

control mode

CCM

Clock sources (PLLs

and oscillators)

√ √ √ √ √

Table continues on the next page...

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Table 2. Hardware/Software control options overview (continued)

Low-power modes

Software

control mode

√

Module Module functionality

Clock roots

LPCGs √ √ √ √ √

Body bias √ √ √

PMU

Internal LDOs √ √ √

CPU mode

control CM7

domain

Hardware control mode

CPU mode

control CM4

domain

Setpoint

mode control

√ (not all of

them)

Standby

mode control

3.1 Software control mode

When the software control mode is selected for the appropriate module, the application code becomes responsible for the module
settings and module behavior. The application code must follow all the recommendations, such as the power-up and power-down
sequences, PLL enable sequences, and so on. When any changes of the clock or power settings are requested, the application
code must check if the planned change is valid and ensure that all the changes are executed in a correct order. Otherwise, the
chip behavior can be unpredictable or unstable. The software control is the default control mode of all modules.

3.2 Hardware control mode

When the hardware control mode is selected, the application code determines the hardware control mechanism used for each
resource. i.MX RT1170 allows to control the resources (modules) via the CPU mode control, Setpoint mode control, or Standby
mode control. The final power mode of the whole MCU is defined by the state of the CPUs (Run, Wait, Stop, or Suspend),
preconfigured setpoint (16 setpoints are available), and enabled or disabled Standby mode.

Figure 1. RT1170 power mode

The advantages of the hardware control mode are that the General Power Controller (GPC) takes responsibility for correct
power-up and power-down sequences, setpoints transition sequences, and so on. Even in the hardware control mode, incorrect
settings can be created, but the chip hardware can check most of the consequences and it does not allow the mode transition into
an invalid configuration.

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Low-power modes

3.2.1 CPU Mode Control (CMC)

i.MX RT1170 contains two CPU platforms: the Cortex-M7 CPU platform and the Cortex-M4 CPU platform. In case of a single-core
variant, only the Cortex-M7 CPU platform is available. Both CPU platforms support four CPU modes: Run, Wait, Stop, and
Suspend. When the CPU mode control is used for resource control, the resource state is determined by the CPU mode.

The CPU mode transition happens when one of the following events occurs:

• Sleep event: the CPU enters the sleep state with the WFI/WFE instruction

• Wakeup event: an unmasked IRQ wakeup

Both CPU platforms can be in the same CPU mode or in a different CPU mode at the same time. For example, the CM7 CPU
platform is in the Run mode, whereas the CM4 CPU platform is in the Stop mode at the same time. All the combinations are
allowed, but not all of them can be used in applications. Table 2 shows which resources (modules) can be controlled by the CPU
platforms. All the resources that allow the CPU mode control can be controlled by a CPU platform (private resource) or by both
CPU platforms together (shared resource). For more details, see section 14.3.4, Power modes in the Reference Manual.

3.2.2 Setpoint mode control (SPC)

i.MX RT1170 supports 16 setpoints. Setpoints are implemented to control the power state of public resources (resources
which are not owned and controlled by a CPU platform). Table 2 lists the resources that can be controlled by setpoints. For
more information about setpoint transitions triggers, see sections 19.3.2 Setpoint Control (SPC) and 19.3.3 System Setpoint
management in the Reference Manual.

3.2.3 Standby mode control (SBC)

The Standby mode control is a low-power mode that has distinguishing settings outside of the CPU mode control and Setpoint
mode control. The System Standby mode can be entered when the CPU enters the Wait, Stop, or Suspend mode and only when
both CPU platforms send a standby request. The Standby mode control is not supported by all modules. See Table 2 for the list
of the supported modules.

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Low-power modes

Figure 2. Resource control options

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Peripherals settings

Figure 3. Power architecture overview

4 Peripherals settings

4.1 DCDC settings

The DCDC converter is controlled via software by default. The default DCDC settings are in chapter 21, DCDC Converter in the
Reference Manual.

Table 3 shows all the DCDC features which can be controlled by hardware (Setpoint mode control and Standby mode control)

and which are related to low-power modes. To enable the hardware control mode, set CTRL0 [CONTROL_MODE] = 1. When
the hardware control is enabled, the DCDC parameters are set according to the selected setpoint and the System Standby mode
(enabled or disabled).

The Setpoint mode control and the Standby mode control settings are saved in the registers listed in Table 4. Table 4 also lists
the registers related to the software control mode.

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Peripherals settings

Table 3. DCDC general control settings

Functionality Setpoint mode control Standby mode control Software control mode

Enable DCDC output √ √

Enable DCDC_DIG output √ √

Low-power mode/high-power mode √ √ √

VDD 1.8 V Run mode √ √

VDD 1.0 V Run mode √ √

VDD 1.8 V Low power mode √ √ √

VDD 1.0 V Low power mode √ √ √

Table 4. DCDC control settings configuration registers

Hardware control mode Software control mode

CTRL0 [CONTROL_MODE] 1 0

Settings SPC setpoint control SBC standby control

Enable DCDC output REG4 [EANBLE_SP] CTRL0 [ENABLE]

Enable DCDC_DIG output REG5 [EANBLE_SP] CTRL0 [DIG_EN]

Low-power mode/Run mode REG6 [EANBLE_SP]

VDD 1.8 V Run mode target voltage

VDD 1.0 V Run mode target voltage

VDD 1.8 V Low power mode
target voltage

VDD 1.0 V Low power mode
target voltage

[ANA_STBY_TRG_SP_N]

[DIG_STBY_TRG_SP_N]

REG8-11

[ANA_TRG_SP_N]

REG12-15

[DIG_TRG_SP_N]

REG16-19

REG20-23

[STBY_LP_MODE_SP]

REG7P

CTRL0 [LP_MODE_EN]

CTRL1

[VDD1P8CTRL_TRG]

CTRL1

[VDD1P0CTRL_TRG]

CTRL1

[VDD1P8CTRL_STBY_TR

G]

CTRL1

[VDD1P0CTRL_STBY_TR

G]

4.2 Power Gating and Memory Controller (PGMC) settings

The PGMC consists of three submodules which control each power domain. These submodules are the Basic Power Controller
(BPC), CPU Power Controller (CPC), and PMIC Power Controller (PPC). Table 5 shows the general PGMC control options. See
the Reference Manual chapter 20 PGMC for more information about domain assignment.

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Table 5. PGMC general control settings

Peripherals settings

CPU mode

control CM7

domain

CPU mode

control CM4

domain

Setpoint mode

control

Standby mode

control

Software control mode

BPC0 - MEGAMIX √ √ √ √

BPC1 - DISPLAYMIX √ √ √ √

BPC2 - WAKEUPMIX √ √ √ √

BPC3 - LPRSMIX √ √ √ √

BPC4 - MIPIPHY √ √ √ √

CPC0 - CM7 core platform √ √ (MLPL only) √

CPC1 - CM4 core platform √ √ (MLPL only) √

PPC0 - PMIC control √ √ √

4.2.1 Basic Power Controller (BPC)

The BPC controls power domains using a simple isolation and power switch (MEGAMIX, DISPLAYMIX, WAKEUPMIX, LPSRMIX,
and MIPIPHY).

The BPC can turn on or shut down the power supply of the domain.

The BPC submodules use the BPC_MODE [CTRL_MODE] register to select which control settings are applied. Every BPC
instance can have different control settings. See Table 5 for the control options list.

If BPC_MODE [CTRL_MODE] = 0x1, thenthe
BPC_POWER_CTRL[PWR_OFF_AT_WAIT],BPC_POWER_CTRL[PWR_OFF_AT_STOP], and
BPC_POWER_CTRL[PWR_OFF_SUSPEND] fields determine the CPU mode in which the power domain is powered off.
The BPC_MODE [DOMAIN_ASSIGN] field selects which CPU mode control is used. Use Domain 0 to select the CM7 domain and
Domain 1 to select the CM4 domain.

If BPC_MODE[CTRL_MODE] = 0x2, then the BPC_POWER_CTRL[PWR_OFF_AT_SP] field determines the setpoints in which
the power domain is powered off.

Table 6. BPC control settings config registers

Software

control

CPU mode control Setpoint

mode control

BPC_MODE [CTRL_MODE] 0 1 2

CM7

domain

CM4

domain

BPC_MODE [DOMAIN_ASSIGN] 0 1

BPC_POWER_CTRL[PSW_ON_SOFT] √

BPC_POWER_CTRL[PSW_OFF_SOFT] √

Table continues on the next page...

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Table 6. BPC control settings config registers (continued)

Peripherals settings

Software

control

CPU mode control Setpoint

mode control

BPC_POWER_CTRL[PWR_OFF_AT_WAIT] √ √

BPC_POWER_CTRL[PWR_OFF_AT_STOP] √ √

BPC_POWER_CTRL[PWR_OFF_AT_SUSPEND] √ √

BPC_POWER_CTRL[PWR_OFF_AT_SP] √

The MEGAMIX and DISPLAYMIX power domains are connected to VDD_SOC_IN via a power switch and they can be power
gated separately, even if VDD_SOC_IN is enabled.

The WAKEUPMIX power domain is connected directly to VDD_SOC_IN and can be power gated only if VDD_SOC_IN is disabled
(DCDC_DIG is disabled).

The LPSRMIX is always on the power domain that can be power gated only if the SNVS low-power mode is used. The SNVS
low-power mode is not described in this document. Figure 3 shows the power architecture scheme.

4.2.2 CPU Power Controller (CPC)

The CPC controls the CPU platforms with complex power domain and sequence requirements (CM7 platform and CM4 platform).

The CPC submodules can turn on or shut down the power supply of the CM7 platform and CM4 platform and they allow to set the
cache and TCM memory power level independently of the entire platform. See SW M7-0, 1 and SW LPSR-0, 1 in Figure 3.

For the CM7 platform and CM4 platform control settings, the CPC_CORE_MODE [CTRL_MODE] register is used to select the
control settings to apply. Every CPC instance can use different core settings. See Table 7 for control options.

If CPC_CORE_MODE [CTRL_MODE] = 0x1, thenthe CPC_CORE_POWER_CTRL
[PWR_OFF_AT_WAIT],CPC_CORE_POWER_CTRL [PWR_OFF_AT_STOP], and

CPC_CORE_POWER_CTRL [PWR_OFF_SUSPEND] fields set the CPU mode in which the power domain is powered off.

Table 7. CPC platform control setting configuration registers

Software control mode CPU mode control

CPC Core Mode [CTRL_MODE] 0 1

CMC0 – CM7 core CMC1 – CM4 core

CPC_CORE_POWER_CTRL[PSW_ON_SOFT] √

CPC_CORE_POWER_CTRL[PSW_OFF_SOFT] √

CPC_CORE_POWER_CTRL[PWR_OFF_AT_W
AIT]

CPC_CORE_POWER_CTRL[PWR_OFF_AT_ST
OP]

CPC_CORE_POWER_CTRL[PWR_OFF_AT_S
USPEND]

√ √

√ √

√ √

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Peripherals settings

For the cache and TCM memories power level, the CPC_LMEM_MODE [CTRL_MODE] register is used to select which control
method is used. Each CPC instance can use different cache and TCM memory control settings. See Table 8 for the control
options list.

If CPC_LMEM_MODE [CTRL_MODE] = 0x1, then the CPC_LMEM_CM_CTRL [MLPL_AT_RUN],CPC_LMEM_CM_CTRL
[MLPL_AT_WAIT],CPC_LMEM_CM_CTRL [MLPL_AT_STOP], and

CPC_LMEM_CM_CTRL [MLPL_AT_SUSPEND] fields set which memory low-power level option is selected in which CPU mode.

If CPC_LMEM_MODE [CTRL_MODE] = 0x2, then CPC_LMEM_SP0 and CPC_LMEM_SP1 set the memory low-power level
option for the defined setpoint.

Table 8. CPC cache and TCM control setting configuration registers

Software

control mode

CPU mode control

Setpoint mode

control

CPC_LMEM_MODE [CTRL_MODE] 0 1 2

CMC0 - CM7 cache

and TCM

CMC1 - CM4 cache

and TCM

CPC_LMEM_CM_CTRL [MLPL_SOFT] √

CPC_LMEM_CM_CTRL [MLPL_AT_RUN] √ √

CPC_LMEM_CM_CTRL [MLPL_AT_WAIT] √ √

CPC_LMEM_CM_CTRL
[MLPL_AT_STOP]

CPC_LMEM_CM_CTRL
[MLPL_AT_SUSPEND]

√ √

√ √

CPC_LMEM_SP_CTRL_0 √

CPC_LMEM_SP_CTRL_1 √

NOTE
The cache memory for the CM4 core is always powered on and it is not possible to power off the memory via
MLPL settings.

NOTE
The power level of the cache memory and the TCM memory on the CM7 core cannot be controlled separately. The
CPC_LMEM_CM_CTRL or CPC_LMEM_SP_CTRL0/1 registers are used to control both memories together.

For detailed memory low-power level settings, see chapter 20.3.5 Memory Low Power Level in the Reference Manual.

4.2.3 PMIC Power Controller (PPC)

The PPC controls the PMIC standby mode outside of the chip. When the system is in the standby mode, the PPC can send
the PMIC_STBY_REQ to the external PMIC, thus enabling the PMIC to provide a standby voltage. See Table 9 for the PPC
control option.

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Peripherals settings

Table 9. PPC control settings config registers

Software control mode Setpoint mode control Standby mode control

Used when the System

PPC_MODE [CTRL_MODE] 0 2

Standby is enabled and

Setpoint mode control

is selected

PPC_STBY_CM_CTRL
[STBY_OFF_SOFT]

PPC_STBY_CM_CTRL
[STBY_ON_SOFT]

PPC_STBY_SP_CTRL
[STBY_ON_AT_SP_ACTIVE]

PPC_STBY_SP_CTRL
[STBY_ON_AT_SP_SLEEP]

√

√

√

√

4.3 Clock Control Module (CCM) settings

The CCM manages the on-chip module clocks. This module allows to set the control for the clock sources (OSCPLL), clock roots,
module clocks (LPCG), and clock groups. Table 10 shows general CCM control options. For detailed information about the CCM,
see the Reference Manual chapter 15 CCM. Detailed control options are discussed later on in this Application note.

Table 10. CCM general control settings

Clock sources

(OSCPLLs)

CPU mode control

CM7 domain

√ √ √ √ √

CPU mode control

CM4 domain

Setpoint

mode control

Standby mode

control

Software

control mode

Clock roots √ √

Module

clocks (LPCGs)

Clock groups √ √

√ √ √ √ √

4.3.1 Module clocks (LPCGs)

The module clocks (LPCGs) support four types of control: unassigned mode, domain mode, CPU low-power mode, and
setpoint mode.

These types are not directly distinguished into the hardware control mode and the software control mode, but the unassigned
mode is considered as software control mode and the CPU low-power mode and the setpoint mode are considered as hardware
control modes.

The domain control mode is not described in this document, because this mode is not directly related to low-power modes. For
more information about the domain control mode, see chapter 15.5.1.2, Domain mode in the Reference Manual. See Table 11 for
the LPCG control options.

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Table 11. LPCGs control settings config registers

Software control

mode

(unassigned

mode)

CPU mode control

Setpoint mode

control

Peripherals settings

Standby mode control

LPCG0_DIRECT ­LPCG137_DIRECT [ON]

LPCG0_AUTHEN ­LPCG137_AUTHEN [CPULPM]

LPCG0_AUTHEN ­LPCG137_AUTHEN
[WHITE_LIST]

LPCG0_DOMAIN ­LPCG137_DOMAIN [LEVEL]

LPCG0_DOMAIN ­LPCG137_DOMAIN [LEVEL0]

LPCG0_DOMAIN ­LPCG137_DOMAIN [LEVEL1]

LPCG0_AUTHEN ­LPCG137_AUTHEN
[SETPOINT_MODE]

x

CM7

domain

CM4 domain

Used when the system

standby is enabled

√ √

√ √

√ √

√

√

√

LPCG2_SETPOINT ­LPCG12_SETPOINT

√

[SETPOINT]

LPCG2_SETPOINT ­LPCG12_SETPOINT

√

[STANDBY]

LPCG14_SETPOINT ­LPCG19_SETPOINT

√

[SETPOINT]

LPCG14_SETPOINT ­LPCG19_SETPOINT

√

[STANDBY]

LPCG24_SETPOINT ­LPCG40_SETPOINT

√

[SETPOINT]

Table continues on the next page...

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Peripherals settings

Table 11. LPCGs control settings config registers (continued)

Software control

mode

(unassigned

CPU mode control

Setpoint mode

control

Standby mode control

mode)

LPCG24_SETPOINT ­LPCG40_SETPOINT

√

[STANDBY]

LPCG43_SETPOINT ­LPCG48_SETPOINT

√

[SETPOINT]

LPCG43_SETPOINT ­LPCG48_SETPOINT

√

[STANDBY]

4.3.1.1 Unassigned mode

This is the LPCG default mode. After reset, all module clocks are in the unassigned mode. In this mode, the LPCG0_DIRECT –
LPCG137_DIRECT [ON] fields are used for control, if the corresponding module clock is enabled or disabled.

4.3.1.2 CPU Low-Power Mode (CPULPM)

This mode controls the LPCG using the CM7 and CM4 platforms’ status. Before the CPULPM mode is selected, it is recommended
to set the LPCG0_DOMAIN - LPCG137_DOMAIN [LEVELn] fields. These fields determine if module clock is enabled or disabled
according to the CPU status.

The LPCG0_AUTHEN - LPCG137_AUTHEN [CPULPM] fields enable the CPU low-power mode for the appropriate module clock.
The LPCG0_AUTHEN - LPCG137_AUTHEN [WHITE_LIST] fields determine which domain is the owner of the module clock.
None, one, or more domains can be module clock owners. These two bitfields must be set in one step.

The LPCG0_DOMAIN - LPCG137_DOMAIN [LEVELn] fields and the LPCG0_AUTHEN - LPCG137_AUTHEN [WHITE_LIST]
fields determine whether the module clock is enabled or disabled.

If only one domain is the module clock owner, the appropriate LPCG0_DOMAIN - LPCG137_DOMAIN [LEVELn] fields are
used to determine if the corresponding module clock is enabled or disabled in the selected CPU mode. If the module clock is
shared between multiple domains, the LPCG0_DOMAIN - LPCG137_DOMAIN [LEVELn] fields of all domain owners are used
to determine whether the module clock is enabled or disabled. Table 12 shows three configuration examples. Bear in mind the
complexity and possibilities of many configuration options.

Table 12. Module clocks configuration examples

CM7 status

(DOMAIN0)

RUN RUN RUN STOP RUN STOP

LPCGn_AUTHEN

- [WHITE_LIST]

1 (own by CM7) 2 (own by CM4) 3 (own by CM7 and CM4)

CM4 status

(DOMAIN1)

CM7 status

(DOMAIN0)

CM4 status

(DOMAIN1)

CM7 status

(DOMAIN0)

CM4 status

(DOMAIN1)

LPCGn_DOMAIN ­[LEVEL0] DOMAIN0

1 (enable in RUN mode) 1 (enable in RUN mode) 1 (enable in RUN mode)

Table continues on the next page...

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Table 12. Module clocks configuration examples (continued)

LPCGn_DOMAIN ­[LEVEL1] DOMAIN1

1 (enable in RUN mode) 1 (enable in RUN mode) 0 (always disable)

clock settings

Peripherals settings

Resulting module n clock
enable/disable

Enable - Module clock is

owned by CM7 core which

is in RUN mode, so per

LEVEL0 configuration the clock

is enabled.

Disable - – Module clock is
owned by CM4 core which

is in STOP mode, so per

LEVEL1 configuration the

clock is disabled

Enable - Module clock is owned

by both cores. CM7 is in the

“highest” modes, so per LEVEL0

configuration the clock is enabled.

4.3.1.3 Setpoint mode

The setpoint mode controls the LPCG using the selected setpoint. Not all LPCGs support the setpoint mode control. The supported
LPCGs are LPCG2 – LPCG12, LPCG14 – LPCG19, LPCG24 – LPCG40, and LPCG43 – LPCG48.

The LPCG0_AUTHEN - LPCG137_AUTHEN [SETPOINT_MODE] fields enable the setpoint mode for the appropriate module
clock. The LPCG2_SETPOINT - LPCG48_SETPOINT [SETPOINT] fields determine in which setpoint is the module clock enabled
or disabled.

The module clocks that support the setpoint mode can be also controlled by the system standby when the setpoint mode is
selected. The LPCG2_SETPOINT - LPCG48_SETPOINT [STANDBY] fields determine whether the module clock is enabled or
disabled when the system enters the standby mode.

4.3.2 Clock sources (OSCPLLs)

The clock sources (OSCPLLs) support four types of control: unassigned mode, domain mode, CPU low-power mode, and
setpoint mode.

The OSCPLLs distinguish between the hardware control mode and the software control mode. These modes can be switched
using the CTRL registers listed in Table 13. When the software control mode is selected, the clock sources are controlled by the
CCM PLL registers and the XTALOSC registers. The settings in the OSCPLL_0 – OSCPLL_28 registers do not have any effect.

The domain mode control is not described in this application note, because this mode is not related to low-power modes. For more
information about the domain mode, see chapter 15.5.1.2 Domain mode in the Reference Manual. See Table 13 for the OSCPLL
control possibilities.

Table 13. OSCPLLs control settings config registers

Software

control

Hardware control mode

mode

ARM_PLL_CTRL
[ARM_PLL_CONTROL_MODE]

SYS_PLL1_CTRL
[SYS_PLL1_CONTROL_MODE]

Unassigned

mode

CPU mode control

0 1

0 1

Setpoint

mode

control

Standby

mode

control

Table continues on the next page...

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Table 13. OSCPLLs control settings config registers (continued)

Peripherals settings

SYS_PLL2_CTRL
[SYS_PLL2_CONTROL_MODE]

SYS_PLL3_CTRL
[SYS_PLL3_CONTROL_MODE]

PLL_AUDIO_CTRL
[PLL_AUDIO_CONTROL_MODE]

PLL_VIDEO_CTRL
[PLL_VIDEO_CONTROL_MODE]

OSC_400M_CTRL1
[RC_400M_CONTROL_MODE]

OSC_48M_CTRL
[RC_48M_CONTROL_MODE]

OSC_48M_CTRL
[RC_48M_DIV2_CONTROL_MODE]

OSC_16M_CTRL
[RC_16M_CONTROL_MODE]

OSC_24M_CTRL
[OSC_24M_CONTROL_MODE]

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

0 1

OSCPLL0_DIRECT ­OSCPLL28_DIRECT [ON]

OSCPLL0_AUTHEN ­OSCPLL28_AUTHEN [CPULPM]

OSCPLL0_AUTHEN ­OSCPLL28_AUTHEN [WHITE_LIST]

OSCPLL0_DOMAIN ­OSCPLL28_DOMAIN [LEVEL]

OSCPLL0_DOMAIN ­OSCPLL28_DOMAIN [LEVEL0]

OSCPLL0_DOMAIN ­OSCPLL28_DOMAIN [LEVEL1]

OSCPLL0_AUTHEN ­OSCPLL28_AUTHEN [SETPOINT_MODE]

√

domain

Table continues on the next page...

CM7

√ √

√ √

√ √

√

CM4

domain

√

√

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Table 13. OSCPLLs control settings config registers (continued)

Peripherals settings

OSCPLL0_SETPOINT ­OSCPLL28_SETPOINT [SETPOINT]

OSCPLL0_SETPOINT ­OSCPLL28_SETPOINT [STANDBY]

√

√

4.3.2.1 Unassigned mode

In this mode, the OSCPLL0_DIRECT - OSCPLL28_DIRECT [ON] fields are used to control whether the clock source is enabled
or disabled.

4.3.2.2 CPU Low-Power Mode (CPULPM)

This mode controls the OSCPLLs using the CM7 and CM4 platforms’ status. Before the CPULPM mode is selected, it is
recommended to set the OSCPLL0_DOMAIN – OSCPLL28_DOMAIN [LEVELn] fields. These fields determine whether the
module clock is enabled or disabled according to the CPU status.

The OSCPLL0_AUTHEN – OSCPLL28_AUTHEN [CPULPM] fields enable the CPULPM for the appropriate module clock. The
OSCPLL0_AUTHEN – OSCPLL28_AUTHEN [WHITE_LIST] fields determine which domain is the owner of the module clock.
None, one, or more domains can be the module clock owners. These two bits must be set in one step.

The OSCPLL0_DOMAIN – OSCPLL28_DOMAIN [LEVELn] fields and OSCPLL0_AUTHEN – OSCPLL28_AUTHEN
[WHITE_LIST] fields determine whether the module clock is enabled or disabled. These settings are the same as those
for the LPCG. See the previous chapter and Table 12 for more details.

4.3.2.3 Setpoint mode

This mode controls the OSCPLLs using the selected setpoint. The OSCPLL0_AUTHEN – OSCPLL28_AUTHEN
[SETPOINT_MODE] fields enable the setpoint mode for the appropriate module clock. The OSCPLL0_SETPOINT – OSCPLL28
[SETPOINT] fields determine in which setpoints the corresponding clock source is enabled or disabled.

The Clock sources that support the setpoint mode can be also controlled by the system standby when the setpoint mode is
selected. The OSCPLL0_SETPOINT – OSCPLL28 [STANDBY] fields determine whether the clock source is enabled or disabled
when the system enters the standby mode.

4.3.3 Clock roots

The clock roots support three types of control: unassigned mode, domain mode, and setpoint mode.

These types are not directly distinguished into the hardware control mode and the software control mode, but the unassigned
mode is the software control mode and the setpoint mode is the hardware control mode.

The domain mode control is not described in this application note, because this mode is not directly related to low-power modes.
For more information about the domain mode, see chapter 15.5.1.2 Domain mode in the Reference Manual. See Table 14 for the
clock roots control possibilities.

Table 14. Clock roots control settings config registers

CLOCK_ROOT0_CONTROL

- CLOCK_ROOT78_CONTROL

Software control mode

(unassigned mode)

√

Setpoint mode control

Table continues on the next page...

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Table 14. Clock roots control settings config registers (continued)

Peripherals settings

CLOCK_ROOT0_AUTHEN ­CLOCK_ROOT78_AUTHEN [SETPOINT_MODE]

CLOCK_ROOT0_SETPOINT0

- CLOCK_ROOT78_SETPOINT15

Software control mode

(unassigned mode)

Setpoint mode control

√

√

4.3.3.1 Unassigned mode

This is the clock roots default mode. After a reset, all clock roots are in the unassigned mode. In this mode, the
CLOCK_ROOT0_CONTROL - CLOCK_ROOT78_CONTROL registers are used to set up the clock roots settings (OFF,
MUX, DIV).

4.3.3.2 Setpoint mode

This mode controls the clock roots using the selected setpoint. Not all clock roots support the setpoint mode control. The
supported clock roots are CLOCK_ROOT0 – CLOCK_ROOT4, CLOCK_ROOT20 – CLOCK_ROOT21, and CLOCK_ROOT77
– CLOCK_ROOT78.

The CLOCK_ROOT0_AUTHEN - CLOCK_ROOT78_AUTHEN [SETPOINT_MODE] fields enable the setpoint mode for the
appropriate clock root. The CLOCK_ROOT0_SETPOINT0 -CLOCK_ROOT78_SETPOINT15 registers are used to set up the
clock root settings (GRADE, OFF, MUX, DIV).

4.3.4 Clock groups

The clock groups support three types of control: unassigned mode, domain mode, and setpoint mode.

These types are not directly distinguished into the hardware control mode and the software control mode, but the unassigned
mode is the software control and the setpoint mode is the hardware control.

The domain mode control is not described in this application note, because this mode is not related to low-power modes. For more
information about the domain mode, see chapter 15.5.1.2 Domain mode in the Reference Manual. See Table 15 for the clock
groups’ control possibilities.

Table 15. Clock groups control settings config registers

CLOCK_GROUP0_CONTROL

- CLOCK_GROUP1_CONTROL

CLOCK_GROUP0_AUTHEN ­CLOCK_GROUP1_AUTHEN [SETPOINT_MODE]

CLOCK_GROUP0_SETPOINT0

- CLOCK_GROUP1_SETPOINT15

4.3.4.1 Unassigned mode

Software control mode

(Unassigned mode)

√

Setpoint mode control

√

√

This is the default clock groups mode. After a reset, all clock groups are in the unassigned mode. In this mode, the
CLOCK_GROUP0_CONTROL - CLOCK_GROUP1_CONTROL registers are used to set up the clock groups’ settings (OFF,
RSTDIV, DIV0).

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Peripherals settings

4.3.4.2 Setpoint mode

The CLOCK_GROUP0_AUTHEN - CLOCK_GROUP1_AUTHEN [SETPOINT_MODE] fields enable the setpoint mode for the
appropriate clock group. The CLOCK_GROUP0_SETPOINT0 -CLOCK_GROUP1_SETPOINT15 registers are used to set up the
clock groups’ settings (GRADE, OFF, RSTDIV, DIV0).

4.4 PMU settings

The Power Management Unit (PMU) is comprised of the following components integrated for the power management. One DCDC
module generates the core power supply, the LDOs generate power for the internal logics, and multiple power switches create
sophisticated power mode management. Table 16 shows general PMU control possibilities. For a detailed schema of the power
architecture, see Figure 3. For more information about the PMU, see the Reference Manual chapter 17.

NOTE
The software mode supports flexible control, but pay attention to the analog dependencies and power structure
sequences. In the Hardware control mode, everything is handled precisely by hardware.

Table 16. PMU general control settings

Setpoint mode control Standby mode control

Software

control mode

PLL LDO √ √ √

LPSR ANA LDO √ √ √

LPSR DIG LDO √ √ √

BANDGAP √ √ √

BODY BIAS √ √ √

4.4.1 PLL LDO

The PLL LDO is used to power the system PLLs. The PMU_LDO_PLL [LDO_PLL_CONTROL_MODE] field is used to select the
control method that are applied. See Table 17 for the control options.

If PMU_LDO_PLL [LDO_PLL_CONTROL_MODE] = 0x0, then the

PMU_LDO_PLL [LDO_PLL_ENABLE] field is used to switch the LDO on or off manually.

If PMU_LDO_PLL [LDO_PLL_CONTROL_MODE] = 0x1, then the

LDO_PLL_ENABLE_SP [ON_OFF_SETPOINTn] and

PLL_LDO_STBY_EN_SP [STBY_EN_SETPOINTn] fields are used to select in which setpoint the LDO is enabled and whether the
LDO is enabled when the system enters the standby mode.

Table 17. PLL LDO control settings config registers

Software control mode Hardware control mode

Setpoint

mode control

Standby

mode control

PMU_LDO_PLL [LDO_PLL_CONTROL_MODE] 0 1

PMU_LDO_PLL [LDO_PLL_ENABLE] √

Table continues on the next page...

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