NXP AN13107 Application note

AN13107

PF series PMIC I2C-bus communication overview

Rev. 1 — 23 February 2021 Application note

Document information

Information Content

Keywords PF8100, PF8200, PF8101, PF8201, PF8121, PF5020, PF5023, PF5024,

PF7100, PF5200, safety power management integrated circuit (PMIC), I2C-bus

Abstract The current document provides a detailed overview on how to implement the

I2C-bus communication protocol for all the low voltage PMICs including PF81 series, PF82 series, PF502x, and PF71 series.

NXP Semiconductors

Revision history

Rev Date Description

1 20210223 initial version

AN13107

PF series PMIC I2C-bus communication overview

Application note Rev. 1 — 23 February 2021

2 / 20

NXP Semiconductors

1 Introduction

The I2C-bus is a de facto world standard that is now widely implemented on many types of integrated circuits. It is used to perform communication between one or more devices within a single communication bus. The power factor (PF) series of PMICs of NXP leverage the I2C-bus to allow control and configuration of the PMIC at system level.

This document provides a quick overview of the I2C-bus as well as detailed information of the specific features implemented around the I2C-bus in the PF series PMICs. It provides advanced functional safety coverage and robustness during system operation.

For more detail description of the NXP I2C-bus specification, refer to document UM10204 I2C-bus user manual.

2 I2C-bus overview

2.1 I2C-bus hardware considerations

The I2C-bus uses two lines to provide bidirectional communication: Clock (SCL) and data transfer (SDA). They are implemented as open-drain outputs with an input buffer on the same line, allowing the same bus to be used for bidirectional communication.

AN13107

PF series PMIC I2C-bus communication overview

Due to the open-drain architecture utilized on the bus lines, both the SDA and SCL lines require external pull-up resistors to provide a HIGH level when the bus is released. LOW level is generated via the internal low-side field effect transistor (FET) of the device controlling the bus at the time.

In the PF series, the selection of the pull-up resistors must consider the following:

• Operating bus speed

• Digital I/O voltage level

• Overall quiescent current allowed on the pullup

As a general approach, for system operating in Standard mode or Fast-mode Plus (Fm+) (F/S mode) up to 1 Mbit/s, 2.2 kΩ pull-up resistors is enough to provide robust communication with a minimum current leakage through the resistors. Likewise, for systems allowing high-speed operation up to 3.4 Mbit/s, 0.5 kΩ pull-up resistors are recommended to ensure faster and stronger drive during a LOW to HIGH transition.

The PF series PMICs provide I2C-bus communication compatible with 1.8 V or 3.3 V I/O voltage rails. The pull-up resistors must be connected to the V level.

selected at system

DDIO

Application note Rev. 1 — 23 February 2021

3 / 20

NXP Semiconductors

PF81

aaa- 0406 22

GND

FSOB

PGOOD

EWARN

PWRON

STANDBY

RESETB MCU

INTB

WDI

SYNCOUT

SYNCIN

AGND

DGND

EPAD

GND

V1P5A

V1P5D

VIN

TBBEN

VDDOTP

VDDIO

LICELL

C11 1 µF

C10

0.1 µFR2

2.2 kΩ

C15 1 µF

C14 1 µF

GND

SCL

SDA

XINTB

AMUX

VDDIO

SCL

SDA

AN13107

PF series PMIC I2C-bus communication overview

Figure 1. I2C-bus pull-up connection

2.2 General I2C-bus operation

The PF series PMICs operate as slave devices, therefore, they will not transmit data unless they have been addressed by the master. To allow a multi-PMIC architecture under the same I2C-bus, the PF devices provide a selectable I2C-bus slave address set via the one time programmable (OTP) configuration.

The OTP_I2C_ADD[2:0] is used to select the 7-bit I2C-bus address as shown in Table 1. The 8-bit address is calculated based on the read/write operation as follows:

8-bit slave address = (7-bit address ≪ 1) + R/W

Table 1. Voltage regulator summary

OTP_I2C_ADD[2:0] 7-bit I2C-bus address 8-bit write address 8-bit read address

During try before buy (TBB) operation, the 7-bit I2C-bus address is set to 08h. Therefore, on multi-PMIC systems it is recommended to select a different address for both devices to allow easier debug access during development phase.

Application note Rev. 1 — 23 February 2021

000 08h 10h 11h

001 09h 12h 13h

010 0Ah 14h 15h

011 0Bh 16h 17h

100 0Ch 18h 19h

101 0Dh 1Ah 1Bh

110 0Eh 1Ch 1Dh

111 0Fh 1Eh 1Fh

4 / 20

NXP Semiconductors

mba608

SDA

SCL

STOP condition

START condition

S or Sr Sr or P

SDA

SCL

MSB

1 2 7 8 9 1 2 3 to 8 9

ACK ACK

002aac861

START or

repeated START

condition

STOP or

repeated START

condition

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held LOW while interrupts are serviced

acknowledgement

signal from receiver

2.2.1 START and STOP conditions

All transactions begin with a START (S) condition and end with a STOP (P) condition.

• A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition.

• A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

Figure 2. START and STOP conditions

The master always generates the START and STOP conditions. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition.

AN13107

PF series PMIC I2C-bus communication overview

2.2.2 Repeated START condition

A repeated START (Sr) condition is similar to a START condition and is used in place of a back-to-back STOP then START condition. It looks identical to a START condition, but differs from a START condition because it happens before a STOP condition (when the bus is not idle). This operation is useful when the master wishes to start a new communication, but does not wish to let the bus go idle with the STOP condition, preventing the master from losing control of the bus to another master (in multi-master environments).

2.2.3 Byte format

Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. An acknowledge bit must follow each byte. Data is transferred with the most significant bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.

Figure 3. Data transfer on the I2C-bus

Application note Rev. 1 — 23 February 2021

5 / 20

NXP Semiconductors

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

2.2.4 Acknowledge (ACK) and not acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. The master generates all clock pulses, including the acknowledge ninth clock pulse.

The acknowledge signal is defined as follows: the transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse. Set-up and hold times must also be taken into account. Refer to document UM10204 for detailed timing description.

When SDA remains HIGH during this ninth clock pulse, it is defined as the not acknowledge signal. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. There are five conditions that lead to the generation of a NACK:

1. No receiver is present on the bus with the transmitted address so there is no device to

2. The receiver is unable to receive or transmit because it is performing some real-time

3. During the transfer, the receiver gets data or commands that it does not understand.

4. During the transfer, the receiver cannot receive any more data bytes.

5. A master-receiver must signal the end of the transfer to the slave transmitter.

AN13107

PF series PMIC I2C-bus communication overview

respond with an acknowledge.

function and is not ready to start communication with the master.

2.2.5 Data validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

Figure 4. Bit transfer on the I2C-bus

Application note Rev. 1 — 23 February 2021

6 / 20

+ 14 hidden pages