NXP 74LVC2G126DC, 74LVC2G126DP, 74LVC2G126GD, 74LVC2G126GF, 74LVC2G126GM Schematic [ru]

...

74LVC2G126

Dual bus buffer/line driver; 3-state

Rev. 12 — 8 April 2013 Product data sheet

1. General description

The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input (pin nOE). A LOW-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G126 as a translator in a mixed 3.3 Vand 5 V environment.

It is fully specified for partial power-down applications using I disables the output, preventing a damaging backflow current throu gh the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V  5 V tolerant input/output for interfacing with 5 V logic  High noise immunity  Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8-B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V  24 mA output drive (V  CMOS low power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V  Multiple package options  Specifie d from 40 Cto+85C and 40 C to +125 C

=3.0V)

OFF

. The I

circuitry

OFF

NXP Semiconductors

3. Ordering information

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 1. Ordering information

Type number Package

74LVC2G126DP 40 Cto+125C TSSOP8 plastic thin shrink small outline package; 8 leads;

74LVC2G126DC 40Cto+125C VSSOP8 plastic very thin shrink small outline package; 8 leads;

74LVC2G126GT 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;

74LVC2G126GF 40 C to +125 C XSON8 extremely thin small outline package; no leads;

74LVC2G126GD 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;

74LVC2G126GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads;

74LVC2G126GN 40 C to +125 C XSON8 extremely thin small outline package; no leads;

74LVC2G126GS 40 C to +125 C XSON8 extremely thin small outline package; no leads;

Temperature range Name Description Version

body width 3 mm; lead length 0.5 mm

body width 2.3 mm

8 terminals; body 1  1.95  0.5 mm

8 terminals; body 1.35  1  0.5 mm

8 terminals; body 3  2  0.5 mm

8 terminals; body 1.6  1.6  0.5 mm

8 terminals; body 1.2  1.0  0.35 mm

8 terminals; body 1.35  1.0  0.35 mm

4. Marking

SOT505-2

SOT765-1

SOT833-1

SOT1089

SOT996-2

SOT902-2

SOT1116

SOT1203

Table 2. Marking codes

Type number Marking code

74LVC2G126DP V26 74LVC2G126DC V26 74LVC2G126GT V26 74LVC2G126GF VN 74LVC2G126GD V26 74LVC2G126GM V26 74LVC2G126GN VN 74LVC2G126GS VN

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

[1]

Product data sheet Rev. 12 — 8 April 2013 2 of 22

NXP Semiconductors

001aah787

2OE

1OE

mna234

nOE

74LVC2G126

1OE V

1A 2OE 2Y 1Y

GND 2A

001aab740

1 2 3 4

6 5

8 7

74LVC2G126

2OE

1OE

GND

001aab741

Transparent top view

74LVC2G126

Dual bus buffer/line driver; 3-state

5. Functional diagram

Fig 1. Logic symbol Fig 2. Logic diagram (one gate)

6. Pinning information

6.1 Pinning

Fig 3. Pin configuration SOT505-2 and SOT765-1 Fig 4. Pin configuration SOT833-1, SOT1089,

Product data sheet Rev. 12 — 8 April 2013 3 of 22

SOT1116 and SOT1203

NXP Semiconductors

001aah949

74LVC2G126

Transparent top view

1OE

GND

2OE

001aaf056

1A1Y

1OE

2OE

GND

Transparent top view

terminal 1 index area

74LVC2G126

Dual bus buffer/line driver; 3-state

Fig 5. Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-2

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203

1OE, 2OE 1, 7 7, 1 output enable input (active HIGH) 1A, 2A 2, 5 6, 3 data input 1Y, 2Y 6, 3 2, 5 data output GND 4 4 ground (0 V) V

8 8 supply voltage

SOT902-2

7. Functional description

[1]

Table 4. Function table

Input Output nOE nA nY

HLL HHH LXZ

[1] H =HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

Product data sheet Rev. 12 — 8 April 2013 4 of 22

NXP Semiconductors

8. Limiting values

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 5. L imiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

GND

tot

stg

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When V [3] For TSSOP8 packages: above 55 C the value of P

For VSSOP8 packages: above 110 C the value of P For XSON8 and XQFN8 packages: above 118C the value of P

supply voltage 0.5 +6.5 V input clamping current VI < 0 V 50 - mA input voltage

[1]

0.5 +6.5 V output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode

Power-down mode

output current VO = 0 V to V

[1]

0.5 VCC + 0.5 V

[1][2]

0.5 +6.5 V

- 50 mA supply current - +100 mA ground current 100 - mA total power dissipation T

= 40 C to +125 C

amb

[3]

- 300 mW storage temperature 65 +150 C

= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

derates linearly at 2.5 mW/K.

tot

derates linearly at 8.0 mW/K.

tot

derates linearly with 7.8 mW/K.

tot

9. Recommended operating conditions

Table 6. Operating conditions

Symbol Parameter Conditions Min Max Unit

amb

supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage Active mode 0 V

ambient temperature 40 +125 C

t/V input transition rise and fall rate V

= 0 V; Power-down mode 0 5.5 V

= 1.65 V to 2.7 V - 20 ns/V

= 2.7 V to 5.5 V - 10 ns/V

Product data sheet Rev. 12 — 8 April 2013 5 of 22

NXP Semiconductors

10. Static characteristics

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ

= 40 Cto+85C

amb

HIGH-level input voltage VCC= 1.65 V to 1.95 V 0.65  VCC-- V

= 2.3 V to 2.7 V 1.7 - - V

= 2.7 V to 3.6 V 2.0 - - V

= 4.5 V to 5.5 V 0.7  V

-- V

LOW-level input voltage VCC= 1.65 V to 1.95 V - - 0.35  V

= 2.3 V to 2.7 V - - 0.7 V

= 2.7 V to 3.6 V - - 0.8 V

= 4.5 V to 5.5 V - - 0.3  V

LOW-level output voltage VI= VIH or V

IO = 100 A; VCC=1.65Vto5.5V - - 0.1 V

= 4 mA; VCC= 1.65 V - - 0.45 V

= 8 mA; VCC=2.3V - - 0.3 V

= 12 mA; VCC= 2.7 V - - 0.4 V

= 24 mA; VCC= 3.0 V - - 0.55 V

= 32 mA; VCC= 4.5 V - - 0.55 V

HIGH-level output voltage VI= VIH or V

IO = 100 A; VCC= 1.65 V to 5.5 V VCC  0.1 - - V

= 4 mA; VCC=1.65V 1.2 - - V

= 8 mA; VCC=2.3V 1.9 - - V

= 12 mA; VCC=2.7V 2.2 - - V

= 24 mA; VCC=3.0V 2.3 - - V

= 32 mA; VCC=4.5V 3.8 - - V

OFF

I

input leakage current VI= 5.5 V or GND; VCC=0Vto5.5V - 0.1 5 A OFF-state output curren t VI= VIH or VIL; VO= 5.5 V or GND;

= 3.6 V

- 0.1 10 A

power-off leakage current VIor VO=5.5V; VCC=0 V - 0.1 10 A supply current VI= 5.5 V or GND;

=1.65Vto5.5V; IO=0A

additional supply current per pin; VI=VCC 0.6 V; IO=0A;

= 2.3 V to 5.5 V

-0.110A

-5500A

input capacitance - 2 - pF

[1]

Max Unit

Product data sheet Rev. 12 — 8 April 2013 6 of 22

NXP Semiconductors

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 7. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ

= 40 C to +125 C

amb

HIGH-level input voltage VCC= 1.65 V to 1.95 V 0.65  VCC-- V

= 2.3 V to 2.7 V 1.7 - - V

= 2.7 V to 3.6 V 2.0 - - V

= 4.5 V to 5.5 V 0.7  V

-- V

LOW-level input voltage VCC= 1.65 V to 1.95 V - - 0.35  V

= 2.3 V to 2.7 V - - 0.7 V

= 2.7 V to 3.6 V - - 0.8 V

= 4.5 V to 5.5 V - - 0.3  V

LOW-level output voltage VI= VIH or V

IO = 100 A; VCC=1.65Vto5.5V - - 0.1 V

= 4 mA; VCC= 1.65 V - - 0.70 V

= 8 mA; VCC=2.3V - - 0.45 V

= 12 mA; VCC= 2.7 V - - 0.60 V

= 24 mA; VCC= 3.0 V - - 0.80 V

= 32 mA; VCC= 4.5 V - - 0.80 V

HIGH-level output voltage VI= VIH or V

IO = 100 A; VCC= 1.65 V to 5.5 V VCC  0.1 - - V

= 4 mA; VCC= 1.65 V 0.95 - - V

= 8 mA; VCC=2.3V 1.7 - - V

= 12 mA; VCC=2.7V 1.9 - - V

= 24 mA; VCC=3.0V 2.0 - - V

= 32 mA; VCC=4.5V 3.4 - - V

input leakage current VI= 5.5 V or GND; VCC=0Vto5.5V - - 20 A OFF-state output curren t VI= VIH or VIL; VO= 5.5 V or GND;

--20 A

VCC= 3.6 V

OFF

I

power-off leakage current VIor VO=5.5V; VCC=0 V - - 20 A supply current VI= 5.5 V or GND;

=1.65Vto5.5V; IO=0A

additional supply current per pin; VI=VCC 0.6 V; IO=0A;

= 2.3 V to 5.5 V

--40A

--5mA

[1]

Max Unit

[1] Typical values are measured at VCC = 3.3 V and T

Product data sheet Rev. 12 — 8 April 2013 7 of 22

amb

= 25 C.

NXP Semiconductors

11. Dynamic characteristics

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); fo r test circuit see Figure 9.

Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit

Min Typ

propagation delay nA to nY; see Figure 7

[2]

[1]

Max Min Max

VCC= 1.65 V to 1.95 V 1.0 3.9 9.8 1.0 12.3 ns

= 2.3 V to 2.7 V 0.5 2.6 4.9 0.5 6.3 ns

= 2.7 V 1.0 2.8 4.7 1.0 5.9 ns

= 3.0 V to 3.6 V 0.5 2.4 4.3 0.5 5.4 ns

= 4.5 V to 5.5 V 0.5 1.9 3.2 0.5 4.0 ns

enable time nOE to nY; see Figure 8

[3]

VCC= 1.65 V to 1.95 V 1.0 4.1 10.0 1.0 12.5 ns

= 2.3 V to 2.7 V 1.0 2.6 5.0 1.0 6.3 ns

= 2.7 V 1.0 2.8 4.7 1.0 5.9 ns

= 3.0 V to 3.6 V 1.0 2.4 4.1 1.0 5.1 ns

= 4.5 V to 5.5 V 0.5 1.8 3.1 0.5 3.9 ns

dis

disable time nOE to nY; see Figure 8

[4]

VCC= 1.65 V to 1.95 V 1.0 3.3 12.6 1.0 15.4 ns

= 2.3 V to 2.7 V 0.5 1.9 5.7 0.5 7.5 ns

= 2.7 V 1.5 3.0 4.8 1.5 6.2 ns

= 3.0 V to 3.6 V 1.0 2.5 4.4 1.0 5.7 ns

= 4.5 V to 5.5 V 0.5 1.8 3.3 0.5 4.4 ns

power dissipation capacitance

per buffer; VI = GND to V

output enabled - 17 - - - pF

[5]

output disabled - 5 - - - pF

[1] Typical values are measured at T [2] t

is the same as t

[3] ten is the same as t [4] t

is the same as t

dis

PLH PZH

PLZ

and t and t and t

PHL PZL PHZ

=25C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.

amb

[5] CPDis used to determine the dynamic power dissipation (PDin W).

 V

D=CPD

= input frequency in MHz;

= output frequency in MHz;

= output load capacitance in pF;

= supply voltage in V;

 fi N+(CL V

 fo) where:

N = number of inputs switching;

 V

(C

 fo) = sum of outputs.

Product data sheet Rev. 12 — 8 April 2013 8 of 22

NXP Semiconductors

mna230

PHL

PLH

nA input

nY output

GND

mna949

PLZ

PHZ

outputs

disabled

outputs enabled

outputs

enabled

output LOW-to-OFF OFF-to-LOW

output

HIGH-to-OFF OFF-to-HIGH

nOE input

GND

PZL

PZH

12. Waveforms

Measurement points are given in Table 9. Logic levels: V

Fig 7. The data input (nA) to output (nY) propagation delays

and VOH are typical output voltage levels that occur with the output load.

74LVC2G126

Dual bus buffer/line driver; 3-state

Measurement points are given in Table 9. Logic levels: V

and VOH are typical output voltage levels that occur with the output load.

Fig 8. 3-state enable an d disable times

Table 9. Mea surement points

Supply voltage Input Output V

1.65 V to 1.95 V 0.5  V

2.3 V to 2.7 V 0.5  V

2.7 V 1.5 V 1.5 V V

3.0 V to 3.6 V 1.5 V 1.5 V V

4.5 V to 5.5 V 0.5  V

Product data sheet Rev. 12 — 8 April 2013 9 of 22

CC CC

0.5  V

CC CC

VOL + 0.15 V VOH  0.15 V VOL + 0.15 V VOH  0.15 V

+ 0.3 V VOH  0.3 V

VOL + 0.3 V VOH  0.3 V

NXP Semiconductors

EXT

mna616

DUT

Test data is given in Table 10. Definitions for test circuit:

= Load resistance.

= Load capacitance including jig and probe capacitance.

= Termination resistance should be equal to the output impedance Zo of the pulse generator.

= External voltage for measuring switching times.

EXT

Fig 9. Test circuit for measuring switching times

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 10. Test data

Supply voltage Input Load V V

1.65 V to 1.95 V V

2.3 V to 2.7 V V

EXT

CC CC

tr, t

PLH

, t

PHL

PZH

, t

PHZ

 2.0ns 30pF 1k open GND 2  V  2.0 ns 30 pF 500  open GND 2  V

2.7 V 2.7 V  2.5 ns 50 pF 500  open GND 6 V

3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open GND 6 V

4.5 V to 5.5 V V

 2.5 ns 50 pF 500  open GND 2  V

PZL

, t

PLZ

CC CC

Product data sheet Rev. 12 — 8 April 2013 10 of 22

NXP Semiconductors

UNIT

max.

A2A3b

wyv

ceD

(1)E(1)

(1)

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9

0.65

4.1

3.9

0.70

0.35

8° 0°

0.13 0.10.20.5

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.47

0.33

SOT505-2 - - -

02-01-16

w M

0.25

(A3)

detail X

v M

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

1.1

pin 1 index

13. Package outline

74LVC2G126

Dual bus buffer/line driver; 3-state

Fig 10. Package outline SOT505-2 (TSSOP8)

Product data sheet Rev. 12 — 8 April 2013 11 of 22

NXP Semiconductors

UNIT

max.

A2A3b

wyv

ceD

(1)E(2)

(1)

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.15

0.00

0.85

0.60

0.27

0.17

0.23

0.08

2.1

1.9

2.4

2.2

0.5

3.2

3.0

0.4

0.1

8° 0°

0.13 0.10.20.4

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.40

0.15

0.21

0.19

SOT765-1 MO-187

02-06-07

w M

0.12

(A3)

detail X

v M

2.5 5 mm0

scale

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

pin 1 index

74LVC2G126

Dual bus buffer/line driver; 3-state

Fig 11. Package outline SOT765-1 (VSSOP8)

Product data sheet Rev. 12 — 8 April 2013 12 of 22

NXP Semiconductors

terminal 1 index area

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT833-1 - - -

MO-252

- - -

SOT833-1

07-11-14 07-12-07

DIMENSIONS (mm are the original dimensions)

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

0.25

0.17

2.0

1.9

0.35

0.27

max

b E

1.05

0.95

ee1L

0.40

0.32

0.50.6

(1)

max

0.5 0.04

8×

(2)

4×

(2)

74LVC2G126

Dual bus buffer/line driver; 3-state

Fig 12. Package outline SOT833-1 (XSON8)

Product data sheet Rev. 12 — 8 April 2013 13 of 22

NXP Semiconductors

References

Outline

version

European projection

Issue date

IEC JEDEC JEITA

SOT1089

MO-252

sot1089_po

10-04-09 10-04-12

Unit

max nom

min

0.5 0.04 1.40

1.35

1.30

1.05

1.00

0.95

0.55 0.35

0.35

0.30

0.27

(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm

SOT1089

A1bL

0.40

0.35

0.32

0.20

0.15

0.12

DEee

0 0.5 1 mm

scale

terminal 1 index area

detail X

terminal 1 index area

(4×)

(2)

(8×)

(2)

74LVC2G126

Dual bus buffer/line driver; 3-state

Fig 13. Package outline SOT1089 (XSON8)

Product data sheet Rev. 12 — 8 April 2013 14 of 22

NXP Semiconductors

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm

74LVC2G126

Dual bus buffer/line driver; 3-state

SOT996-2

terminal 1 index area

B A

detail X

0 1 2 mm

scale

Dimensions (mm are the original dimensions)

(1)

Unit

Outline version

SOT996-2

max

nom

min

0.5

A1b

0.05

0.00

DEee1LL1L2v

0.35

2.1

3.1

0.15

1.9

IEC JEDEC JEITA

0.5 1.5

2.9

0.5

0.3

References

0.15

0.05

0.6

0.4

0.1

0.05

0.1

sot996-2_po

European projection

Issue date

07-12-21 12-11-20

Fig 14. Package outline SOT996-2 (XSON8)

Product data sheet Rev. 12 — 8 April 2013 15 of 22

NXP Semiconductors

74LVC2G126

Dual bus buffer/line driver; 3-state

XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm

terminal 1 index area

SOT902-2

detail X

terminal 1 index area

Dimensions

(1)

Unit

max

nom

min

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline

version

SOT902-2 - - -

A1b

0.5 0.05

0.00

0.25

0.20

0.15

IEC JEDEC JEITA

- - -

DEee1L

1.65

1.60

1.55

1.65

1.60

1.55

0.55 0.5

MO-255

metal area not for soldering

0 1 2 mm

0.35

0.15

0.30

0.10

0.25

0.05

References

Fig 15. Package outline SOT902-2 (XQFN8)

scale

L1vw

0.05

0.1 0.05

0.05

European projection

sot902-2_po

Issue date

10-11-02 11-03-31

Product data sheet Rev. 12 — 8 April 2013 16 of 22

NXP Semiconductors

References

Outline

version

European projection

Issue date

IEC JEDEC JEITA

SOT1116

sot1116_po

10-04-02 10-04-07

Unit

max nom

min

0.35 0.04 1.25

1.20

1.15

1.05

1.00

0.95

0.55 0.3

0.40

0.35

0.32

(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm

SOT1116

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1 index area

(4×)

(2)

(8×)

(2)

b 4321

5678

74LVC2G126

Dual bus buffer/line driver; 3-state

Fig 16. Package outline SOT1116 (XSON8)

Product data sheet Rev. 12 — 8 April 2013 17 of 22

NXP Semiconductors

References

Outline

version

European projection

Issue date

IEC JEDEC JEITA

SOT1203

sot1203_po

10-04-02 10-04-06

Unit

max nom

min

0.35 0.04 1.40

1.35

1.30

1.05

1.00

0.95

0.55 0.35

0.40

0.35

0.32

(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm

SOT1203

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1 index area

(4×)

(2)

(8×)

(2)

74LVC2G126

Dual bus buffer/line driver; 3-state

Fig 17. Package outline SOT1203 (XSON8)

Product data sheet Rev. 12 — 8 April 2013 18 of 22

NXP Semiconductors

14. Abbreviations

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic

15. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC2G126 v.12 20130408 Product data sheet - 74LVC2G126 v.11 Modifications: 74LVC2G126 v.11 20120622 Product data sheet - 74LVC2G126 v.10 Modifications: 74LVC2G126 v.10 20111201 Product data sheet - 74LVC2G126 v.9 Modifications: 74LVC2G126 v.9 20100913 Product data sheet - 74LVC2G126 v.8 74LVC2G126 v.8 20080505 Product data sheet - 74LVC2G126 v.7 74LVC2G126 v.7 20080228 Product data sheet - 74LVC2G126 v.6 74LVC2G126 v.6 20070907 Product data sheet - 74LVC2G126 v.5 74LVC2G126 v.5 20061006 Product data sheet - 74LVC2G126 v.4 74LVC2G126 v.4 20050201 Product specification - 74LVC2G126 v.3 74LVC2G126 v.3 20040922 Product specification - 74LVC2G126 v.2 74LVC2G126 v.2 20030901 Product specification - 74LVC2G126 v.1 74LVC2G126 v.1 20030310 Product specification - -

• For type number 74LVC2G126GD XSON8U has changed to XSON8.

• For type number 74LVC2G126GM the SOT code has changed to SOT902-2.

• Legal pages updated.

Product data sheet Rev. 12 — 8 April 2013 19 of 22

NXP Semiconductors

74LVC2G126

Dual bus buffer/line driver; 3-state

16. Legal information

16.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) d escribed i n this docu ment may have changed si nce this d ocument was p ublished and may dif fer in case of multiple devices. The latest product statu s

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the cust omer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is open for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

, unless otherwise

Product data sheet Rev. 12 — 8 April 2013 20 of 22

NXP Semiconductors

74LVC2G126

Dual bus buffer/line driver; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neit her qua lif ied nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, custome r (a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct claims result ing from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 12 — 8 April 2013 21 of 22

NXP Semiconductors

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 4

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

9 Recommended operating conditions. . . . . . . . 5

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17 Contact information. . . . . . . . . . . . . . . . . . . . . 21

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

74LVC2G126

Dual bus buffer/line driver; 3-state

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 April 2013

Document identifier: 74LVC2G126

NXP 74LVC2G126DC, 74LVC2G126DP, 74LVC2G126GD, 74LVC2G126GF, 74LVC2G126GM Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Ordering information

4. Marking

5. Functional diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

8. Limiting values

9. Recommended operating conditions

10. Static characteristics

11. Dynamic characteristics

12. Waveforms

13. Package outline

14. Abbreviations

15. Revision history

16. Legal information

16.1 Data sheet status

16.2 Definitions

16.3 Disclaimers

16.4 Trademarks

17. Contact information

18. Contents