NXP 74LVC2G126DC, 74LVC2G126DP, 74LVC2G126GD, 74LVC2G126GF, 74LVC2G126GM Schematic [ru]

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74LVC2G126

Dual bus buffer/line driver; 3-state

Rev. 12 — 8 April 2013 Product data sheet

1. General description

The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input (pin nOE). A LOW-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G126 as a translator in a mixed 3.3 Vand 5 V environment.

It is fully specified for partial power-down applications using I disables the output, preventing a damaging backflow current throu gh the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V  5 V tolerant input/output for interfacing with 5 V logic  High noise immunity  Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8-B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V  24 mA output drive (V  CMOS low power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V  Multiple package options  Specifie d from 40 Cto+85C and 40 C to +125 C

=3.0V)

OFF

. The I

circuitry

OFF

NXP Semiconductors

3. Ordering information

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 1. Ordering information

Type number Package

74LVC2G126DP 40 Cto+125C TSSOP8 plastic thin shrink small outline package; 8 leads;

74LVC2G126DC 40Cto+125C VSSOP8 plastic very thin shrink small outline package; 8 leads;

74LVC2G126GT 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;

74LVC2G126GF 40 C to +125 C XSON8 extremely thin small outline package; no leads;

74LVC2G126GD 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;

74LVC2G126GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads;

74LVC2G126GN 40 C to +125 C XSON8 extremely thin small outline package; no leads;

74LVC2G126GS 40 C to +125 C XSON8 extremely thin small outline package; no leads;

Temperature range Name Description Version

body width 3 mm; lead length 0.5 mm

body width 2.3 mm

8 terminals; body 1  1.95  0.5 mm

8 terminals; body 1.35  1  0.5 mm

8 terminals; body 3  2  0.5 mm

8 terminals; body 1.6  1.6  0.5 mm

8 terminals; body 1.2  1.0  0.35 mm

8 terminals; body 1.35  1.0  0.35 mm

4. Marking

SOT505-2

SOT765-1

SOT833-1

SOT1089

SOT996-2

SOT902-2

SOT1116

SOT1203

Table 2. Marking codes

Type number Marking code

74LVC2G126DP V26 74LVC2G126DC V26 74LVC2G126GT V26 74LVC2G126GF VN 74LVC2G126GD V26 74LVC2G126GM V26 74LVC2G126GN VN 74LVC2G126GS VN

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

[1]

Product data sheet Rev. 12 — 8 April 2013 2 of 22

NXP Semiconductors

001aah787

2OE

1OE

mna234

nOE

74LVC2G126

1OE V

1A 2OE 2Y 1Y

GND 2A

001aab740

1 2 3 4

6 5

8 7

74LVC2G126

2OE

1OE

GND

001aab741

Transparent top view

74LVC2G126

Dual bus buffer/line driver; 3-state

5. Functional diagram

Fig 1. Logic symbol Fig 2. Logic diagram (one gate)

6. Pinning information

6.1 Pinning

Fig 3. Pin configuration SOT505-2 and SOT765-1 Fig 4. Pin configuration SOT833-1, SOT1089,

Product data sheet Rev. 12 — 8 April 2013 3 of 22

SOT1116 and SOT1203

NXP Semiconductors

001aah949

74LVC2G126

Transparent top view

1OE

GND

2OE

001aaf056

1A1Y

1OE

2OE

GND

Transparent top view

terminal 1 index area

74LVC2G126

Dual bus buffer/line driver; 3-state

Fig 5. Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-2

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203

1OE, 2OE 1, 7 7, 1 output enable input (active HIGH) 1A, 2A 2, 5 6, 3 data input 1Y, 2Y 6, 3 2, 5 data output GND 4 4 ground (0 V) V

8 8 supply voltage

SOT902-2

7. Functional description

[1]

Table 4. Function table

Input Output nOE nA nY

HLL HHH LXZ

[1] H =HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

Product data sheet Rev. 12 — 8 April 2013 4 of 22

NXP Semiconductors

8. Limiting values

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 5. L imiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

GND

tot

stg

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When V [3] For TSSOP8 packages: above 55 C the value of P

For VSSOP8 packages: above 110 C the value of P For XSON8 and XQFN8 packages: above 118C the value of P

supply voltage 0.5 +6.5 V input clamping current VI < 0 V 50 - mA input voltage

[1]

0.5 +6.5 V output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode

Power-down mode

output current VO = 0 V to V

[1]

0.5 VCC + 0.5 V

[1][2]

0.5 +6.5 V

- 50 mA supply current - +100 mA ground current 100 - mA total power dissipation T

= 40 C to +125 C

amb

[3]

- 300 mW storage temperature 65 +150 C

= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

derates linearly at 2.5 mW/K.

tot

derates linearly at 8.0 mW/K.

tot

derates linearly with 7.8 mW/K.

tot

9. Recommended operating conditions

Table 6. Operating conditions

Symbol Parameter Conditions Min Max Unit

amb

supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage Active mode 0 V

ambient temperature 40 +125 C

t/V input transition rise and fall rate V

= 0 V; Power-down mode 0 5.5 V

= 1.65 V to 2.7 V - 20 ns/V

= 2.7 V to 5.5 V - 10 ns/V

Product data sheet Rev. 12 — 8 April 2013 5 of 22

NXP Semiconductors

10. Static characteristics

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ

= 40 Cto+85C

amb

HIGH-level input voltage VCC= 1.65 V to 1.95 V 0.65  VCC-- V

= 2.3 V to 2.7 V 1.7 - - V

= 2.7 V to 3.6 V 2.0 - - V

= 4.5 V to 5.5 V 0.7  V

-- V

LOW-level input voltage VCC= 1.65 V to 1.95 V - - 0.35  V

= 2.3 V to 2.7 V - - 0.7 V

= 2.7 V to 3.6 V - - 0.8 V

= 4.5 V to 5.5 V - - 0.3  V

LOW-level output voltage VI= VIH or V

IO = 100 A; VCC=1.65Vto5.5V - - 0.1 V

= 4 mA; VCC= 1.65 V - - 0.45 V

= 8 mA; VCC=2.3V - - 0.3 V

= 12 mA; VCC= 2.7 V - - 0.4 V

= 24 mA; VCC= 3.0 V - - 0.55 V

= 32 mA; VCC= 4.5 V - - 0.55 V

HIGH-level output voltage VI= VIH or V

IO = 100 A; VCC= 1.65 V to 5.5 V VCC  0.1 - - V

= 4 mA; VCC=1.65V 1.2 - - V

= 8 mA; VCC=2.3V 1.9 - - V

= 12 mA; VCC=2.7V 2.2 - - V

= 24 mA; VCC=3.0V 2.3 - - V

= 32 mA; VCC=4.5V 3.8 - - V

OFF

I

input leakage current VI= 5.5 V or GND; VCC=0Vto5.5V - 0.1 5 A OFF-state output curren t VI= VIH or VIL; VO= 5.5 V or GND;

= 3.6 V

- 0.1 10 A

power-off leakage current VIor VO=5.5V; VCC=0 V - 0.1 10 A supply current VI= 5.5 V or GND;

=1.65Vto5.5V; IO=0A

additional supply current per pin; VI=VCC 0.6 V; IO=0A;

= 2.3 V to 5.5 V

-0.110A

-5500A

input capacitance - 2 - pF

[1]

Max Unit

Product data sheet Rev. 12 — 8 April 2013 6 of 22

NXP Semiconductors

74LVC2G126

Dual bus buffer/line driver; 3-state

Table 7. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ

= 40 C to +125 C

amb

HIGH-level input voltage VCC= 1.65 V to 1.95 V 0.65  VCC-- V

= 2.3 V to 2.7 V 1.7 - - V

= 2.7 V to 3.6 V 2.0 - - V

= 4.5 V to 5.5 V 0.7  V

-- V

LOW-level input voltage VCC= 1.65 V to 1.95 V - - 0.35  V

= 2.3 V to 2.7 V - - 0.7 V

= 2.7 V to 3.6 V - - 0.8 V

= 4.5 V to 5.5 V - - 0.3  V

LOW-level output voltage VI= VIH or V

IO = 100 A; VCC=1.65Vto5.5V - - 0.1 V

= 4 mA; VCC= 1.65 V - - 0.70 V

= 8 mA; VCC=2.3V - - 0.45 V

= 12 mA; VCC= 2.7 V - - 0.60 V

= 24 mA; VCC= 3.0 V - - 0.80 V

= 32 mA; VCC= 4.5 V - - 0.80 V

HIGH-level output voltage VI= VIH or V

IO = 100 A; VCC= 1.65 V to 5.5 V VCC  0.1 - - V

= 4 mA; VCC= 1.65 V 0.95 - - V

= 8 mA; VCC=2.3V 1.7 - - V

= 12 mA; VCC=2.7V 1.9 - - V

= 24 mA; VCC=3.0V 2.0 - - V

= 32 mA; VCC=4.5V 3.4 - - V

input leakage current VI= 5.5 V or GND; VCC=0Vto5.5V - - 20 A OFF-state output curren t VI= VIH or VIL; VO= 5.5 V or GND;

--20 A

VCC= 3.6 V

OFF

I

power-off leakage current VIor VO=5.5V; VCC=0 V - - 20 A supply current VI= 5.5 V or GND;

=1.65Vto5.5V; IO=0A

additional supply current per pin; VI=VCC 0.6 V; IO=0A;

= 2.3 V to 5.5 V

--40A

--5mA

[1]

Max Unit

[1] Typical values are measured at VCC = 3.3 V and T

Product data sheet Rev. 12 — 8 April 2013 7 of 22

amb

= 25 C.

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