NXP 74AHC1G09GV, 74AHC1G09GW Schematic [ru]

74AHC1G09

2-input AND gate with open-drain output

Rev. 02 — 18 December 2007 Product data sheet

1. General description

The 74AHC1G09 is a high-speed Si-gate CMOS device.
The 74AHC1G09 provides the 2-input AND function with open-drain output.
The output of the 74AHC1G09 is an open drain and can be connected to other open-drain

outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For
digital operation this device must have a pull-up resistor to establish a logic HIGH level.

2. Features

■ High noise immunity

■ Low power dissipation

■ SOT353-1 and SOT753 package options

■ ESD protection:

◆ HBM JESD22-A114E: exceeds 2000 V

◆ MM JESD22-A115-A: exceeds 200 V

◆ CDM JESD22-C101C: exceeds 1000 V

■ Specified from −40 °Cto+85°C and from −40 °C to +125 °C.

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC1G09GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads;

body width 1.25 mm

74AHC1G09GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753

SOT353-1

4. Marking

Table 2. Marking

Type number Marking code

74AHC1G09GW A9
74AHC1G09GV A09

NXP Semiconductors

74AHC1G09

2-input AND gate with open-drain output

5. Functional diagram

1

B

2

A

4

001aad598

Y

1
2

&

001aad599

4

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

A

B

6. Pinning information

6.1 Pinning

Y

GND

001aad600

1

BV

2

A

GND Y

09

3

001aad601

5

CC

4

Fig 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A)

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

B 1 data input B
A 2 data input A
GND 3 ground (0 V)
Y 4 data output Y
V

CC

5 supply voltage

7. Functional description

Table 4. Function table

Input Output
A B Y

LLL
LHL
HLL
HHZ

[1]

[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.

74AHC1G09_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 18 December 2007 2 of 10

NXP Semiconductors

74AHC1G09

2-input AND gate with open-drain output

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

V
V
V

I

IK

I

OK

I

O

I

CC

I

GND

T
P

CC
I
O

stg
tot

supply voltage −0.5 +7.0 V
input voltage
output voltage active mode

high-impedance mode
input clamping current VI< −0.5 V
output clamping current VO< −0.5 V

[1]

−0.5 +7.0 V

[1]

−0.5 +7.0 V

[1]

−0.5 +7.0 V

[1]

- −20 mA

[1]

- ±20 mA
output current VO> −0.5 V - 25 mA
supply current - ±75 mA
GND current - ±75 mA
storage temperature −65 +150 °C
total power dissipation T

= −40 °C to +125 °C

amb

[2]

- 250 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 and SC-74A packages: above 87.5 °C the value of P

derates linearly with 4.0 mW/K.

tot

9. Recommended operating conditions

Table 6. Recommended operating operations

Symbol Parameter Conditions Min Typ Max Unit

V

CC

V

I

V

O

supply voltage 2.0 5.0 5.5 V
input voltage 0 - 5.5 V
output voltage active mode 0 - V

CC

V

high-impedance mode 0 - 6.0 V

T

amb

∆t/∆V input transition rise and fall rate V

ambient temperature −40 +25 +125 °C

= 3.0 V to 3.6 V - - 100 ns/V

CC

= 4.5 V to 5.5 V - - 20 ns/V

V

CC

10. Static characteristics

Table 7. Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

V

IH

HIGH-level
input voltage

V

IL

LOW-level
input voltage

VCC= 2.0 V 1.5 - - 1.5 - 1.5 - V

= 3.0 V 2.1 - - 2.1 - 2.1 - V

V

CC

= 5.5 V 3.85 - - 3.85 - 3.85 - V

V

CC

VCC= 2.0 V - - 0.5 - 0.5 - 0.5 V

= 3.0 V - - 0.9 - 0.9 - 0.9 V

V

CC

= 5.5 V - - 1.65 - 1.65 - 1.65 V

V

CC

74AHC1G09_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 18 December 2007 3 of 10

NXP Semiconductors

74AHC1G09

2-input AND gate with open-drain output

Table 7. Static characteristics

…continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

V

OL

I

I

I

OZ

I

CC

C

I

LOW-level
output voltage

input leakage
current

OFF-state
output current

VI= VIH or V

IL

IO= 50 µA; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V

= 50 µA; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V

I

O

= 50 µA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V

I

O

= 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V

I

O

= 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V

I

O

VI= 5.5 Vor GND;
V

= 0 V to 5.5 V

CC

VI= VIH or VIL; VO = VCC or
GND; V

CC

= 5.5 V

supply current VI=VCCor GND; IO = 0 A;

V

= 5.5 V

CC

input

--±0.1 - ±1.0 - ±2.0 µA

--±0.25 ±2.5 ±10.0 µA

- - 1.0 - 10 - 20 µA

- 1.5 10 - 10 - 10 pF

capacitance

11. Dynamic characteristics

Table 8. Dynamic characteristics

GND = 0 V; for test circuit seeFigure 6.

Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

t

pd

propagation delay A and B to Y;

see

Figure 5

VCC = 3.0 V to 3.6 V

[1]

[2]

CL= 15 pF - 4.6 7.5 1.0 8.5 1.0 9.0 ns

= 50 pF - 6.5 11.0 1.5 12.0 1.5 12.5 ns

C

L

= 4.5 V to 5.5 V

V

CC

[3]

CL= 15 pF - 3.2 5.5 1.0 6.5 1.0 7.0 ns

= 50 pF - 4.6 7.5 1.5 8.0 1.5 8.5 ns

C

L

C

PD

power dissipation
capacitance

[1] tpd is the same as t
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPDis used to determine the dynamic power dissipation (PDin µW).

PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in V;
N = number of inputs switching;
(CL× V

CC

2

PZL

2

× fi× N + (CL× V

CC

× fo) = dissipation due to the output if the combination of the pull up voltage and resistance results in VCC at the output.

CL= 50 pF; fi= 1 MHz;
V

= GND to V

I

and t

PLZ

.

2

× fo) where:

CC

CC

[4]

-5- - - - - pF

74AHC1G09_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 18 December 2007 4 of 10

NXP Semiconductors

12. Waveforms

V

I

A, B input

GND

V

CC

Y output

V

OL

Measurement points are given in Table 9.
VOL is the typical voltage output level that occur with the output load.

Fig 5. The data input (A, B) to output (Y) propagation delays

Table 9. Measurement points

Input Output
V

M

0.5V

CC

V

M

0.5V

CC

V

M

t

PLZ

V

74AHC1G09

2-input AND gate with open-drain output

t

PZL

V

M

X

001aad602

V

X

VOL + 0.3 V

V

CC

PULSE

GENERATOR

V

I

R

D.U.T.

T

V

O

Test data is given in Table 10.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig 6. Load circuit for switching times

Table 10. Test data

Input Load S
V

I

GND to V
GND to V

CC
CC

tr, t

f

R

L

C

L

≤ 3.0 ns 1000 Ω 15 pF GND V
≤ 3.0 ns 1000 Ω 50 pF GND V

t

1

PHZ

S

1

V

CC

open

R

L

1000 Ω

C

L

mna232

, t

PZH

GND

=

t

PLZ

CC
CC

, t

PZL

t

PLH

open
open

, t

PHL

74AHC1G09_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 18 December 2007 5 of 10

NXP Semiconductors

13. Package outline

74AHC1G09

2-input AND gate with open-drain output

TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm

D

y

Z

5

4

13

e

e

1

w M

b

p

c

A

2

E

H

E

A

1

L

p

L

detail X

SOT353-1

A

X

v M

A

(A3)

A

θ

1.5 3 mm0

scale

DIMENSIONS (mm are the original dimensions)

A

A

UNIT

max.

mm

1.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE
VERSION

SOT353-1 MO-203 SC-88A

1

0.101.0

0.8

A2A3b

0.15

IEC JEDEC JEITA

p

0.30

0.15

ceD

0.25

0.08

(1)E(1)

2.25

1.35

1.85

1.15

REFERENCES

0.65

e

1.3

LH

1

E

2.25

2.0

L

p

0.46

0.21

PROJECTION

EUROPEAN

wyv

0.1 0.10.30.425

(1)

Z

0.60

0.15

ISSUE DATE

00-09-01
03-02-19

θ

7°
0°

Fig 7. Package outline SOT353-1 (TSSOP5)

74AHC1G09_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 18 December 2007 6 of 10

NXP Semiconductors

74AHC1G09

2-input AND gate with open-drain output

Plastic surface-mounted package; 5 leads SOT753

D

y

E

H

E

AB

X

v M

A

45

Q

A

A

1

c

132

e

detail X

b

p

wBM

L

p

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1.1

mm

0.9

OUTLINE
VERSION

SOT753 SC-74A

0.100

0.013

b

cD

p

1

0.40

0.26

0.25

0.10

IEC JEDEC JEITA

3.1

2.7

E

1.7

1.3

REFERENCES

e

0.95

H

3.0

2.5

L

Qywv

p

E

0.6

0.2

0.33

0.23

0.2 0.10.2

EUROPEAN

PROJECTION

ISSUE DATE

02-04-16
06-03-16

Fig 8. Package outline SOT753 (SC-74A)

74AHC1G09_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 18 December 2007 7 of 10

NXP Semiconductors

2-input AND gate with open-drain output

74AHC1G09

14. Abbreviations

Table 11. Abbreviations

Acronym Description

CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model

15. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AHC1G09_2 20071218 Product data sheet - 74AHC1G09_1
Modifications:

74AHC1G09_1 20050926 Product data sheet - -

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Package SOT753 added to Section 3, Section 4 and Section 13.

• Quick reference data section removed.

74AHC1G09_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 18 December 2007 8 of 10

NXP Semiconductors

16. Legal information

16.1 Data sheet status

74AHC1G09

2-input AND gate with open-drain output

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was publishedand may differin case of multiple devices. The latest product status

information is available on the Internet at URL

[1][2]

Product status

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability forthe consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or

[3]

http://www.nxp.com.

Definition

malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device.Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyanceor implication of any license under any copyrights, patents
or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names,service namesand trademarks
are the property of their respective owners.

17. Contact information

For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [e-mail]

74AHC1G09_2 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 02 — 18 December 2007 9 of 10

NXP Semiconductors

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

7 Functional description . . . . . . . . . . . . . . . . . . . 2

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

9 Recommended operating conditions. . . . . . . . 3

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 3

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 4

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 6

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 8

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 8

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

17 Contact information. . . . . . . . . . . . . . . . . . . . . . 9

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

74AHC1G09

2-input AND gate with open-drain output

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Date of release: 18 December 2007

Document identifier: 74AHC1G09_2