NSC SCANSTA101ME, SCANSTA101W-QML, SCANPSC100FMW Datasheet
SCANPSC100F
Embedded Boundary Scan Controller
(IEEE 1149.1 Support)
General Description
The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is
associated with applying serial patterns with a parallel processor. The ’PSC100F operates by serializing data from the
parallel bus for shifting through the chain of 1149.1compliant
components (i.e., scan chain). Scan data returning from the
scan chain is placed on the parallel port to be read by the
host processor. Up to two scan chains can be directly controlled with the ’PSC100F via two independent TMS pins.
Scan control is supplied with user specific patterns which
makes the ’PSC100F protocol-independent. Overflow and
underflow conditions are prevented by stopping the test
clock.A32-bit counter is used to program the number of TCK
cycles required to complete a scan operation within the
boundary scan chain or to complete a ’PSC100F Built-In Self
Test (BIST) operation. SCANPSC100F device drivers and
1149.1 embedded test application code are available with
National’s SCANEase software tools.
Features
n Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
n Supported by National’s SCAN Ease (Embedded
Application Software Enabler) Software
n Uses generic, asynchronous processor interface;
compatible with a wide range of processors and PCLK
frequencies
n Directly supports up to two 1149.1 scan chains
n 16-bit Serial Signature Compaction (SSC) at the Test
Data In (TDI) port
n Automatically produces pseudo-random patterns at the
Test Data Out (TDO) port
n Fabricated on FACT
™
1.5 µm CMOS process
n Supports 1149.1 test clock (TCK) frequencies up to
25 MHz
n TTL-compatible inputs; full-swing CMOS outputs with
24 mA source/sink capability
n Standard Microcircuit Drawing (SMD) 5962-9475001
Connection Diagrams
FACT™is a trademark of Fairchild Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
28-Pin DIP and Flatpak
DS100325-1
Pin Assignment for LCC
DS100325-18
September 1998
SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support)
© 1999 National Semiconductor Corporation DS100325 www.national.com
Chip Architecture
The ’PSC100 is designed to act together with a parallel bus
host as a serial test bus master. Parallel data is written by the
host to the ’PSC100, which serializes the data for application
to a serial test bus. Serial data returningfrom thetarget scan
chain(s) is placed on the processor port for parallel reads.
Several features are included in the ’PSC100 which make
scan test communication more convenient and efficient.
Figure 1
shows the major functional blocks of the ’PSC100
design. The Parallel Processor Interface (PPI) is an asynchronous, 8-bit parallel interface which is used by the host
processor to write and read data. The PPI generates the
necessary internal data, address, and control signals to
complete internal write and read operations.
The Serial Scan Interface (SSI) consists of a bank of
double-buffered parallel/serial shift registers (i.e.,a2x8bit
FIFO), or Shifter/Buffers. The double buffering improves efficiency by allowing parallel writes or reads to/from one of the
two 8-bit FIFOs within the shifter/buffer while the other FIFO
is shifting data to/from the scan chain. Three Shifter/Buffers
are provided for outgoing serial data and one for incoming
serial data. TestData Out (TDO) is for scanning out test data
while the two TestMode Select signals (TMS0/1) are used to
provide user specific control data. Test Data In (TDI) receives serial data from the scan chain. A local control block
is associated with each Shifter/Buffer to provide shift and
load control as well as providing full or empty status. The SSI
also provides Test Clock (TCK) Control. TCK is stopped and
started depending on the status of the Shifter/Buffers or the
32-bit Counter. By stopping and starting TCK, scan operations will proceed only when the enabled Shifter/Buffers are
ready to send and/or receive serial data.
The 32-bit Counter (CNT32) is a count-down binary counter
included to assist in controlling the SSI. The initial state of
CNT32 is loaded from the parallel port with four consecutive
writes to its address. When enabled, CNT32 is used to program the number of TCKs applied by the SSI to the boundary scan chain(s). The value of CNT32 can also be used to
generate interrupts (i.e., when CNT32 reaches terminal
count) and to trigger ’PSC100 features, such as, Auto TMS
High (discussed later within this datasheet).
The Mode and Status Registers are used to control and observe the operation of the SSI and CNT32. Each of the
Shifter/Buffers and CNT32 have an associated mode bit
which enables it for participation in on-going operations. Status bits can be used for polling operations.
Pin Descriptions
Pin Description
Name
RST (Input)
The Reset pin is an asynchronous input that, when low, initializes the ’PSC100. Mode bits, Shifter/Buffer
and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states. RST has hysteresis
for improved noise immunity.
SCK (Input) The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK.
SCK has hysteresis for improved immunity.
OE (Input)
Output Enable TRI-STATEs all SSI outputs when high. A 20 kΩ pull-up resistor is connected to
automatically TRI-STATE
®
these outputs when this signal is floating.
DS100325-2
FIGURE 1. ’PSC100 Block Diagram
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Pin Descriptions (Continued)
Pin Description
Name
CE (Input)
Chip Enable, when low, enables the PPI for byte transfers. D(7:0) and RDY are TRI-STATEd if CE is high.
CE has hysteresis for improved noise immunity.
R/W (Input) Read/Write defines a PPI cycle —Read when high, Write when low. R/ W has hysteresis for improved
noise immunity.
STB (Input) Strobe is used for timing all PPI byte transfers. D(7:0) are TRI-STATEd when STB is high. All other PPI
inputs must meet specified setup and hold times with respect to this signal. STB has hysteresis for
improved noise immunity.
A(2:0) The Address pins are used to select the register to be written to or read from.
(Input)
D(7:0) (I/O) Bidirectional pins used to transfer parallel data to and from the ’PSC100.
INT Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active high.
(Output)
RDY
Ready is used to synchronize asynchronous byte transfers between the host and the ’PSC100. When low,
(TRI-STATE RDY signals that the addressed register is ready to be accessed RDY is enabled when CE is low.
Output)
TDO Test Data Out is the serial scan output from the ’PSC100. TDO is enabled when OE is low.
(TRI-STATE
Output)
TMS(1:0) The Test Mode Select pins are serial outputs used to supply control logic to the UUT. TMS(1:0) are
(TRI-STATE enabled when OE is low.
Output)
TCK The Test Clock output is a buffered version of SCK for distribution in the UUT. TCK Control logic starts
(TRI-STATE and stops TCK to prevent overflow and underflow conditions. TCK is enabled when OE is low.
Output)
TDI (Input) Test Data In is the serial scan input to the ’PSC100. A 20 kΩ pull-up resistor is connected to force TDI to
a logic 1 when the TDO line from the UUT is floating.
FRZ (Input) The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode
bit is set, TCK will be forced high if FRZ goes high. FRZ has hysteresis for improved noise immunity.
Mode and Status Registers
MODE REGISTER 0 (MODE0)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TDO TDI CNT32 TMS0 TMS1 Auto TMS High Loop-
Enable Enable Enable Enable Enable Reserved Enable Around
Enable
This register is purely a mode register. All bits are writeable
and readable. The value 00100000 is placed in this register
upon RST low or a synchronous reset operation.
•
Bit 7: This bit enables the TDO shifter/buffer for shift op-
erations. If this bit is set, the TDO shifter/buffer will
cause TCK to stop if it is empty.
•
Bit 6: This bit enables the TDI shifter/buffer for shift op-
erations. If this bit is set, the TDI shifter/buffer will
cause TCK to stop if it is full.
•
Bit 5: This bit enables the 32-bit counter. If this bit is set,
the counter will cause TCK to stop if if has not been
loaded or if it has reached terminal count.
•
Bit 4: This bit enables the TMS0 shifter/bufferfor shift op-
erations. If this bit is set, the TMS0 shifter/bufferwill
cause TCK to stop if it is empty.
•
Bit 3: This bit enables the TMS1 shifter/bufferfor shift op-
erations. If this bit is set, the TMS1 shifter/bufferwill
cause TCK to stop if it is empty.
•
Bit 2: This bit is reserved and should remain as a logic 0
during all ’PSC100 operations.
•
Bit 1: If this bit is set, TMS will be forced high when the
32-bit counter is at state (00000001)h.
•
Bit 0: This bit causes TDI to be connected directly back
through TDO for Loop-Around operations.
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Mode and Status Registers (Continued)
MODE REGISTER 1 (MODE1)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TDO TDI CNT32 PRPG SSC Freeze Test Test
Interrupt Interrrupt Interrupt Enable Enable Pin Loop- Loop-
Enable Enable Enable Enable Back Back
This register is purely a mode register. All bits are writeable
and readable. The value 00000000 is placed in this register
upon RST low or a synchronous reset operation.
•
Bit 7: If this bit is set and the TDO shifter/buffer is
not full (i.e., one or both 8-bit TDO FIFOs
are empty), the INT pin will go high.
•
Bit 6: If this bit is set and the TDI shifter/buffer is
not empty (i.e., one or both 8-bit TDI FIFOs
are full), the INT pin will go high.
•
Bit 5: If this bit is set, and the 32-bit counter is not
loaded or has reached terminal count, the
INT pin will go high.
•
Bit 4: This bit signifies that the TD0 shifter/buffer
is reconfigured as a 32-Bit Pseudo Random
Pattern Generator. If set, and MODE0 Bit 7
is set, the TDO shifter/buffer will stop TCK
until a seed value has been written to all
four of the 8-bit LFSR segments.
•
Bit 3: This bit signifies that the TD1 shifter/buffer
is reconfigured as a 16-Bit Serial Signature
Compactor. If set, and MODE0 Bit 6 is set,
the TDI shifter/buffer will cause TCK to stop
until a seed value has been written to the
two TDI registers.
•
Bit 2: If this bit is set, a high value on FRZ will
force TCK high (see TCK Control Section).
•
Bits 1 and 0: These bits are used to control
Test Loop-Back operations according to the
following table.
MODE1 MODE1 Function
Bit 1 Bit 0
0 0 Normal Operation
0 1 Loop-Back TDO to TDI
1 0 Loop-Back TMS0 to TDI
1 1 Loop Back TMS1 to TDI
MODE REGISTER 2 (MODE2)
Write:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Not Not Not Not Continuous Update Single
Used Used Used Used Update Status Reset Step
CNT32
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TDO TDI CNT32 TMS0 TMS1 Continuous Single
Status Status Status Status Status Update Reset Step
CNT32
This register contains both mode and status bits. Bits 4–7
are status bits only. Bit 3 is a status bit during read operations and a mode bit during write operations. Bits 0–2 are
mode bits only. Upon RST low, or a synchronous reset, the
value placed in MODE2 is 10111000 (Read mode). Latches
used to update status bits 3–7 retain their last state upon
RST and are in an “unknown” state after power-up. Toinitialize the latches to a known state, they need to be updated using the Update Status bit (bit 2) or continuous update bit (bit
3).
•
Bit 7: Set high if theTDO shifter/buffer is not full, i.e., one
or both 8-bit TDO FIFOs are ready to be written to.
•
Bit 6: Set high if the TDI shifter/buffer is not empty, i.e.,
one or both 8-bit TDI FIFOs are ready to be read
from.
•
Bit 5: Set high if the 32-bit counter has not been loaded,
or has reached terminal count.
•
Bit 4: Set high if the TMS0 shifter/buffer is not full, i.e.,
one or both 8-bit TMS0 FIFOs are ready to be written to.
•
Bit 3 (Read Cycle):
Set high if the TMS1 shifter/buffer is not full, i.e.,
one or both 8-bit TMS1 FIFOs are ready to be written to.
•
Bit 3 (Write Cycle):
If set, will cause all status bits to be continuously
updated.
•
Bit 2 (Read Cycle):
Shows the state of the Continuous Update bit during read operations (Bit 3 during writes).
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Mode and Status Registers (Continued)
•
Bit 2 (Write Cycle):
If set, will cause a pulse to be issued internally that
will update all status bits. This bit will be reset upon
completion of the pulse. The state of this bit is not
readable. It is reset upon RST low.
•
Bit 1: If set, will cause a synchronous reset of all func-
tions except the parallel interface. The value of this
bit will return to zero when the reset operation is
complete.
•
Bit 0: If set, will cause the 32-bit counter to count for one
SCK cycle (no TCK cycle will be generated). The
value of this bit will return to zero when the single
step operation is complete.
PROGRAMMING RESTRICTIONS
Because certain mode bits enable shift operations for certain
functions, these mode bits should
not
be changed when shift
operations are in progress. The alignment of all registers
during shift operations is controlled by a 3-bit counter in the
TCK control block. Enabling or disabling a function in the
middle of a shift operation may disrupt the logicnecessary to
keep all shifter/buffers byte-aligned.
For example, if the TDO shifter/buffer (already loaded) is enabled while the 3-bit counter value is 3, the shifter/buffer will
only shift out only five bits of the first byte loaded.
The following bits should not be changed when shift operations are in progress, i.e., when TCK is enabled (see section
on TCK Control).
•
MODE0(7:3)
•
MODE1(4:3)
•
MODE2(0)
Parallel Processor Interface (PPI)
ADDRESS ASSIGNMENT
The following table defines which register is selected for access with the address lines, A(2:0).
A2 A1 A0 R/W Function
0 0 0 0 TDO Shifter/Buffer
0 0 0 1 Counter Register 1
0 0 1 0 TDI Shifter/Buffer
0 0 1 1 TDI Shifter/Buffer
0 1 0 0 TMS0 Shifter/Buffer
0 1 0 1 Counter Register 2
0 1 1 0 TMS1 Shifter/Buffer
0 1 1 1 Counter Register 3
1 0 0 0 32-Bit Counter
1 0 0 1 Counter Register 0
1 0 1 0 MODE0
1 0 1 1 MODE0
1 1 0 0 MODE1
1 1 0 1 MODE1
1 1 1 0 MODE2
1 1 1 1 MODE2
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Parallel Processor Interface (PPI) (Continued)
TIMING WAVEFORMS
Note 1: Valid data is provided on the RDY line a t
pd1
after R/W is asserted low or a t
pd2
after valid data is decoded on A2:0. The RDY line will remain high until the
addressed register is ready to participate in the write operation. This condition only applies when writing to a shifter/buffer and is eliminated (i.e., RDY will go low
immediately once valid) when using shifter/buffer status polling (discussed later in this datasheet).
Note 2: Validdata will not appear on D7:0 (and RDY will remain high) until the addressed register is ready to participate in the read operation. When the addressed
register becomes ready (i.e., a byte is available to be read), valid data will be placed on the D7:0 bus and the RDY pin will go low allowing the bus cycle to continue.
This read cycle delay only applies when reading the TDI shifter/buffer and is eliminated when using shifter/buffer status poling.
DS100325-3
FIGURE 2. Write Cycle
DS100325-4
FIGURE 3. Read Cycle
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Parallel Processor Interface (PPI) (Continued)
TIMING WAVEFORMS (Continued)
Note 3:
Figures 4, 5:Figure 4
shows the best case bus cycle timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe occurs a
setup time, t
s4
or before the falling edge of SCK. This allows the cycle to be completed within 1.5 clock SCK clock cycles.
Figure 5
shows the worst case bus cycle
timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe does not meet the t
s4
requirement between STB and SCK. Therefore,
the propagation of the internal PSC100 control and reset signals is delayed until the next falling edge of SCK. The bus cycle is then completed 1.5 SCK cycles later
creating a total bus cycle time of 2.5 SCK cycles. If worst case timing is considered for bus cycle timing, t
s4
is not a mandatory timing specification.
DS100325-5
FIGURE 4. Consecutive Read/Writes (best case timing)
DS100325-6
FIGURE 5. Consecutive Read/Writes (worst case timing)
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Parallel Processor Interface (PPI) (Continued)
TIMING WAVEFORMS (Continued)
Note 4:
Figures 6, 7
: This diagram shows the timing for a read followed by a write (or write followed by a read). Separate Read and Write data/address latches and
control logic allow consecutive read/write or write/read operations to be overlapped (i.e., do not need to wait 2 or 3 SCK cycles between bus cycles). For the best
case timing scenario (
Figure 6
: rising edge of STB to falling edge of SCK greater than ts4), a new bus cycle can be performed each SCK cycle. For the worst timing
scenario (
Figure 7
: rising edge of STB to falling edge of SCK is less than ts4), a one SCK cycle delay must be included after each back to back read/write or write/
read sequence.
Note 5:
Figures 4, 5, 6, 7
assume that the PSC100 register participating in the bus cycle is ready to accept/provide data. For bus cycles involving a PSC100 shifter/
buffer(s), the ready status of a shifter/buffer can be checked using the status bits in Mode Register 2 prior to the start of the bus cycle. Polling is required when the
RDY pin is not used to provide a processor “handshake”.
READ AND WRITE CYCLES
A Write cycle (see
Figure 2
) is initiated by asserting CE and
R/W low followed by a low on STB a set time later. CE and
STB are gated within the PSC100F and may be asserted
concurrently (i.e., zero setup and hold time). The address is
then asserted on A2:0 to indicate which internal address
within the PSC100F will be written to by the processor. An
address decoder within the PSC100F monitors the address
lines for a valid PSC100F register address. Once a valid address has been decoded, the RDY line becomes active (a
propagation delay time later). The active RDY line will go low
immediately if the addressed register is ready to accept data.
If the addressed register is not ready, the RDY pin will remain high preventing the processor from completing the bus
cycle. Once the register is ready to receive date (see
Table
2
), the RDY pin will go low and processor can resume the
write cycle. The processor then forces a high on STB (a wait
time after RDY goes low) which latches the address (A2:0)
and data (D7:0) completing the bus cycle. The RDY line is
forced high a propagation delay later.
A Read cycle (see
Figure 3
) is initiated by asserting CE low
and R/W high followed by a low on STB a set time later. CE
and STB are gated within the PSC100F and may be asserted concurrently (i.e., zero setup and hold time). The address bits (A2:0) are then asserted to indicate which internal
address within the PSC100F will be read by the processor.
An address decoder within the PSC100F monitors the ad-
dress lines for a valid PSC100F register address. Once a
valid address has been decoded and if the addressed
PSC100F register is ready to be read (see
Table 2
), valid
data is placed on the Data lines (D7:0) a propagation delay
later and the ready line isasserted low.If the addressed register is not ready (e.g., the TDI shifter/buffer is empty), the
ready line will remain high and hold the bus cycle until the
register contains valid data. RDY will then go low allowing
the read cycle to continue. With the high to low edge on RDY
line, the processor can successfully read the valid data.
However,the bus cycle is not completed within the PSC100F
until the rising edge on STB which resets the PSC100F read
logic (required prior to the start of the next read cycle).
Important note concerning the use of RDY : The RDY signal provides a useful “handshake” between the PSC100F
and the processor. However,care must betaken whenusing
the PSC100F RDY signal to prevent a large (or indefinite)
number of processor generated wait states. For example, if
the TDO shifter/buffer is not enabled for shift operations and
the processor writes to the TDO shifter/buffer address 3
times, the two registers which make up the TDO shifter/
buffer will accept the first two bytes of data, but since the
data is not shifting out, the 3rd byte will be held off by the
RDY signal indefinitely. An equally severe problem could result with a finite number of wait states if the application uses
DS100325-20
FIGURE 6. Read/Write or Write/Read (best case timing)
DS100325-7
FIGURE 7. Read/Write or Write/Read (worst case timing)
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