NSC PC87360-IBM-VLA, PC87360-ICK-VLA Datasheet

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PC87360 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support

General Description

The PC87360 is the first member of National Semiconductor’s 128-pin SuperI/O family to support the Low Pin Count (LPC) interface. It provides features to protect the system design, and supports 45 GPIO ports, many with Assert IRQ/

SMI/PWUREQ capability. The PC87360 is PC99 and ACPI compliant, and offers a single-chip solution to the most commonly used PC I/O peripherals.

The PC87360 also incorporates: Fan Speed Control and Monitoring for two fans, a Floppy Disk Controller (FDC), a Keyboard and Mouse Controller (KBC), a full IEEE 1284 Parallel Port, two enhanced Serial Ports (UARTs), one with Infrared (IR) support, an ACCESS.bus

Interface (ACB), System Wake-Up Control (SWC), Interrupt Serializer for Parallel IRQs and an enhanced WATCHDOG timer.

Outstanding Features

●

Bus interface, based on Intel’s

LPC Interface Speciﬁ-

cation

Revision 1.0, September 29th, 1997

●

Protection features, including I/O access lock, GPIO lock and pin conﬁguration lock

●

45 GPIO Ports (37 standard, including 23 with Assert IRQ/

SMI/PWUREQs interrupts; 8 VSB-powered)

●

Fan Speed Control and Monitor for two fans

●

Interrupt Serializer (11 Parallel IRQs to Serial IRQ)

●

Serial IRQ support (15 options)

●

ACCESS.bus Interface, compatible with SMbus physical layer

●

Blinking LEDs

●

128-pin PQFP Package

Block Diagram

System Wake-Up

Serial Port 2

IEEE 1284

Wake-Up

Parallel Port

Ports

Keyboard

& Mouse I/F

SCL

ACCESS.bus

Floppy Disk

Controller

Floppy Drive

Interface

Keyboard &

Serial Infrared

Interface Interface

Control

Events

Bus

Interface

LPC

Interface

I/O

2 Control

WATCHDOG

Timer

WDO

PWUREQ

Serial Port 1

Serial

Interface

Outputs

Fan Speed

Control & Monitor

Interface

Mouse Controller

with IR

GPIO Ports

2 Monitor

Inputs

SDA

Serial IRQ

Parallel

IRQs

Interrupt

Parallel Port

Interface

SMI

Ports

Serializer

BAT

PRELIMINARY

January 10, 1999

PC87360 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support

ACCESS.bus® is a registered trademark of Digital Equipment Corporation. I2C® is a registered trademark of Philips Corporation. IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation. Microsoft® and Windows® are registered trademarks of Microsoft Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. WATCHDOG‰ is a trademark of National Semiconductor Corporation. SMBus® is a registered trademark of Intel Corporation.

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Features

• LPC System Interface

— Synchronous cycles, up to 33 MHz bus clock — 8-bit I/O cycles — Up to four DMA channels — 8-bit DMA cycles — Basic read, write and DMA bus cycles are 13 clock

cycles long

• Protection

— Access lock to I/O ports (

XLOCK)

— GPIO lock — Pin conﬁguration lock

• 45 General-Purpose I/O (GPIO) Ports

— 37 standard, with Assert IRQ/

SMI/PWUREQ for 23

ports

— 8 V

-powered

— Programmable drive type for each output pin (open-

drain, push-pull or output disable)

— Programmable option for internal pull-up resistor on

each input pin

— Output lock option — Input debounce mechanism

• PC99 and ACPI Compliant

— PnP Conﬁguration Register structure — Flexible resource allocation for all logical devices

❏ Relocatable base address ❏ 15 IRQ routing options ❏ 4 optional 8-bit DMA channels(where applicable)

• Fan Speed Control and Fan Speed Monitor (FSCM)

— Supports different fan types — Speed monitoring for two fans

❏ Digital ﬁltering of the tachometer input signal ❏ Alarm for fan slower than programmable thresh-

old speed

❏ Alarm for fan stop

— TwospeedcontrollineswithPulse Width Modulation

(PWM)

❏ Output signal in the range of 6 Hz to 93.75 KHz ❏ Duty cycle resolution of 1/256

• Interrupt Serializer

— 11 Parallel IRQs to Serial IRQ

• Floppy Disk Controller (FDC)

— Programmable write protect — FM and MFM mode support — Enhanced mode command for three-mode Floppy

Disk Drive (FDD) support

— Perpendicular recording drive support for 2.88 MB — Burst and non-burst modes — Full support for IBM Tape Drive register (TDR) im-

plementation of AT and PS/2 drive types

— 16-byte FIFO

— Software compatible with the PC8477, which con-

tains a superset of the FDC functions in the microDP8473, the NEC microPD765A and the N82077

— High-performance, digital separator — Standard 5.25” and 3.5” FDD support

• Parallel Port

— Software or hardware control — Enhanced Parallel Port (EPP) compatible with new

version EPP 1.9 and IEEE 1284 compliant

— EPP support for versionEPP1.7of the Xircom spec-

iﬁcation

— EPP support as mode 4oftheExtendedCapabilities

Port (ECP)

— IEEE 1284 compliant ECP, including level 2 — Selection of internal pull-up or pull-down resistor for

Paper End (PE) pin

— PCI bus utilization reduction by supporting a de-

mand DMA mode mechanism and a DMA fairness mechanism

— Protection circuit that prevents damage to the paral-

lel port when a printer connected to it powers up or is operated at high voltages, even if the device is in power-down

— Output buffers that can sink and source 14 mA

• Serial Port 1 (UART1)

— Software compatible with the 16550A and the 16450 — Shadow register support for write-only bitmonitoring — UART data rates up to 1.5 Mbaud

• Serial Port 2 with Infrared (UART2)

— Software compatible with the 16550A and the 16450 — Shadow register support for write-only bitmonitoring — UART data rates up to 1.5 Mbaud — HP-SIR — ASK-IR option of SHARP-IR — DASK-IR option of SHARP-IR — Consumer Remote Control supports RC-5, RC-6,

NEC, RCA and RECS 80

— Non-standard DMA support − 1 or 2 channels — PnP dongle support

• Keyboard and Mouse Controller (KBC)

— 8-bit microcontroller — Software compatible with the 8042AH and PC87911

microcontrollers

— 2 KB custom-designed program ROM — 256 bytes RAM for data — Five programmable dedicated open-drain I/O lines — Asynchronous access to two data registers and one

status register during normal operation

— Support for both interrupt and polling — 93 instructions — 8-bit timer/counter — Support for binary and BCD arithmetic — Operation at 8MHz,12MHzor16 MHz (programma-

ble option)

Features (Continued)

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— Can be customized by using the PC87323, which in-

cludes a RAM-based KBC as a development platform for KBC code

• ACCESS.bus Interface (ACB)

— Serial interface compatible with SMbusph ysicalla yer — Compatible with Philips’ I2C

— ACB master and slave — Supports polling and interrupt controlled operation — Optional internal pull-up on SDA and SCL pins

• WATCHDOG Timer

— Times out the system based on user-programmable

time-out period

— System power-down capability for power saving — User-deﬁned trigger events to restart WATCHDOG — Optional routing of WATCHDOG output on IRQ

and/or SMI lines

• System Wake-Up Control (SWC)

— Power-up request upon detection of Keyboard,

Mouse, RI1, RI2, RING activity and General-Purpose Input Events, as follows:

❏ Preprogrammed Keyboard or Mouse sequence ❏ External modem ring on serial port ❏ Ring pulse or pulse train on the RING input signal ❏ Preprogrammed CEIR address in a preselected

standard (NEC, RCA or RC-5)

❏ General-Purpose Input Events ❏ IRQs of internal logical devices

— Optional routing of power-up request on IRQ and/or

SMI lines

— Battery-backed event conﬁguration — Programmable VSB-powered output for blinking

LEDs (LED1, LED2) control

• Clock Sources

— 48 MHz clock input — LPC clock, up to 33 MHz — On-chip low frequency clock generator for wake-up

• Power Supplies

— 3.3V supply operation — Main (V

)

— Standby (V

)

— Battery backup (V

BAT

)

— All pins are 5V tolerant and back-driveprotected,ex-

cept LPC bus pins

• Strap Configuration

— Base Address (BADDR) strap to determine the base

address of the Index-Data register pair

— Test strap to force the device into test mode (re-

served for National Semiconductor use)

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Datasheet Revision Record

Revision Date Status Comments

December 1998 Draft 1.0 Specifcations subject to change without notice January 1999 Preliminary 1.0 Speciﬁcation subject to change without notice; Power

Supply Control and LED sections in Chapter 2 are incomplete

Item Topic Change/Correction Location

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Table of Contents

Datasheet Revision Record....................................................................................................................4

1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM .........................................................................................................12

1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY ....................................................................13

1.3 PIN MULTIPLEXING .................................................................................................................17

1.4 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................19

1.4.1 ACCESS.bus Interface (ACB) ....................................................................................19

1.4.2 Bus Interface ...............................................................................................................19

1.4.3 Clock ............................................................................................................................19

1.4.4 Fan Speed Control and Monitor (FSCM) .....................................................................19

1.4.5 Floppy Disk Controller (FDC) ......................................................................................20

1.4.6 General-Purpose Input/Output (GPIO) Ports ...............................................................21

1.4.7 Infrared (IR) .................................................................................................................21

1.4.8 Keyboard and Mouse Controller (KBC) .....................................................................22

1.4.9 Parallel Port ...............................................................................................................22

1.4.10 Power and Ground .....................................................................................................23

1.4.11 Protection ....................................................................................................................24

1.4.12 Serial Port 1 and Serial Port 2 .....................................................................................24

1.4.13 Strap Configuration ......................................................................................................25

1.4.14 System Wake-Up Control ............................................................................................25

1.4.15 WATCHDOG Timer (WDT) .........................................................................................25

1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................26

2.0 Device Architecture and Configuration

2.1 OVERVIEW ...............................................................................................................................29

2.2 CONFIGURATION STRUCTURE AND ACCESS .....................................................................29

2.2.1 The Index-Data Register Pair ......................................................................................29

2.2.2 Banked Logical Device Registers Structure ................................................................31

2.2.3 Standard Logical Device Configuration Register Definitions .......................................32

2.2.4 Standard Configuration Registers ...............................................................................34

SuperI/O Control and Configuration Registers ............................................................34

Logical Device Control and Configuration Registers ...................................................34

Control .........................................................................................................................35

Standard Configuration ................................................................................................35

Special Configuration ..................................................................................................35

2.2.5 Default Configuration Setup ........................................................................................35

2.2.6 Power States ...............................................................................................................35

2.2.7 Address Decoding .......................................................................................................36

2.3 INTERRUPT SERIALIZER ........................................................................................................36

2.4 PROTECTION ...........................................................................................................................37

2.4.1 Access Lock to I/O Ports .............................................................................................37

2.4.2 Pin Configuration Lock ................................................................................................37

2.4.3 GPIO Pin Function Lock ..............................................................................................37

Table of Contents (Continued)

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2.5 LED OPERATION AND STATES ..............................................................................................38

2.6 REGISTER TYPE ABBREVIATIONS ........................................................................................38

2.7 SUPERI/O CONFIGURATION REGISTERS .............................................................................38

2.7.1 SuperI/O ID Register (SID) ..........................................................................................40

2.7.2 SuperI/O Configuration 1 Register (SIOCF1) ..............................................................40

2.7.3 SuperI/O Configuration 2 Register (SIOCF2) ..............................................................41

2.7.4 SuperI/O Configuration 3 Register (SIOCF3) ..............................................................42

2.7.5 SuperI/O Configuration 4 Register (SIOCF4) ..............................................................43

2.7.6 SuperI/O Configuration 5 Register (SIOCF5) ..............................................................44

2.7.7 SuperI/O Configuration 6 Register (SIOCF6) ..............................................................45

2.7.8 SuperI/O Revision ID Register (SRID) ........................................................................45

2.7.9 SuperI/O Configuration 8 Register (SIOCF8) ..............................................................46

2.7.10 SuperI/O Configuration A Register (SIOCFA) .............................................................47

2.7.11 SuperI/O Configuration B Register (SIOCFB) .............................................................48

2.7.12 SuperI/O Configuration C Register (SIOCFC) .............................................................49

2.7.13 SuperI/O Configuration D Register (SIOCFD) .............................................................50

2.8 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................51

2.8.1 General Description .....................................................................................................51

2.8.2 Logical Device 0 (FDC) Configuration .........................................................................51

2.8.3 FDC Configuration Register ........................................................................................52

2.8.4 Drive ID Register .........................................................................................................53

2.9 PARALLEL PORT CONFIGURATION ......................................................................................54

2.9.1 General Description .....................................................................................................54

2.9.2 Logical Device 1 (PP) Configuration ............................................................................55

2.9.3 Parallel Port Configuration Register ............................................................................55

2.10 SERIAL PORT 2 CONFIGURATION .........................................................................................56

2.10.1 General Description .....................................................................................................56

2.10.2 Logical Device 2 (SP2) Configuration ..........................................................................56

2.10.3 Serial Port 2 Configuration Register ............................................................................56

2.11 SERIAL PORT 1 CONFIGURATION .........................................................................................57

2.11.1 Logical Device 3 (SP1) Configuration ..........................................................................57

2.11.2 Serial Port 1 Configuration Register ............................................................................57

2.12 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION .....................................................58

2.12.1 Logical Device 4 (SWC) Configuration ........................................................................58

2.13 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION .....................................59

2.13.1 General Description .....................................................................................................59

2.13.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration ..................................60

2.13.3 KBC Configuration Register ........................................................................................61

2.14 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION ..........................62

2.14.1 General Description .....................................................................................................62

2.14.2 Implementation ............................................................................................................62

2.14.3 Logical Device 7 (GPIO) Configuration .......................................................................63

2.14.4 GPIO Pin Select Register ............................................................................................64

2.14.5 GPIO Pin Configuration Register .................................................................................65

2.14.6 GPIO Event Routing Register ......................................................................................66

Table of Contents (Continued)

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2.15 ACCESS.BUS INTERFACE (ACB) CONFIGURATION ............................................................67

2.15.1 General Description .....................................................................................................67

2.15.2 Logical Device 8 (ACB) Configuration .........................................................................67

2.15.3 ACB Configuration Register ........................................................................................68

2.16 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION .....................................69

2.16.1 General Description .....................................................................................................69

2.16.2 Logical Device 9 (FSCM) Configuration ......................................................................69

2.16.3 Fan Speed Control and Monitor Configuration 1 Register ...........................................70

2.17 WATCHDOG TIMER (WDT) CONFIGURATION ......................................................................71

2.17.1 Logical Device 10 (WDT) Configuration ......................................................................71

2.17.2 WATCHDOG Timer Configuration Register ................................................................71

3.0 System Wake-Up Control (SWC)

3.1 OVERVIEW ...............................................................................................................................72

3.2 FUNCTIONAL DESCRIPTION ..................................................................................................72

3.3 EVENT DETECTION .................................................................................................................74

3.3.1 Modem Ring ................................................................................................................74

3.3.2 Telephone Ring ...........................................................................................................74

3.3.3 Keyboard and Mouse Activity ......................................................................................74

3.3.4 CEIR Address ..............................................................................................................75

3.3.5 Standby General-Purpose Input Events ......................................................................75

3.3.6 GPIO-Triggered Events ...............................................................................................75

3.3.7 Software Event ............................................................................................................75

3.3.8 Module IRQ Wake-Up Event .......................................................................................75

3.4 SWC REGISTERS .....................................................................................................................76

3.4.1 SWC Register Map ......................................................................................................76

3.4.2 Wake-Up Events Status Register 0 (WK_STS0) .........................................................78

3.4.3 Wake-Up Events Status Register (WK_STS1) ............................................................79

3.4.4 Wake-Up Events Enable Register (WK_EN0) .............................................................80

3.4.5 Wake-Up Events Enable Register 1 (WK_EN1) ..........................................................81

3.4.6 Wake-Up Configuration Register (WK_CFG) ..............................................................82

3.4.7 Wake-Up Events Routing to SMI Enable Register 0 (WK_SMIEN0) ...........................83

3.4.8 Wake-Up Events Routing to SMI Enable Register 1 (WK_SMIEN1) ...........................84

3.4.9 Wake-Up Events Routing to IRQ Enable Register 0 (WK_IRQEN0) ...........................85

3.4.10 Wake-Up Events Routing to IRQ Enable Register 1 (WK_IRQEN1) ...........................86

3.4.11 Wake-Up Extension 1 Enable Register 0 (WK_X1EN0) ..............................................87

3.4.12 Wake-Up Extension 1 Enable Register 1 (WK_X1EN1) ..............................................88

3.4.13 Wake-Up Extension 2 Enable Register 0 (WK_X2EN0) ..............................................89

3.4.14 Wake-Up Extension 2 Enable Register 1 (WK_X2EN1) ..............................................90

3.4.15 PS/2 Keyboard and Mouse Wake-Up Events ..............................................................91

Keyboard Wake-Up Events .........................................................................................91

Mouse Wake-Up Events ..............................................................................................91

3.4.16 PS/2 Protocol Control Register (PS2CTL) ...................................................................92

3.4.17 Keyboard Data Shift Register (KDSR) .........................................................................92

3.4.18 Mouse Data Shift Register (MDSR) .............................................................................93

3.4.19 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) ......................................93

Table of Contents (Continued)

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3.4.20 CEIR Wake-Up Control Register (IRWCR) .................................................................94

3.4.21 CEIR Wake-Up Address Register (IRWAD) ................................................................95

3.4.22 CEIR Wake-Up Address Mask Register (IRWAM) ......................................................95

3.4.23 CEIR Address Shift Register (ADSR) ..........................................................................96

3.4.24 CEIR Wake-Up Range 0 Registers .............................................................................96

IRWTR0L Register ......................................................................................................96

IRWTR0H Register ......................................................................................................96

3.4.25 CEIR Wake-Up Range 1 Registers .............................................................................97

IRWTR1L Register ......................................................................................................97

IRWTR1H Register ......................................................................................................97

3.4.26 CEIR Wake-Up Range 2 Registers .............................................................................97

IRWTR2L Register ......................................................................................................97

IRWTR2H Register ......................................................................................................97

3.4.27 CEIR Wake-Up Range 3 Registers .............................................................................98

IRWTR3L Register ......................................................................................................98

IRWTR3H Register ......................................................................................................98

CEIR Recommended Values .......................................................................................98

3.4.28 Standby General-Purpose I/O (SBGPIO) Register Overview ......................................99

Basic Functionality .....................................................................................................100

Configuration Options ................................................................................................101

Operation ...................................................................................................................101

Event Detection .........................................................................................................101

Event Configuration ...................................................................................................102

3.4.29 Standby GPIO Pin Select Register (SBGPSEL) ........................................................102

3.4.30 Standby GPIO Pin Configuration Register (SBGPCFG) ...........................................103

3.4.31 Standby GPIOE/GPIE Data Out Register 0 (SB_GPDO0) ........................................104

3.4.32 Standby GPIOE/GPIE Data In Register 0 (SB_GPDI0) ............................................104

3.5 SWC REGISTER BITMAP .......................................................................................................105

4.0 Fan Speed Control

4.1 OVERVIEW .............................................................................................................................108

4.2 FUNCTIONAL DESCRIPTION ................................................................................................108

4.3 FAN SPEED CONTROL REGISTERS ....................................................................................109

4.3.1 Fan Speed Control Register Map ..............................................................................109

4.3.2 Fan Speed Control Pre-Scale Register (FCPSR) ......................................................109

4.3.3 Fan Speed Control Duty Cycle Register (FCDCR) ....................................................110

4.4 FAN SPEED CONTROL BITMAP ...........................................................................................110

5.0 Fan Speed Monitor

5.1 OVERVIEW .............................................................................................................................111

5.2 FUNCTIONAL DESCRIPTION ................................................................................................111

5.3 FAN SPEED MONITOR REGISTERS .....................................................................................112

5.3.1 Fan Speed Monitor Register Map ..............................................................................112

5.3.2 Fan Monitor Threshold Register (FMTHR) ................................................................113

5.3.3 Fan Monitor Speed Register (FMSPR) ......................................................................113

5.3.4 Fan Monitor Control and Status Register (FMCSR) ..................................................113

Table of Contents (Continued)

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5.4 FAN SPEED MONITOR BITMAP ............................................................................................114

6.0 General-Purpose Input/Output (GPIO) Port

6.1 OVERVIEW .............................................................................................................................115

6.2 BASIC FUNCTIONALITY ........................................................................................................116

6.2.1 Configuration Options ................................................................................................116

6.2.2 Operation ...................................................................................................................116

6.3 EVENT HANDLING AND SYSTEM NOTIFICATION ..............................................................117

6.3.1 Event Configuration ...................................................................................................117

Event Type and Polarity ............................................................................................117

Event Debounce Enable ............................................................................................117

6.3.2 System Notification ....................................................................................................117

6.4 GPIO PORT REGISTERS .......................................................................................................118

6.4.1 GPIO Pin Configuration (GPCFG) Register ..............................................................119

6.4.2 GPIO Pin Event Routing (GPEVR) Register .............................................................120

6.4.3 GPIO Port Runtime Register Map .............................................................................120

6.4.4 GPIO Data Out Register (GPDO) ..............................................................................121

6.4.5 GPIO Data In Register (GPDI) ..................................................................................121

6.4.6 GPIO Event Enable Register (GPEVEN) ..................................................................122

6.4.7 GPIO Event Status Register (GPEVST) ....................................................................122

7.0 WATCHDOG Timer (WDT)

7.1 OVERVIEW .............................................................................................................................123

7.2 FUNCTIONAL DESCRIPTION ................................................................................................123

7.3 WATCHDOG TIMER REGISTERS .........................................................................................124

7.3.1 WATCHDOG Timer Register Map .............................................................................124

7.3.2 WATCHDOG Timeout Register (WDTO) ..................................................................124

7.3.3 WATCHDOG Mask Register (WDMSK) ....................................................................125

7.3.4 WATCHDOG Status Register (WDST) ......................................................................126

7.4 WATCHDOG TIMER REGISTER BITMAP .............................................................................126

8.0 ACCESS.bus Interface (ACB)

8.1 OVERVIEW .............................................................................................................................127

8.2 FUNCTIONAL DESCRIPTION ................................................................................................127

8.2.1 Data Transactions .....................................................................................................127

8.2.2 Start and Stop Conditions ..........................................................................................127

8.2.3 Acknowledge (ACK) Cycle ........................................................................................128

8.2.4 Acknowledge after Every Byte Rule ..........................................................................129

8.2.5 Addressing Transfer Formats ....................................................................................129

8.2.6 Arbitration on the Bus ................................................................................................129

8.2.7 Master Mode ..............................................................................................................130

Requesting Bus Mastership .......................................................................................130

Sending the Address Byte .........................................................................................130

Master Transmit .........................................................................................................130

Master Receive ..........................................................................................................131

Master Stop ...............................................................................................................131

Table of Contents (Continued)

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Master Bus Stall ........................................................................................................131

Repeated Start ..........................................................................................................131

Master Error Detection ..............................................................................................131

Bus Idle Error Recovery ............................................................................................131

8.2.8 Slave Mode ................................................................................................................132

Slave Receive and Transmit ......................................................................................132

Slave Bus Stall ..........................................................................................................132

Slave Error Detection ................................................................................................132

8.2.9 Configuration .............................................................................................................132

SDA and SCL Signals ...............................................................................................132

ACB Clock Frequency ...............................................................................................132

8.3 ACB REGISTERS ....................................................................................................................133

8.3.1 ACB Register Map .....................................................................................................133

8.3.2 ACB Serial Data Register (ACBSDA) ........................................................................133

8.3.3 ACB Status Register (ACBST) ..................................................................................134

8.3.4 ACB Control Status Register (ACBCST) ...................................................................135

8.3.5 ACB Control Register 1 (ACBCTL1) ..........................................................................136

8.3.6 ACB Own Address Register (ACBADDR) .................................................................137

8.3.7 ACB Control Register 2 (ACBCTL2) ..........................................................................137

8.4 ACB REGISTER BITMAP ........................................................................................................138

9.0 Legacy Functional Blocks

9.1 KEYBOARD AND MOUSE CONTROLLER (KBC) ..................................................................140

9.1.1 General Description ...................................................................................................140

9.1.2 KBC Register Map .....................................................................................................140

9.1.3 KBC Bitmap Summary ...............................................................................................140

9.2 FLOPPY DISK CONTROLLER (FDC) .....................................................................................141

9.2.1 General Description ...................................................................................................141

9.2.2 FDC Register Map .....................................................................................................141

9.2.3 FDC Bitmap Summary ...............................................................................................142

9.3 PARALLEL PORT ....................................................................................................................143

9.3.1 General Description ...................................................................................................143

9.3.2 Parallel Port Register Map .........................................................................................143

9.3.3 Parallel Port Bitmap Summary ..................................................................................144

9.4 UART FUNCTIONALITY (SP1 AND SP2) ...............................................................................146

9.4.1 General Description ...................................................................................................146

9.4.2 UART Mode Register Bank Overview .......................................................................146

9.4.3 SP1 and SP2 Register Maps for UART Functionality ................................................147

9.4.4 SP1 and SP2 Bitmap Summary for UART Functionality ...........................................149

9.5 IR FUNCTIONALITY (SP2) .....................................................................................................151

9.5.1 General Description ...................................................................................................151

9.5.2 IR Mode Register Bank Overview .............................................................................151

9.5.3 SP2 Register Map for IR Functionality ......................................................................152

9.5.4 SP2 Bitmap Summary for IR Functionality ................................................................153

Table of Contents (Continued)

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10.0 Device Characteristics

10.1 GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................155

10.1.1 Recommended Operating Conditions .......................................................................155

10.1.2 Absolute Maximum Ratings .......................................................................................155

10.1.3 Capacitance ..............................................................................................................155

10.1.4 Power Consumption under Recommended Operating Conditions ............................156

10.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ................................................156

10.2.1 Input, CMOS Compatible ...........................................................................................156

10.2.2 Input, PCI 3.3V ..........................................................................................................156

10.2.3 Input, SMBus Compatible ..........................................................................................157

10.2.4 Input, Strap Pin ..........................................................................................................157

10.2.5 Input, TTL Compatible ...............................................................................................157

10.2.6 Input, TTL Compatible with Schmitt Trigger ..............................................................157

10.2.7 Output, PCI 3.3V .......................................................................................................158

10.2.8 Output, Totem-Pole Buffer .........................................................................................158

10.2.9 Output, Open-Drain Buffer .........................................................................................158

10.2.10 Exceptions .................................................................................................................158

10.3 INTERNAL RESISTORS .........................................................................................................159

10.3.1 Pull-Up Resistor .........................................................................................................159

10.3.2 Pull-Down Resistor ....................................................................................................159

10.4 AC ELECTRICAL CHARACTERISTICS ..................................................................................160

10.4.1 AC Test Conditions ....................................................................................................160

10.4.2 Clock Timing ..............................................................................................................160

10.4.3 LCLK and LRESET ....................................................................................................161

10.4.4 LPC and SERIRQ Signals .........................................................................................162

10.4.5 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing ...........................163

10.4.6 Modem Control Timing ..............................................................................................164

10.4.7 FDC Write Data Timing .............................................................................................164

10.4.8 FDC Drive Control Timing .........................................................................................165

10.4.9 FDC Read Data Timing .............................................................................................165

10.4.10 Standard Parallel Port Timing ....................................................................................166

10.4.11 Enhanced Parallel Port Timing ..................................................................................166

10.4.12 Extended Capabilities Port (ECP) Timing ..................................................................167

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1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM

Plastic Quad Flatpack (PQFP), JEDEC

xxx =Three character identiﬁer for National data, and keyboard ROM and/or customer identiﬁcation code

Order Number PC87360-xxx/VLA

See NS Package Number VLA128A

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

59585756555453525150494847464544424140

PC87360-xxx/VLA

PD7

VSS

VBAT

MTR0

SLCT

DIR

STEP

WDATA

DRATE0

TRK0

WGATE

RDATA

DENSEL

INDEX

GPIO17/

DR1/IRSL3

636261

65 66 67

68 69 70

71 72

73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101 102

103

104

105

106

107

108

GPIO43

GPIO42

VDD

VSB

PWUREQ

GPIO16/

MTR1/IRSL2

DR0

GPIO34

GPIO01/FANOUT1

GPIO47

GPIO46

GPIO45

BUSY_WAIT

HDSEL

DSKCHG

GPIO44

ACK

ERR

AFD_DSTRB

PD1

STB_WRITE

INIT

PD6 PD5

PD4 PD3

SLIN_ASTRB

PD2

VSS

PD0

GPIO00/FANIN1

GPIO33

VDD

VSS

VDD

VSS

VDD

Note 1.

GPIOE1

GPIOE2/LED1

LAD1

LAD3 LAD2

LRESET

LCLK

LFRAME

LAD0

LDRQ SERIRQ

GPIO32/PIRQ15/P16/IRSL1

DTR1_BOUT1/BADDR

RI1

DCD1

SOUT1

DSR1

SIN1

RTS1/TEST

CTS1

DTR2_BOUT2

RI2

DCD2

SOUT2

DSR2

SIN2

RTS2

CTS2

GPIO13/SDA

GPIO14/WDO

KBDAT

KBCLK

MCLK

MDAT

KBRST/GPIO06

GA20/GPIO07

GPIO41

GPIOE3/LED2

GPIOE5

GPIO03/FANOUT0 GPIO02/FANIN0

GPIE6/IRRX2_IRSL0

GPIE7/IRRX1

GPO15/IRTX

GPIO10/SMI

GPIOE4/

RING

GPIO05/P17 GPIO04/P12

GPIO11/XLOCK

GPIO12/SCL

CLKIN

GPIOE0

GPIO40

NC NC

NCNCNC

GPIO27/PIRQ11

GPIO25/PIRQ9

GPIO26/PIRQ10

GPIO24/PIRQ7

GPIO23/PIRQ6

GPIO21/PIRQ4

GPIO22/PIRQ5

GPIO20/PIRQ3

GPIO30/PIRQ12

GPIO31/PIRQ14

Note 1. For correct operation, this pin must be tied to VSS.

1.0 Signal/Pin Connection and Description (Continued)

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1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY

Table 2 is an alphabetical list of all signals, cross-referenced to additional information for detailed functional descriptions, electrical DC characteristics, and pin multiplexing. The signal DC characteristics are denoted by a buffer type symbol, described briefly below and in further detail in Section 10.2. The pin multiplexing information refers to two different types of multiplexing:

●

MUX - Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two different functions. Each function is associated with different board connectivity, and normally, the function selection is determined by the board design and cannot be changed dynamically. The multiplexing options must be conﬁgured by the BIOS upon power-up, in order to comply with the board implementation.

●

MM - Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or more modes of operation within the same function. These modes are associated with the same external (board) connectivity. Mode selection may be controlled by the device driver, through the registers of the functional block, and do not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O conﬁguration perspective. The mode selection method (registers and bits) as well as the signal speciﬁcation in each mode, are described within the functional description of the relevant functional block.

Table 2. SIgnal/Pin Directory

Table 1. Buffer Types

Symbol Description

Input, CMOS compatible

PCI

Input, PCI 3.3V

Input, SMBus compatible

STRP

Input, Strap pin with weak pull-down during strap time

Input, TTL compatible

Input, TTL compatible with Schmidt Trigger

ULR

Input, with serial UL Resistor

PCI

Output, PCI 3.3V

p/n

Output, push-pull buffer that is capable of sourcingpmA and sinkingn mA

Output, open-drain output buffer that is capable of sinkingn mA PWR Power pin GND Ground pin

Signal Pin(s)

Functional Group DC Characteristics

MUX

Name Section Buffer Type Section

ACK 79 Parallel Port 1.4.9

10.2.5

AFD_DSTRB 93 Parallel Port 1.4.9

14,O14/14

10.2.9, 10.2.8 MM ASTRB See SLIN_ASTRB BADDR 101 Strap Conﬁguration 1.4.13

STRP

10.2.4 MUX BOUT1 See

DTR1_BOUT1

BOUT2 See

DTR2_BOUT2

BUSY_

WAIT 78 Parallel Port 1.4.9

10.2.5 MM CLKIN 22 Clock 1.4.3

10.2.5 CTS1 100 Serial Port 1 1.4.12

10.2.6

1.0 Signal/Pin Connection and Description (Continued)

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CTS2 108 Serial Port 2 1.4.12

10.2.6 DCD1 95 Serial Port 1 1.4.12

10.2.6 DCD2 103 Serial Port 2 1.4.12

10.2.6 DENSEL 75 FDC 1.4.5

2/12

10.2.8 DIR 68 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8 DR0 70 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8 DR1 71 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8 MUX DRATE0 74 FDC 1.4.5

3/6

10.2.8 DSKCHG 60 FDC 1.4.5

10.2.5 DSR1 96 Serial Port 1 1.4.12

10.2.6 DSR2 104 Serial Port 2 1.4.12

10.2.6 DSTRB See AFD_DSTRB DTR1_BOUT1 101 Serial Port 1 1.4.12

3/6

10.2.8 MUX, MM DTR2_BOUT2 109 Serial Port 2 1.4.12

3/6

10.2.8 MUX, MM ERR 91 Parallel Port 1.4.9

10.2.5 FANIN0 4 Fan Speed 1.4.4

10.2.6 MUX FANIN1 2 Fan Speed 1.4.4

10.2.6 MUX FANOUT0 5 Fan Speed 1.4.4

2/14

10.2.8 MUX FANOUT1 3 Fan Speed 1.4.4

2/14

10.2.8 MUX GA20 (P21) 9 KBC 1.4.8

,OD

10.2.5, 10.2.9 MUX GPIE6-7 58-59 System Wake-Up 1.4.14

10.2.6 MUX GPIO00-07 2-9 GPIO Port 1.4.6

,OD6,O

3/6

10.2.6, 10.2.9, 10.2.8 MUX GPIO10

GPIO11-14 GPO15 GPIO16-17

21 53-56 57 69, 71

GPIO Port 1.4.6

,OD6,O

3/6

10.2.6, 10.2.9, 10.2.8 MUX

GPIO20-27 117-124 GPIO Port 1.4.6

,OD6,O

3/6

10.2.6, 10.2.9, 10.2.8 MUX GPIO30-33

GPIO34

125-128 1

GPIO Port 1.4.6

,OD6,O

3/6

10.2.6, 10.2.9, 10.2.8 MUX

GPIO40-47 43-50 GPIO Port 1.4.6

,OD6,O

3/6

10.2.6, 10.2.9, 10.2.8 GPIOE0-5 23-28 System Wake-Up 1.4.14

,OD6,O

3/6

10.2.6, 10.2.9, 10.2.8 HDSEL 61 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8 INDEX 73 FDC 1.4.5

10.2.5 INIT 89 Parallel Port 1.4.9

14,O14/14

10.2.9, 10.2.8 IRRX1 59 Infrared 1.4.7

10.2.6

MUX

IRRX2_IRSL0 58 Infrared 1.4.7

TS,O3/6

10.2.6, 10.2.8

MUX, MM

Signal Pin(s)

Functional Group DC Characteristics

MUX

Name Section Buffer Type Section

1.0 Signal/Pin Connection and Description (Continued)

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IRSL1 127 Infrared 1.4.7

T,O3/6

10.2.5, 10.2.8 MUX IRSL2 69 Infrared 1.4.7

INT,O

3/6

10.2.5, 10.2.8

MUX

IRSL3 71 Infrared 1.4.7

10.2.5

MUX

IRTX 57 Infrared 1.4.7

6/12

10.2.8

MUX

KBCLK 111 KBC 1.4.8

INTS,OD

10.2.6, 10.2.9 KBDAT 112 KBC 1.4.8

,OD

10.2.6, 10.2.9 KBRST (P20) 8 KBC 1.4.8

INTS,OD

10.2.6, 10.2.9

MUX

LAD0-3 15-18 Bus Interface 1.4.2

PCI,OPCI

10.2.2, 10.2.7 LED1, LED2 25, 26 System Wake-Up 1.4.14

12/12

10.2.8

MUX

LCLK 11 Bus Interface 1.4.2

PCI

10.2.2 LDRQ 13 Bus Interface 1.4.2

PCI

10.2.7 LFRAME 14 Bus Interface 1.4.2

PCI

10.2.2 LRESET 10 Bus Interface 1.4.2

PCI

10.2.2 MCLK 13 KBC 1.4.8

,OD

10.2.6, 10.2.9 MDAT 114 KBC 1.4.8

,OD

10.2.6, 10.2.9 MTR0 72 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8 MTR1 69 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8

MUX

P12, P16, P17 6,127, 7 KBC 1.4.8

,OD

10.2.5, 10.2.9

MUX

PD7-5 PD4-3, PD2, PD1 PD0

80-82 85-86 88, 90 92

Parallel Port 1.4.9

,OD14,O

14/14

10.2.5, 10.2.9, 10.2.8

PE 77 Parallel Port 1.4.9

10.2.5 PIRQ3-7

PIRQ9-12 PIRQ14-15

117-121 122-125 126-127

Bus Interface 1.4.2

10.2.6 MUX

PWUREQ 32 System Wake-Up 1.4.14

10.2.9 RDATA 62 FDC 1.4.5

10.2.5 RI1 102 Serial Port 1 1.4.12

10.2.6 RI2 110 Serial Port 2 1.4.12

10.2.6 RING 27 System Wake-Up 1.4.14

10.2.6

MUX

RTS1 98 Serial Port 1 1.4.12

3/6

10.2.8

MUX

RTS2 106 Serial Port 2 1.4.12

3/6

10.2.8 SCL 54 ACB 1.4.1

,OD6,O

3/6

10.2.5, 10.2.9, 10.2.8

MUX

SDA 55 ACB 1.4.1

,OD6,O

3/6

10.2.5, 10.2.9, 10.2.8

MUX

SERIRQ 12 Bus Interface 1.4.2

PCI,OPCI

10.2.2, 10.2.7

Signal Pin(s)

Functional Group DC Characteristics

MUX

Name Section Buffer Type Section

1.0 Signal/Pin Connection and Description (Continued)

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SIN1 97 Serial Port 1 1.4.12

10.2.6 SIN2 105 Serial Port 2 1.4.12

10.2.6 SLCT 76 Parallel Port 1.4.9

10.2.5 SLIN_ASTRB 87 Parallel Port 1.4.9

14,O14/14

10.2.9, 10.2.8

SMI 21 Bus Interface 1.4.2

10.2.9

MUX

SOUT1 99 Serial Port 1 1.4.12

3/6

10.2.8

MUX

SOUT2 107 Serial Port 2 1.4.12

3/6

10.2.8 STEP 67 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8 STB_WRITE 94 Parallel Port 1.4.9

14,O14/14

10.2.9, 10.2.8

TEST 98 Strap Conﬁguration 1.4.13

STRP

10.2.4

MUX

TRK0 64 FDC 1.4.5

10.2.5 V

BAT

30 Power and Ground 1.4.10

ULR

N/A

20, 52, 83, 115 Power and Ground 1.4.10 PWR N/A

31 Power and Ground 1.4.10 PWR N/A

19, 51, 84, 116 Power and Ground 1.4.10 GND N/A WAIT See BUSY_WAIT WDATA 66 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8

WDO 56 WATCHDOG 1.4.15

6,O3/6

10.2.9, 10.2.8

MUX

WGATE 65 FDC 1.4.5

12,O2/12

10.2.9, 10.2.8

WP 63 FDC 1.4.5

10.2.5 WRITE See STB_WRITE XLOCK 53 Protection 1.4.11

10.2.5

MUX

Signal Pin(s)

Functional Group DC Characteristics

MUX

Name Section Buffer Type Section

1.0 Signal/Pin Connection and Description (Continued)

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1.3 PIN MULTIPLEXING

The multiplexing options and the associated setup configuration for all pins are described in Table 3. A multiplexing option can be chosen on one pin only per group.

Table 3. Pin Multiplexing Conﬁguration

Pin(s)

Default Alternate

Signal I/O Conﬁguration Signal I/O Conﬁguration

2 GPIO00 I/O SIOCF2, Bit 2 = 0 FANIN1 I SIOCF2, Bit 2 = 1 3 GPIO01 I/O SIOCF2, Bit 3 = 0 FANOUT1 O SIOCF2, Bit 3 = 1 4 GPIO02 I/O SIOCF2, Bit 4 = 0 FANIN0 I SIOCF2, Bit 4 = 1 5 GPIO03 I/O SIOCF2, Bit 5 = 0 FANOUT0 O SIOCF2, Bit 5 = 1 6 GPIO04 I/O SIOCF2, Bit 6 = 0 P12 I/O SIOCF2, Bit 6 = 1 7 GPIO05 I/O SIOCF2, Bit 7 = 0 P17 I/O SIOCF2, Bit 7 = 1 8 KBRST (P20) SIOCF3, Bit 0 = 1 GPIO06 I/O SIOCF3, Bit 0 = 0 9 GA20 (P21) SIOCF3, Bit 1 = 1 GPIO07 I/O SIOCF3, Bit 1 = 0 21 GPIO10 I/O SIOCF3, Bit 2 = 0

SMI O SIOCF3, Bit 2 = 1

25 GPIOE2 I/O

SIOCFA, Bits 2-1 = 00

LED1 O SIOCFA, Bits 2-1 = 01

26 GPIOE3 I/O SIOCFA, Bit 3 = 0 LED2 O SIOCFA, Bit 3 =1 27 GPIOE4 I/O SIOCFA, Bits 5-4 = 00 RING I SIOCFA, Bits 5-4 = 01 53 GPIO11 I/O SIOCF3, Bit 4 = 0

XLOCK I SIOCF3, Bit 4 = 1 54 GPIO12 I/O SIOCF3, Bit 5 = 0 SCL I/O SIOCF3, Bit 5 = 1 55 GPIO13 I/O SIOCF3, Bit 5 = 0 SDA I/O SIOCF3, Bit 5 = 1 56 GPIO14 I/O SIOCF3, Bit 6 = 0

WDO O SIOCF3, Bit 6 = 1 57 GPO15 O SIOCF3, Bit 7 = 0 IRTX O SIOCF3, Bit 7 = 1 58 GPIE6 I SIOCFB, Bit 0 = 0 IRRX2_IRSL0 I/O SIOCFB, Bit 0 = 1 59 GPIE7 I SIOCFB, Bit 1 = 0 IRRX1 I SIOCFB, Bit 1 = 1 69 GPIO16 I/O SIOCF4, Bits 1-0 = 00

MTR1 O SIOCF4, Bits 1-0 = 01

IRSL2 I/O SIOCF4, Bits 1-0 = 10 71 GPIO17 I/O SIOCF4, Bits 3-2 = 00

DR1 O SIOCF4, Bits 3-2 = 01

IRSL3 I SIOCF4, Bits 3-2 = 10 117 GPIO20 I/O

SIOCF4, Bits 4,P

Note 1.

=00

PIRQ3 I SIOCF4, Bits 4,P = X1 118 GPIO21 I/O

SIOCF4, Bits 4,P

Note 1.

=00

PIRQ4 i SIOCF4, Bits 4,P = X1 119 GPIO22 I/O

SIOCF4, Bits 4,P

Note 1.

=00

PIRQ5 I SIOCF4, Bits 4,P = X1 120 GPIO23 I/O

SIOCF4, Bits 4,P

Note 1.

=00

PIRQ6 I SIOCF4, Bits 4,P = X1 121 GPIO24 I/O

SIOCF4, Bits 4,P

Note 1.

=00

PIRQ7 I SIOCF4, Bits 4,P = X1 122 GPIO25 I/O

SIOCF4, Bits 4,P

Note 1.

=00

PIRQ9 I SIOCF4, Bits 4,P = X1 123 GPIO26 I/O

SIOCF4, Bits 4,P

Note 1.

=00

PIRQ10 I SIOCF4, Bits 4,P = X1 124 GPIO27 I/O

SIOCF4, Bits 4,P

Note 1.

=00

PIRQ11 I SIOCF4, Bits 4,P = X1 125 GPIO30 I/O

SIOCF4, Bits 5,P

Note 1.

=00

PIRQ12 I SIOCF4, Bits 5,P = X1 126 GPIO31 I/O

SIOCF4, Bits 5,P

Note 1.

=00

PIRQ14 I SIOCF4, Bits 5,P = X1

1.0 Signal/Pin Connection and Description (Continued)

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127 GPIO32 I/O

SIOCF4, Bits 7,6,P

Note 1.

= 000

P16 I/O

SIOCF4, Bits 7,6,P

Note 1.

= 010

IRSL1 I/O

SIOCF4, Bits 7,6,P

Note 1.

= 100

PIRQ15 I

SIOCF4, Bits 7,6,P

Note 1.

= XX1

Note 1. P = SIOCF1, Bit 6 (Pins 117-127 Select PIRQ)

Pin(s)

Default Alternate

Signal I/O Conﬁguration Signal I/O Conﬁguration

1.0 Signal/Pin Connection and Description (Continued)

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1.4 DETAILED SIGNAL/PIN DESCRIPTIONS

This section describes all signals, organized in functional groups.

1.4.1 ACCESS.bus Interface (ACB)

1.4.2 Bus Interface

1.4.3 Clock

1.4.4 Fan Speed Control and Monitor (FSCM)

Signal Pin(s) I/O Buffer Type Power Well Description

SCL 54 I/O

/OD

ACCESS.bus Clock Signal. An internal pull-up is optional, depending upon the ACCESS.bus conﬁguration register.

SDA 55 I/O

/OD

ACCESS.bus Data Signal. An internal pull-up is optional, depending upon the ACCESS.bus conﬁguration register.

Signal Pin(s) I/O Buffer Type Power Well Description

LAD0-3 15-18 I/O

PCI/OPCI

LPC Address-Data. Multiplexed command, address bidirectional data and cycle status.

LCLK 11 I

PCI

LPC Clock. Practically the PCI clock (up to 33 MHz)

LDRQ 13 O

PCI

LPC DMA Request. Encoded DMA request for LPC I/F.

LFRAME 14 I

PCI

LPC Frame. Low pulse indicates the beginning of new LPC cycle or termination of a broken cycle.

LRESET 10 I

PCI

LPC Reset. Practically the PCI system reset.

PIRQ3-7 PIRQ9-12 PIRQ14-15

117-121 122-125 126-127

Parallel Interrupt. Converts Parallel Port interrupts into Serial Interrupts by means of the Interrupt Serializer.

SERIRQ 12 I/O

PCI/OPCI

Serial IRQ. The interrupt requests are serialized over a single pin, where each internal IRQ signal is delivered during a designated time slot.

SMI 21 OD

System Management Interrupt

Signal Pin(s) I/O Buffer Type Power Well Description

CLKIN 22 I

Clock In. 48 MHz clock input.

Signal Pin(s) I/O Buffer Type Power Well Description

FANIN0 FANIN1

4 2I

Fan Inputs. Used to feed the fan’s tachometer pulse to the Fan Speed Monitor. The rising edge indicates the completion of a half (or full) revolution of the fan.

FANOUT0 FANOUT153O

2/14

Fan Outputs. Pulse Width Modulation (PWM) signals, used to control the speed of cooling fans by controlling the voltage supplied to the fan’s motor.

1.0 Signal/Pin Connection and Description (Continued)

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1.4.5 Floppy Disk Controller (FDC)

Signal Pin(s) I/O Buffer Type Power Well Description

DENSEL 75 O

2/12

Density Select. Indicates that a high FDC density data rate (500 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is selected.

DENSEL polarity is controlled by bit 5 of the FDC Configuration Register.

DIR 68 O

12,O2/12

Direction. Determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in, inactive = step out) during a seek operation. During reads or writes,

DIR is inactive.

DR0 70 O

12,O2/12

Drive Select 0. Decoded drive select output signal. DR0 is controlled by bit 0 of the Digital Output Register (DOR).

DR1 71 O

12,O2/12

Drive Select 1. Decoded drive select output signal. DR0 is controlled by bit 1 of the Digital Output Register (DOR).

DRATE0 74 O

3/6

Data Rate 0. Reflects the value of bit 0 of the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last. Output from the pin is push-pull buffered.

DSKCHG 60 I

Disk Change. Indicates if the drive door has been opened. The state of this pin is stored in the Digital Input Register (DIR). This pin can also be configured as the RGATEdata separator diagnostic input signal via the MODE command.

HDSEL 61 O

12,O2/12

Head Select. Determines which side of the FDD is accessed. Active low selects side 1, inactive selects side 0.

INDEX 73 I

Index. Indicates the beginning of an FDD track.

MTR0 72 O

12,O2/12

Motor Select 0. Active low, motor enable line for drives 0, controlled by bits D7-4 of the Digital Output Register (DOR).

MTR1 69 O

12,O2/12

Motor Select 1. Active low, motor enable lines for drives 1, controlled by bits D7-4 of the Digital Output Register (DOR).

RDATA62 I

Read Data. Raw serial input data stream read from the FDD.

STEP 67 O

12,O2/12

Step. Issues pulses to the disk drive at a software programmable rate to move the head during a seek operation.

TRK0 64 I

Track 0. Indicates to the controller that the head of the selected floppy disk drive is at track 0.

WDATA66 O

12,O2/12

Write Data. Carries out the pre-compensated serial data that is written to the floppy disk drive. Pre-compensation is software selectable.

WGATE 65 O

12,O2/12

Write Gate. Enables the write circuitry of the selected disk drive. WGATE is designed to prevent glitches during power up and power down. This prevents writing to the disk when power is cycled.

WP 63 I

Write Protected. Indicates that the disk in the selected drive is write protected. A software programmable conﬁguration bit (FDC conﬁguration at Index F0h, Logical Device 0) can force an active write-protect indication to the FDC, regardless of the status of this pin.

1.0 Signal/Pin Connection and Description (Continued)

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1.4.6 General-Purpose Input/Output (GPIO) Ports

1.4.7 Infrared (IR)

Signal Pin/s I/O Buffer Type Power Well Description

GPIO00-07 2-9 I/O

6,O3/6

General-Purpose I/O Port 0, bits 0-7. Each pin is configured independently as input or I/O, with or without static pull-up, and with either open-drain or push-pull output type. The port support interrupt assertion and each pin can be enabled or maskedas an interrupt source.

GPIO10 GPIO11-14 GPO15 GPIO16-17

21 53-56 57 69, 71

I/O

6,O3/6

General-Purpose I/O Port 1, bits 0-7. Same as Port 0. Bit 5 is output only with low output as default.

GPIO20-27 117-124 I/O

6,O3/6

General-Purpose I/O Port 2, bits 0-7. Similar to port 0, but without the interrupt assertion capability.

GPIO30-33 GPIO34

125-128 1 I/O

6,O3/6

General-Purpose I/O Port 3, bits 0-4. Similar to port 0, but without the interrupt assertion capability. Bits 5, 6 and 7 are not implemented.

GPIO40-47 43-50 I/O

6,O3/6

General-Purpose I/O Port 4, bits 0-7. Same as Port 0.

Signal Pin/s I/O Buffer Type Power Well Description

IRRX1 59 I

VDD,V

IR Receive 1. Primary input to receive serial data from the IR transceiver. Monitored during power-off for wake-up event detection.

IRRX2_IRSL0 58 I/O

TS/O3/6

VDD,VSBIRRX2 - IR Receive 2. Auxiliary IR receiver input to support a

second transceiver. Monitored during power-off for wake-up event detection.

IRSL3-0 IR Select. Output are used to control the IR transceivers. Input for PnP identiﬁcation of plug-in IR transceiver (dongle).

After reset, the dual-function IRSLX pins wake up in input mode. After the ID is read by the IR driver, they may be put into output mode. The output mode is controlled by Serial Port 2.

IRSL1 127 I/O

T/O3/6

IRSL2 69 I/O

T/O3/6

IRSL3 71 I

IRTX 57 O

6/12

IR Transmit. IR serial output data.

1.0 Signal/Pin Connection and Description (Continued)

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1.4.8 Keyboard and Mouse Controller (KBC)

1.4.9 Parallel Port

Signal Pin/s I/O Buffer Type Power Well Description

GA20 9 I/O

/OD

Gate A20. KBC gate A20 (P21) output.

KBCLK 111 I/O

/OD14VDD,V

Keyboard Clock. Transfers the keyboard clock between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P26 signal, and is connected internally to the T0 signal of the KBC. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage.

KBDAT 112 I/O

/OD14VDD,V

Keyboard Data. Tr ansfers the ke yboard data between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P27 signal, and is connected internally to KBC P10. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage.

KBRST 8 I/O

/OD

KBD Reset. Keyboard Reset (P20) output.

MCLK 113 I/O

/OD14VDD,V

Mouse Clock. Transfers the mouse clock between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P23 signal, and is connected internally to KBC T1. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage.

MDAT 114 I/O

/OD14VDD,V

Mouse Data. Transfers the mouse data between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P22 signal, and is connected internally to KBC P11. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage.

P12, P16, P17

6,127, 7

I/O

/OD

I/O Port. KBC open-drain signal for general-purpose input and output, controlled by KBC ﬁrmware.

Signal Pin/s I/O Buffer Type Power Well Description

ACK 79 I

Acknowledge. Pulsed low by the printer to indicate that it has received data from the Parallel Port.

AFD_DSTRB 93 O

14,O14/14

AFD - Automatic Feed. When low, instructs the printer to automatically feed a line after printing each line. This pin is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be attached to this pin.

DSTRB - Data Strobe (EPP). Active low, used in EPP mode to denote a data cycle. When the cycle is aborted,

DSTRB

becomes inactive (high).

BUSY_

WAIT 78 I

Busy. Set high by the printer when it cannot accept another character.

Wait. In EPP mode, the Parallel Port device uses this active low signal to extend its access cycle.

ERR 91 I

Error. Set active low by the printer when it detects an error.

1.0 Signal/Pin Connection and Description (Continued)

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1.4.10 Power and Ground

INIT 89 O

14,O14/14

Initialize. When low, initializes the printer. This signal is in TRI-STATE after a 1 is loaded into the corresponding control register bit. Use an external 4.7 KΩ pull-up resistor.

PD7-5 PD4-3, PD2, PD1 PD0

80-82 85-86 88, 90 92

I/O

14,O14/14

Parallel Port Data. Transfer data to and from the peripheral data bus and the appropriate Parallel Port data register. These signals have a high current drive capability.

PE 77 I

Paper End. Set high by the printer when it is out of paper. This pin has an internal weak pull-up or pull-down resistor.

SLCT 76 I

Select. Set active high by the printer when the printer is selected.

SLIN_ASTRB 87 O

14,O14/14

SLIN - Select Input. When low, selects the printer. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. Uses an external 4.7 KΩ pull-up resistor.

ASTRB - Address Strobe (EPP). Active low, used in EPP mode to denote an address or data cycle. When the cycle is aborted,

ASTRB becomes inactive (high).

STB_WRITE 94 O

14,O14/14

STB - Data Strobe. When low, Indicates to the printer that valid data is available at the printer port. This signal is in TRISTATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be employed.

WRITE - Write Strobe. Active low, used in EPP mode to denote an address or data cycle. When the cycle is aborted, WRITE becomes inactive (high).

Signal Pin/s I/O Buffer Type Power Well Description

BAT

30 I

ULR

Battery Power Supply. Provides battery back-up to the System Wake-Up Control registers, when V

is lost (power-fail). The

pin is connected to the internal logic through a series resistor for UL protection.

20, 52, 83, 115

I PWR - Main 3.3V Power Supply

31 I PWR -

Standby 3.3V Power Supply. Provides power to the Wake-Up Control circuitry, while the main power supply is turned off.

19, 51, 84, 116

I GND - Ground

Signal Pin/s I/O Buffer Type Power Well Description

1.0 Signal/Pin Connection and Description (Continued)

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1.4.11 Protection

1.4.12 Serial Port 1 and Serial Port 2

Signal Pin(s) I/O Buffer Type Power Well Description

XLOCK 53 I

Access Lock. When low, this pin blocks read/write from/to the SuperI/O Conﬁguration 6 (SIOCF6) register to prevent accidental access.

Signal Pin/s I/O Buffer Type Power Well Description

CTS1 CTS2

100 108

Clear to Send. When low, indicate that the modem or other data transfer device is ready to exchange data.

DCD1 DCD2

95 103

Data Carrier Detected. When low, indicate that the modem or other data transfer device has detected the data carrier.

DSR1 DSR2

96 104

Data Set Ready. When low, indicate that the data transfer device, e.g., modem, is ready to establish a communications link.

DTR1_ BOUT1

DTR2_ BOUT2

101

109

3/6

Data Terminal Ready. When low, indicate to the modem or other data transfer device that the UART is ready to establish a communications link. After a system reset, these pins provide the DTR function and set these signals to inactive high. Loopback operation holds them inactive.

Baud Output. Provides the associated serial channel baud rate generator output signal if test mode is selected, i.e., bit 7 of the EXCR1 Register is set.

DTR1_BOUT1 is used also as BADDR.

RI1 RI2

102 110

VDD,V

Ring Indicator. When low, indicate that a telephone ring signal has been received by the modem. They are monitored during power-off for wake-up event detection.

RTS1 RTS2

98 106

3/6

Request to Send. When low, indicate to the modem or other data transfer device that the corresponding UART is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them inactive.

RTS1 is used also as TEST.

SIN1 SIN2

97 105

Serial Input. Receive composite serial data from the communications link (peripheral device, modem or other data transfer device).

SOUT1 SOUT2

99 107

3/6

Serial Output. Send composite serial data to the communications link (peripheral device, modem or other data transfer device). These signals are set active high after a system reset.

1.0 Signal/Pin Connection and Description (Continued)

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1.4.13 Strap Configuration

1.4.14 System Wake-Up Control

1.4.15 WATCHDOG Timer (WDT)

Signal Pin/s I/O Buffer Type Power Well Description

BADDR 101 I

STRP

Base Address. Sampled by the trailing edge of the system reset to determine the base address of the conﬁguration Index-Data register pair. During reset, it is pulled down by internal 30Kohm resistor.

If no pull-up resistor is connected, it is sampled low, setting the Index-Data pair at 2Eh-2Fh.

Connecting a 10K external pull-up resistor to V

would make it

sample high, setting the Index-Data pair at 4Eh-4Fh.

TEST 98 I

STRP

Test. If sampled high on the trailing edge of system reset, this signal forces the device into test mode. This pin is for National Semiconductor use only, and should be left unconnected.

Signal Pin/s I/O Buffer Type Power Well Description

LED1 LED2

25 26

12/12

LED. VSB-powered pins with programmable outputs, each of which can be used to produce a 0, 0.25, 0.5, 1, 4 Hz waveform for

LED control.

GPIE6-7 58-59 I

General-Purpose Input Event

GPIOE0-5 23-28 I/O

6,O3/6

General-Purpose I/O Event. VSB-powered pins.

PWUREQ 32 O

Power-Up Request. Active (low) level indicates that wake-up event has occurred, and causes the chipset to turn the power supply on, or to exit its current sleep state. The open-drain output must be pulled up to V

in order to function during power-off.

RING 27 I

Telephone Line Ring. Detection of a pulse train on the RING pin is a wake-up event that can activate the power-up request (

PWUREQ). The pin has a Schmidt-trigger input buffer, powered

by V

Signal Pin/s I/O Buffer Type Power Well Description

WDO 56 O

6,O3/6

WATCHDOG Out. Low level indicates that the WATCHDOG Timer has reached its time-out period without being retriggered.

The output type and an optional pull-up are conﬁgurable.

1.0 Signal/Pin Connection and Description (Continued)

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1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS

The signals listed in Table 4 can optionally support internal pull-up (PU) and/or pull-down (PD) resistors. See Section 10.3 for the values of each resistor type.

Table 4. Internal Pull-Up and Pull-Down Resistors

Signal Pin/s Type Comments

ACCESS.bus (ACB)

SCL 54 PU

Programmable

SDA 55 PU

Programmable

General-Purpose Input/Output (GPIO) Ports

GPIO00-07 2-9

Programmable

GPIO10 GPIO11-14 GPO15 GPIO16-17

21 53-56 57 69, 71

Programmable

GPIO20-27 117-124

Programmable

GPIO30-33 GPIO34

125-128 1

Programmable

GPIO40-47 43-50

Programmable

Keyboard and Mouse Controller (KBC)

P12, P16, P17 6,127,7 PU

Strap Conﬁguration

BADDR 101 PD

Strap

TEST 98 PD

Strap

Parallel Port

ACK 79

AFD_DSTRB 93

100

BUSY_WAIT 78

ERR 91

INIT 89

100

PE 77

Programmable

SLCT 76

SLIN_ASTRB 87

100

STB_WRITE 94

100

System Wake-Up Control (SWC)

GPIE6-7 58-59

Programmable

GPIOE0-5 23-28

Programmable

1.0 Signal/Pin Connection and Description (Continued)

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RING 27 PU

WATCHDOG Timer (WDT)

WDO 56 PU1 Programmable

Signal Pin/s Type Comments

1.0 Signal/Pin Connection and Description (Continued)

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2.0 Device Architecture and Conﬁguration

The PC87360 SuperI/O device comprises a collection of generic and proprietary functional blocks. Each functional block is described in aseparatechapterinthisdocument.However,some parameters in the implementation of each functional block may vary per SuperI/O device. This chapter describes the PC87360 structure and provides all logical device specific information, including special implementation of generic blocks, system interface and device configuration.

2.1 OVERVIEW

The PC87360 consists of 11 logical devices, the host interface, and a central set of configuration registers, all built around a central, internal bus.The internal bus is similarto an 8-bit ISA busprotocol. See Figure 1, whichillustrates the blocks and related logic.

The system interface serves as a bridge between theexternalLPC interface and the internal bus. It supports 8-bit I/O Read, 8-bit I/O Write and 8-bit DMA transactions, as defined in Intel’s

LPC Interface Speciﬁcation, Revision 1.0

The central configuration register set supportsACPIcompliantPnPconfiguration.Theconfigurationregistersarestructuredas a subset of the Plug and PlayStandardregisters, defined in Appendix A of the

Plug and Play ISA Specification, Revision 1.0a

byIntelandMicrosoft. All systemresourcesassignedto the functional blocks(I/Oaddressspace, DMA channelsandIRQlines) are configured in, and managed by, the central configuration register set. In addition, some function-specific parameters are configurable through the configuration registers and distributed to the functional blocks through special control signals.

2.2 CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is comprised of a set of banked registers which are accessed via a pair of specialized registers.

2.2.1 The Index-Data Register Pair

Access to the SuperI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations. The base address of thisregister pair is determined during reset,according to the state of thehardware strapping option on the BADDR pin. Table 5 shows the selected base addresses as a function of BADDR.

Table 5. BADDR Strapping Options

The Index register is an 8-bit R/W register located atthe selected base address (Base+0). It is used as a pointer to the configuration register file, and holds the index of the configuration register that is currently accessible via the Data register. Reading the Index register returns the last value written to it (or the default of 00h after reset).

The Data register is an 8-bit virtual register, used as a data path to any configuration register. Accessing the Data register actually accesses the configuration register that is currently pointed to by the Index register.

BADDR

I/O Address

Index Register Data Register

0 2Eh 2Fh 1 4Eh 4Fh

2.0 Device Architecture and Configuration (Continued)

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Figure 1. PC87360 Detailed Block Diagram

Keyboard

Fan Speed

Serial Port 1

Mouse

Controller

Control &

ACCESS.

Internal Bus

Bus

Control Signals

Interface

bus

SCL

SDA

Monitor

LCLK

LRESET

LAD3-0

LFRAME

LDRQ

SERIRQ

CLKIN

System

P12,P16,P17 GA20

KBCLK KBDAT

MDAT

MCLK

KBRST

SIN1

SOUT1

RTS1

DTR1/BOUT1

CTS1 DSR1 DCD1

RI1

with IR

IRRX1,IRRX2

IRTX IRSL0-2

SIN2 SOUT2 RTS2 DTR2/BOUT2 CTS2 DSR2

DCD2 RI2

Serial Port 2

IRSL3

FANOUT0,1

FANIN0,1

SLCT

PD0-7

Parallel

Port

DRATE0

RDATA

WDATA

WGATE

HDSEL

DIR

STEP

TRK0

INDEX

MTR1,0

DR1,0

DENSEL

FDC

WA TCHDOG

Timer

WDO

GPIO20-27

GPIO30-34

GPIO40-47

GPIO

Ports

SMI

STB_WRITE

AFD_DSTRB

ERR

INIT

SLIN_ASTRB

ACK

BUSY_WAIT

LED1,2

PWUREQ

RING

GPIE6,7

GPIOE0-5

Wake-Up Control

Protection

DSKCHG

XLOCK

PIRQ3-7,9-12,14-15

Strap

BADDR

TEST

& Control

Registers

Conﬁg

GPIO00-07

GPIO10-14,16,17

GPO15

Conﬁg

2.0 Device Architecture and Configuration (Continued)

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2.2.2 Banked Logical Device Registers Structure

Eachfunctionalblockisassociated with a LogicalDeviceNumber(LDN).The configuration registers aregroupedintobanks, where each bank holds the standard configuration registers of the corresponding logical device. Table 6 shows the LDN values of the PC87360 functional blocks.

Figure 2 shows the structure of the standard configuration registerfile. The SuperI/O control and configuration registers are not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and device configuration registers are duplicated over banks for logical devices. Therefore, accessing a specific register in a specific bank is performed bytwo dimensional indexing, where the LDN register selects the bank (or logical device)and the Index register selects the register within the bank. Accessing the Data register while the Index register holds a value of 30h or higher results in a physical access totheLogical Device Configuration registers currently pointed to by the Indexregister, within the logical device currently selected by the LDN register.

Figure 2. Structure of the Standard Conﬁguration Register File

Table 6. Logical Device Number (LDN) Assignments

Write accesses to unimplemented registers (i.e. accessing theDataregister while the Index register points to a non-existing register), are ignored and read returns 00h on all addresses except for 74h and 75h (DMA configuration registers) which returns 04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.

LDN Functional Block

00h Floppy Disk Controller (FDC) 01h Parallel Port (PP) 02h Serial Port 2 with IR (SP2) 03h Serial Port 1 (SP1) 04h System Wake-Up Control (SWC) 05h Keyboard and Mouse Controller (KBC) - Mouse interface 06h Keyboard and Mouse Controller (KBC) - Keyboard interface 07h General-Purpose I/O (GPIO) Ports 08h ACCESS.bus Interface (ACB) 09h Fan Speed Control and Monitor (FSCM)

0Ah WATCHDOG Timer (WDT)

07h 20h

30h 60h

75h

FEh

Logical Device Number Register

SuperI/O Configuration Registers

Logical Device Control Register

Standard Logical Device

Special (Vendor-defined)

Configuration Registers

Banks

2Fh

F0h

Bank Select

63h

74h

70h 71h

Configuration Registers

(One per Logical Device)

Logical Device

2.0 Device Architecture and Configuration (Continued)

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2.2.3 Standard Logical Device Configuration Register Definitions

Unless otherwise noted in Tables 7 through 12:

●

All registers are read/write.

●

All reserved bits return 0 on reads, except where noted otherwise. They must not be modiﬁed as it may cause unpredictable results. Use read-modify-write to prevent the values of reserved bits from being changed during write.

●

Write only registers should not use read-modify-write during updates.

Table 7. Standard Control Registers

Table 8. Logical Device Activate Register

Table 9. I/O Space Conﬁguration Registers

Index Register Name Description

07h Logical Device

Number

This register selects the current logical device. See Table 6 for valid numbers. All other values are reserved.

20h - 2Fh SuperI/O

Conﬁguration

SuperI/O conﬁguration registers and ID registers

Index Register Name Description

30h Activate Bit 0 - Logical device activation control

0: Disabled 1: Enabled

Bits 7-1 - Reserved

Index Register Name Description

60h I/O Port Base

Address Bits (15-8)

Descriptor 0

Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0.

61h I/O Port Base

Address Bits (7-0)

Descriptor 0

Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0.

62h I/O Port Base

Address Bits (15-8)

Descriptor 1

Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 1.

63h I/O Port Base

Address Bits (7-0)

Descriptor 1

Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 1.

2.0 Device Architecture and Configuration (Continued)

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Table 10. Interrupt Conﬁguration Registers

Table 11. DMA Conﬁguration Registers

Table 12. Special Logical Device Conﬁguration Registers

Index Register Name Description

70h Interrupt Number

and Wake-Up on

IRQ Enable

Indicates selected interrupt number. Bit 4 - Enables wake-up on the IRQ of the logical device. When enabled, IRQ

assertion triggers a wake-up event.

0: Disabled (default) 1: Enabled

Bits 3-0 select the interrupt number. A value of 1 selects IRQ1, a value of 2 selects IRQ2, etc. (up to IRQ15). IRQ0 is not a valid interrupt selection.

71h Interrupt Request

Type Select

Indicates the type and level of the interrupt request number selected in the previous register.

Bit 0 - Type of interrupt request selected in previous register

0: Edge 1: Level

Bit 1 - Level of interrupt request selected in previous register

0: Low polarity 1: High polarity

Index Register Name Description

74h DMA Channel

Select 0

Indicates selected DMA channel for DMA 0 of the logical device (0 - The ﬁrst DMA channel in case of using more than one DMA channel).

Bits 2-0 select the DMA channel for DMA 0. The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.

A value of 4 indicates that no DMA channel is active. The values 5-7 are reserved.

75h DMA Channel

Select 1

Indicates selected DMA channel for DMA 1 of the logical device (1 - The second DMA channel in case of using more than one DMA channel).

Bits 2-0 select the DMA channel for DMA 1. The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.

A value of 4 indicates that no DMA channel is active. The values 5-7 are reserved.

Index Register Name Description

F0h-FEh Logical Device

Conﬁguration

Special (vendor-deﬁned) conﬁguration options.

2.0 Device Architecture and Configuration (Continued)

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2.2.4 Standard Configuration Registers

Figure 3. Conﬁguration Register Map

SuperI/O Control and Conﬁguration Registers

The SuperI/O Configuration registers at indexes 20h and 27h are mainly used for part identification, global power management and the selection of pin multiplexing options. For details, see Section 2.7.

Logical Device Control and Conﬁguration Registers

A subset of these registers is implemented for each logical device. See functional block description in the following sections.

SuperI/O Control and Conﬁguration Registers

Logical Device Control and

one per Logical Device

Conﬁguration Registers -

Index Register Name

07h Logical Device Number 20h SuperI/O ID 21h SuperI/O Conﬁguration 1 22h SuperI/O Conﬁguration 2 23h SuperI/O Conﬁguration 3 24h SuperI/O Conﬁguration 4 25h SuperI/O Conﬁguration 5 26h SuperI/O Conﬁguration 6 27h SuperI/O Revision ID 28h SuperI/O Conﬁguration 8 2Ah SuperI/O Conﬁguration A 2Bh SuperI/O Conﬁguration B 2Ch SuperI/O Conﬁguration C 2Eh Reserved exclusively for National use 30h Logical Device Control (Activate) 60h I/O Base Address Descriptor 0 Bits 15-8 61h I/O Base Address Descriptor 0 Bits 7-0 62h I/O Base Address Descriptor 1 Bits 15-8 63h I/O Base Address Descriptor 1 Bits 7-0 70h Interrupt Number and Wake-Up on IRQ Enable 71h IRQ Type Select 74h DMA Channel Select 0 75h DMA Channel Select 1 F0h Device Speciﬁc Logical Device Conﬁguration 1 F1h Device Speciﬁc Logical Device Conﬁguration 2 F2h Device Speciﬁc Logical Device Conﬁguration 3

(some are optional)

2.0 Device Architecture and Configuration (Continued)

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Control

The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate register controls the activation of the associated function block. Activation of the block enables access to the block’s registers, and attaches its system resources, which are unused as long as the block is not activated. Other effects may apply, on a function-specific basis (such as clock enable and active pinout signaling).

Standard Conﬁguration

The standard configuration registers are used to manage the PnP resource allocation to the functional blocks. The I/O port base address descriptor 0 is a pair of registers atIndex60-61h,holding the (first or only) 16-bit base address for the register set of the functional block.An optional 16-bit second base-address (descriptor 1) at index 62-63h is used forlogical devices with more thanonecontinuousregisterset.InterruptNumberand Wake-Up on IRQ Enable (index 70h) and IRQ Type Select (index 71h)allocateanIRQline to the block and controlitstype.DMAChannel Select 0 (index 74h) allocatesaDMAchannel to the block, where applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable.

Special Conﬁguration

The vendor-defined registers, starting at index F0h, are used to control function-specific parameters such as operation modes, power saving modes, pin TRI-STATE, clock rate selection, and non-standard extensions to generic functions.

2.2.5 Default Configuration Setup

The default configuration setup of the PC87360 can include four reset types,describedbelow.See specific register descriptions for the bits affected by each reset type.

• Software Reset

This reset is enabled by bit 1 of the SIOCF1 register, which resets all logical devices. A software reset also resets most bits in the SuperI/O control and configuration registers (see Section 2.7 for the bits not affected). This reset does not affect register bits that are locked for write access.

• Hardware Reset

This reset isactivatedbytheassertionofthe

LRESET input. Itresetsalllogicaldevices,withtheexception of the System Wake-Up Control (SWC). It also resets all SuperI/O control and configuration registers, except for those thatarebatterybacked.

• V

Power-Up Reset

This reset is activated when either V

or V

BAT

is powered up after both have been off. VPPis an internal voltage which

is a combination of V

and V

BAT.VPP

is taken from VSBif VSBis greater than the minimum (Min) value defined in the

Device Characteristics

chapter; otherwise, V

BAT

is used as the VPPsource. This reset resets all registers whose values

are retained by V

• V

Power-Up Reset

This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by V

. This reset is activated after VSB is powered up.

In event of a hardware reset, the PC87360 wakes up with the following default configuration setup:

— The conﬁguration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 5. — The Keyboard Controller (KBC) is active and all other logical devices are disabled, with the exception of the SWC

which remains functional but whose registers cannot be accessed.

— All multiplexed GPIO pins, exceptfor pins whose function is controlled bybattery-backed registers and pins 8 and 9

(which are controlled by bits 1 and 0 of the SIOCF3 register) areconﬁguredas GPIO pins, with an internal static pullup (default direction is input).

In event of either a hardware or a software reset, the PC87360 wakes up with the following default configuration setup:

— The legacy devices are assigned with their legacy system resource allocation. — The National proprietary functions are not assigned with any default resources and the default values of their base

addresses are all 00h.

2.2.6 Power States

The following terminology is used in this document to describe the various possible power states:

• Power On

Both V

and VDD are active.

• Power Off

is active and VDD is inactive.

2.0 Device Architecture and Configuration (Continued)

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• Power Fail

Both V

and VDD are inactive.

Note: The following state is illegal: V

active and VSB inactive.

2.2.7 Address Decoding

A full 16-bitaddressdecodingisappliedwhenaccessingthe configuration I/O space as well as the registers ofthefunctional blocks. However, the number of configurable bits in the base address registers varies for each logical device.

The lower1,2,3,4 or 5addressbitsaredecodedwithin the functional block to determine theoffsetoftheaccessedregister, within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base address register to decode the entire I/O range allocated to the logical device. Therefore the lower bits of the base address register are forced to 0(read only), and the base addressis forced to be 2, 4,8, 16 or 32 byte-aligned, accordingto the size of the I/O range.

The base address of the FDC, Serial Port 1, Serial Port 2 with IR and KBC are limited to the I/O address range of 00h to 7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses of the non-legacy logical devices are configurable within the full 16-bit address range (up to FFFXh).

In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel Port). The KBC has two I/Odescriptors with some implied dependency between them. Formore details, see the description of the base address register for each logical device.

2.3 INTERRUPT SERIALIZER

The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from external devices, via the PIRQn pins, into serial interrupt request data transmitted over the SERIRQ bus. This enables the integration of devices that support only parallel IRQ in a system which supports only serial IRQs. Figure 4 shows the interrupt serialization mechanism.

Figure 4. Interrupt Serialization Mechanism

PIRQ signals that enter the device are fed into an IRQ sharing mechanism. This mechanism combines them with internal IRQ signals that are mappedto their associated IRQ slots. Theresulting internal shared IRQs are thenfed into the Interrupt Serializer, where they are translated into serial data and transmitted over the SERIRQ bus.

The IRQ sharing mechanism allows an internal IRQ and an external PIRQ to share the same IRQ slot. To share an IRQslot, all IRQ sources routed to it, includingpossibly a PIRQn pin, must be active low. WhenmultipleIRQ sources are set to share an IRQ slot, the corresponding internal IRQ signal is a logic AND of all IRQ sources.

When an IRQ slot is exclusively used by a PIRQ pin, each transition sensed on this PIRQ pin is translated into a new value. This value is transmitted over the SERIRQ bus during the corresponding IRQ slot. A transition on PIRQn results in a new value that is transmitted during IRQ slot “n” of the SERIRQ bus. For example, a transition on PIRQ3 is translated into the transmission of the new value of PIRQ3 during slot 3 of the SERIRQ bus. No polarity adjustment occurs during this translation process. Therefore, when the level of a PIRQn pin goes high or low, the result is transmitted with no polarity adjustment during slot “n” of the SERIRQ bus.

IRQ Mapping

and Polarity

Control

IRQ Sharing

Mechanism

Internal

IRQ

Sources

Internal

Polarity/

Control Signals

PIRQn Pins

Shared PIRQs

IRQ3

IRQ15

Interrupt

Serializer

Mapped IRQs

Non-Shared

Bus Interface

SERIRQ

Mapping

PIRQs

2.0 Device Architecture and Configuration (Continued)

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The Interrupt Serializer is controlledby bit 6, Pins 117-127 SelectPIRQ, of SuperI/O Configuration 1 register. When this bit is setto0(default),theInterruptSerializer is disabled. When it is set to1,theInterruptSerializerisenabled, and each PIRQn input function is selected on its associated pin. The PIRQn input value is then routed to the Interrupt Serializer as the IRQ value to be driven onto IRQ slot “n” when at least one of the following conditions is true:

●

Slot “n” is not selected by any internal IRQ source.

●

Slot “n” is selected by an internal IRQ source which is set for sharing (low polarity).

Otherwise, the IRQ value driven onto IRQ slot “n” is the value of any internal IRQ that is selected.

2.4 PROTECTION

The PC87360 provides features to protect the PC at both hardware and software levels .

The device can disable I/O port access.Thisprotectssystemintegritybyenablingtheprimaryoperatingsoftwaretoprevent

other unwanted I/O operations by other software. At the software level, the device can be locked to protect configuration bits or alterationof the hardware configuration of the

device, as well as internal GPIO settings and several types of configuration settings. All protection mechanisms can optionally be used.

2.4.1 Access Lock to I/O Ports

Locking access to the I/O ports of the device is based on the SIOCF6 register (for details, see Section 2.7.7). This protection feature is implemented for the following logical devices:

●

FDC (Logical Device 0)

●

Parallel Port (Logical Device 1)

●

Serial Port 2 (Logical Device 2)

●

Serial Port 1 (Logical Device 3)

●

ACB (Logical Device 8)

Each one of theselogicaldeviceshasanassociatedbitinthe SIOCF6 register. When one of these bits is set, the associated logical device is completely disabled. For example, when bit 0 of the SIOCF6 register is set to 1, the FDC is disabled.

To lock access to the I/O ports, the SIOCF6 register must be set to read only. This can be done by either software or hardware. Bysoftware,setbit 7 of the SIOCF6registerto1. This bit can onlybecleared(read/write enabled) by a hardwarereset.

Alternatively, use the

XLOCK input hardware-based function to set the SIOCF6 register to read only. First, select XLOCK

on its pin, pin 53, by setting bit 4 of the SIOCF3 register to 1.

XLOCK can then can be used to control the SIOCF6 register,

as follows:

●

When XLOCK is driven high, the SIOCF6 register is read/write.

●

When XLOCK is driven low, the SIOCF6 register is read only.

2.4.2 Pin Configuration Lock

To lock the pin configuration of the PC87360 in order to prevent unwanted changes to hardware configuration, set bit 7 of the SIOCF1 register to 1. Setting thisbitcausesallfunctionselectconfigurationbits,includingthosethatarebatterybacked, to become read only bits. This bit can only be cleared by a hardware reset.

2.4.3 GPIO Pin Function Lock

The PC87360 is capable of locking the attributes of each GPIO or Standby GPIO pin. The following attributes can be locked:

●

Output enable

●

Output type

●

Static pull-up

●

Driven data.

GPIO pins are locked per pin by setting the Lock bit in the appropriate GPIO Pin Configuration register. When the Lock bit is set, the configuration of the associated GPIO pin can only be released by a hardware reset.

Standby GPIOpinsarelockedin the same manner bysettingtheLockbit in the appropriate Standby GPIOPinConfiguration registers. However,onceaStandbyGPIOpinis locked, its locked attributes can onlybereleasedwithaV

power-up reset.

Table 13 summarizes the bit states that affect PSON V

power-up default state.

2.0 Device Architecture and Configuration (Continued)

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Table 13. PSON VSB Power-Up Default State

2.5 LED OPERATION AND STATES

The device supports up to two LEDs, depending on Pin 25 and Pin 26 Function Select (bits 1-2 and bit 3) of the SIOCFA register. The polarity of both LEDs is determined by LED Polarity Control (bit 7) of the SIOCFD register.

, when in power-on state. The device also provides modes for hardware LED control. This enables the LEDs to support features such as power and error indication.

The LEDs may be operated in software, hardware1 or hardware 2 modes. These modes are set by LED Mode Control (bits 2 and 3) of the SIOCFB register. Each LED can be set to On, Off or to blink at different rates by means of bits 0-2 (LED1) and bits 3-5 (LED2) of the SIOCFC register. When in power-on state (both V

and VSBexist), the LEDs are software-con-

trolled. When in power fail state (no V

and no VDD) the LEDs are off. Table 14showsthe effect of hardware modes 1 and

2 on LED operation that override the above rules.

Table 14. Hardware Modes 1 and 2 Effect on LED Operation

2.6 REGISTER TYPE ABBREVIATIONS

The following abbreviations are used to indicate the Register Type:

●

R/W = Read/Write

●

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different register.

●

W=Write

●

RO = Read Only

●

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

2.7 SUPERI/O CONFIGURATION REGISTERS

This section describes theSuperI/OconfigurationandIDregisters(thoseregisterswithfirstlevel indexes in the range of 20h

- 2Eh). See Table 15 for a summary and directory of these registers.

Table 15. SuperI/O Conﬁguration Registers

Resume Last

PSON State

(SIOCFD, Bit 2)

Last PSON

State

PSON V

Power-Up

Default

10 0 11 1 0 X Same as

SLPS3 state

Mode System State LED1 LED2

Hardware 1 (SIOCFB, bits 3-2=01)

VSBpower-up reset

Off 1 Hz blink, 50% duty cycle

Power off (V

,noVDD)

Software-controlled 1 Hz blink, 50% duty cycle

Index Mnemonic Register Name Power Well Type Section

20h SID SuperI/O ID V

RO 2.7.1

21h SIOCF1

SuperI/O Conﬁguration 1

R/W 2.7.2

22h SIOCF2 SuperI/O Conﬁguration 2 V

R/W 2.7.3

23h SIOCF3 SuperI/O Conﬁguration 3 V

R/W 2.7.4

24h SIOCF4 SuperI/O Conﬁguration 4 V

R/W 2.7.5

25h SIOCF5 SuperI/O Conﬁguration 5 V

R/W 2.7.6

27h SRID SuperI/O Revision ID V

RO 2.7.8

2.0 Device Architecture and Configuration (Continued)

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28h SIOCF8 SuperI/O Conﬁguration 8 V

R/W 2.7.9

2Ah SIOCFA SuperI/O Conﬁguration A V

R/W 2.7.10

2Bh SIOCFB SuperI/O Conﬁguration B V

R/W 2.7.11

2Ch SIOCFC SuperI/O Conﬁguration C V

R/W 2.7.12

2Eh Reserved exclusively for National use

Index Mnemonic Register Name Power Well Type Section

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2.7.1 SuperI/O ID Register (SID)

This register contains the identity number of the chip. The PC87360 is identified by the value E1h. Location: Index 20h Type: RO

2.7.2 SuperI/O Configuration 1 Register (SIOCF1)

Location: Index 21h Type: R/W

Bit 76543210 Name Chip ID Reset 11100001

Bit 76543210

Name

Function

Select Lock

Pins

117-127

Function

Select

Number of DMA Wait

States

Number of I/O Wait

States

SW Reset

Global Device

Enable

Reset 00010001

Bit Description

7 Pin Function Select Lock. This bit determines if the bits (located in the SIOCF1, 2, 3, 4, 5, A and B registers)

that select pin functions are read only or read/write. When set to 1, this bit can only be cleared by a hardware reset.

0: Bits are R/W. 1: Bits are RO.

6 Pins 117-127 Function Select.

0: Pins 117-127 function set by SIOCF4 (default) 1: Pins 117-127 are PIRQ3-7, 9, 11-12, 14-15

5-4 Number of DMA Wait States.

Bits 5 4 Number

0 0 Reserved 0 1 Two (default) 1 0 Six 1 1 Twelve

3-2 Number of I/O Wait States.

Bits 3 2 Number

0 0 Zero (default) 0 1 Two 1 0 Six 1 1 Twelve

1 SW Reset. Read always returns 0.

0: Ignored (default) 1: Resets all the logical devices that are reset by hardware reset (with the exception of the lock bits), and resets

the registers of the SWC

0 Global Device Enable. This bit controls the function enable of all the PC87360 logical devices, except System

Wake-Up Control (SWC). With the exception of SWC, it allows all logical devices to be disabled simultaneously by writing to a single bit.

0: All logical devices in the PC87360 are disabled, except SWC 1: Each logical device is enabled according to its Activate register (Index 30h) (default)

2.0 Device Architecture and Configuration (Continued)

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2.7.3 SuperI/O Configuration 2 Register (SIOCF2)

Location: Index 22h Type: Varies per bit

Bit 7654 3210

Name

Pin 7

Function

Select

Pin 6

Function

Select

Pin 5

Function

Select

Pin 4

Function

Select

Pin 3

Function

Select

Pin 2

Function

Select

Pin 1

Function

Select

Reset 0000 0000

Bit Description

7 Pin 7 Function Select. This is a R/W bit.

0: GPIO05 (default) 1: P17

6 Pin 6 Function Select. This is a R/W bit.

0: GPIO04 (default) 1: P12

5 Pin 5 Function Select. This is a R/W bit.

0: GPIO03 (default) 1: FANOUT0

4 Pin 4 Function Select. This is a R/W bit.

0: GPIO02 (default) 1: FANIN0

3 Pin 3 Function Select. This is a R/W bit.

0: GPIO01 (default) 1: FANOUT1

2 Pin 2 Function Select. This is a R/W bit.

0: GPIO00 (default) 1: FANIN1

1-0 Pin 1 Function Select. This is a RO bit.

Bits 1 0 Function

0 0 GPIO34 (default) Others Reserved

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2.7.4 SuperI/O Configuration 3 Register (SIOCF3)

Location: Index 23h Type: R/W

Bit 76543210

Name

Pin 57

Function

Select

Pin 56

Function

Select

Pins 54, 55

Function

Select

Pin 53

Function

Select

Reserved

Pin 21

Function

Select

Pin 9

Function

Select

Pin 8

Function

Select

Reset 0 0 0 00011

Bit Description

7 Pin 57 Function Select.

0: GPO15 (default) 1: IRTX

6 Pin 56 Function Select.

0: GPIO14 (default) 1:

WDO

5 Pins 54, 55 Function Select.

0: GPIO12/GPIO13 (default) 1: SCL/SDA

4 Pin 53 Function Select.

0: GPIO11 (default) 1:

XLOCK 3 Reserved 2 Pin 21 Function Select.

0: GPIO10 (default) 1:

SMI 1 Pin 9 Function Select.

0: GPIO07 1: GA20 (P21) (default)

0 Pin 8 Function Select.

0: GPIO06 1: KBRST (P20) (default)

2.0 Device Architecture and Configuration (Continued)

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2.7.5 SuperI/O Configuration 4 Register (SIOCF4)

Location: Index 24h Type: Varies per bit

* Bit 6, Pins 117-127 Select PIRQ, of the SIOCF1 register

Bit 76543210

Name

Pin 127

Function

Select

Pins125,126

Function

Select

PIns 117-124

Function

Select

Pin 71

Function

Select

Pin 69

Function

Select

Reset 00000000

Bit Description 7-6 Pin 127 Function Select. This is a R/W bit.

Bits 7 6 P* Function

0 0 0 GPIO32 (default) 0 1 0 P16 1 0 0 IRSL1 X X 1 PIRQ15

5 Pins 125,126 Function Select. This is a RO bit.

Bits 5 P* Function

0 0 GPIO30,31 (default) 1 0 Reserved X 1 PIRQ12,14

4 Pins 117-124 Function Select. This is a RO bit.

Bits 4 P* Function

0 0 GPIO20-27 (default) 1 0 Reserved X 1 PIRQ3-7,9-11

3-2 Pin 71 Function Select. This is a R/W bit.

Bits 3 2 Function

0 0 GPIO17 (default) 0 1

DR1 1 0 IRSL3 1 1 Reserved

1-0 Pin 69 Function Select. This is a R/W bit.

Bits 1 0 Function

0 0 GPIO16 (default) 0 1

MTR1 1 0 IRSL2 1 1 Reserved

2.0 Device Architecture and Configuration (Continued)

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2.7.6 SuperI/O Configuration 5 Register (SIOCF5)

Location: Index 25h Type: Varies per bit

Bit 76543210

Name Reserved

SMI to IRQ2

Enable

Reserved

Pin 128

Function

Select

Reset 00000000

Bit Description

7-5 Reserved

SMI to IRQ2 Enable. This is a R/W bit. 0: Disabled (default) 1: Enabled

3-2 Reserved 1-0 Pin 128 Function Select. This is a RO bit.

Bits 1 0 Function

0 0 GPIO33 (default) Others Reserved

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2.7.7 SuperI/O Configuration 6 Register (SIOCF6)

Write access to this register can be inhibited by either asserting

XLOCK when it is selected on pin 53, or by setting bit 7 of this register. Activation of each logical device (bits 0-4) is also affected by bit 0 of the logical device Activate register, index 30h and bit 0 of the SIOCF1 register.

Location: Index 26h Type: R/W

2.7.8 SuperI/O Revision ID Register (SRID)

This register contains the identity number of the chip revision. SRID is incremented on each revision. Location: Index 27h Type: RO

Bit 76543210

Name

SIOCF6

Software

Lock

General-Purpose

Scratch

ACB

Disable

Serial Port 1

Disable

Serial Port 2

Disable

Parallel Port

Disable

FDC

Disable

Reset 00000000

Bit Description

7 SIOCF6 Software Lock. Once this bit is set to 1 by software, it can be cleared only by hardware reset.

0: Write access to bits 0-6 of this register is controlled by

XLOCK (default)

1: Bits 0-6 of this register are RO

6-5 General-Purpose Scratch

4 ACB Disable

0: Enabled (default) 1: Disabled

3 Serial Port 1 Disable

0: Enabled (default) 1: Disabled

2 Serial Port 2 Disable

0: Enabled (default) 1: Disabled

1 Parallel Port Disable

0: Enabled (default) 1: Disabled

0 FDC Disable

0: Enabled (default) 1: Disabled

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2.7.9 SuperI/O Configuration 8 Register (SIOCF8)

Location: Index 28h Type: R/W

Bit 76543210

Name Reserved

Mouse IRQ

to SMI

Enable

KBD IRQ to

SMI Enable

KBD P12 to

SMI Enable

GPI to

SMI

Enable

WDOtoSMI

Enable

Reset 0 0 0 00000

Bit Description

7-5 Reserved

4 Mouse IRQ to

SMI Enable

0: Disabled (default) 1: Enabled

3 KBD IRQ to

SMI Enable

0: Disabled (default) 1: Enabled

2 KBD P12 to

SMI Enable

0: Disabled (default) 1: Enabled

1 GPI to

SMI Enable

0: Disabled (default) 1: Enabled

WDO to SMI Enable

0: Disabled (default) 1: Enabled

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2.7.10 SuperI/O Configuration A Register (SIOCFA)

This is a battery-backed register. Location: Index 2Ah Type: R/W

Bit 76543210

Name Reserved

Pin 28

Function

Select

PIn 27

Function

Select

Pin 26

Function

Select

Pin 25

Function

Select

Reserved

Reset Strap 0000000

Bit Description

Reserved

6 Pin 28 Function Select

0: GPIOE5 (default at V

power-up reset)

1: Reserved

5-4 PIn 27 Function Select

Bits 5 4 Function

0 0 GPIOE4 (default at V

power-up reset)

0 1

RING

Other Reserved

3 Pin 26 Function Select

0: GPIOE3 (default at V

power-up reset)

1: LED2

2-1 Pin 25 Function Select

Bits 2 1 Function

0 0 GPIOE2 (default at V

power-up reset) 0 1 LED1 Other Reserved

0 Pin 24 Function Select

0: GPIOE1 (default at V

power-up reset)

1: Reserved

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2.7.11 SuperI/O Configuration B Register (SIOCFB)

This is a battery-backed register. Location: Index 2Bh

Type: R/W

Bit 7 6 5 4 3 2 1 0

Name Reserved LED

Mode Control

Pin 59

Function

Select

Pin 58

Function

Select

Reset 0 0 0 0 0 0 0 0

Bit Description

7-4 Reserved 3-2 LED Mode Control

Bits 3 2 Function

0 0 Software mode (default at V

power-up reset)

0 1 Hardware mode 1 (default at V

power-up)1 XReserved

1 Pin 59 Function Select

0: GPIE7 (default at V

power-up reset)

1: IRRX1

0 Pin 58 Function Select

0: GPIE6 (default at V

power-up reset)

1: IRRX2_IRSL0

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2.7.12 SuperI/O Configuration C Register (SIOCFC)

This is a battery-backed register. Location: Index 2Ch Type: R/W

Bit 76543210

Name

LED

Configura-

tion

Reserved LED2 Blink Rate LED1 Blink Rate

Reset 00000000

Bit Description

7 LED Conﬁguration

0: One dual-colored LED (default at V

power-up reset)

1: Two LEDs

6 Reserved

5-3 LED2 Blink Rate

Bits 5 4 3 Rate Duty Cycle

(Hz)

0 0 0 Off Always low 0 0 1 0.25 12.5% 0 1 0 0.5 25% 0 1 1 1 50%

Note 1.

1 0 0 2 50% 1 0 1 3 50% 1 1 0 4 50% 1 1 1 On Always high (default at V

power-up reset)

Note 1. When hardware mode 1 is selected, this rate will be set when V

is powered up or when VDDbecomes

inactive while VSB is active.

2-0 LED1 Blink Rate

Bits 2 1 0 Rate Duty Cycle

(Hz)

0 0 0 Off Always low (default at V

power-up reset) 0 0 1 0.25 12.5% 0 1 0 0.5 25% 0 1 1 1 50% 1 0 0 2 50% 1 0 1 3 50% 1 1 0 4 50% 1 1 1 On Always high

2.0 Device Architecture and Configuration (Continued)

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2.7.13 SuperI/O Configuration D Register (SIOCFD)

This is a battery-backed register. Location: Index 2Dh Type: Varies per bit

Bit 76543210 Name

LEDPolarity

Control

Reserved

Reset 00000000

Bit Description

7 LED Polarity Control. This is a R/W bit. It determines if the LED outputs are active high or active low when

they are lit. 0: Active high (default at V

power-up reset)

1: Active low

6-0 Reserved

2.0 Device Architecture and Configuration (Continued)

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2.8 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION

2.8.1 General Description

The generic FDC is a standard FDC with a digital data separator, and is DP8473 and N82077 software compatible. The PC87360 FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter, including:

●

FM and MFM modes are supported. To select either mode, set bit 6 of the ﬁrst command byte when writing to/reading from a diskette, where: 0 = FM mode 1 = MFM mode

●

A logic 1 is returned for all ﬂoating (TRI-STATE) FDC register bits upon LPC I/O read cycles.

Exceptions to standard FDC support include:

●

Automatic media sense is not supported (MSEN0-1 pins are not implemented)

●

DRATE1 is not supported.

Table 16 lists the FDC functional block registers.

Table 16. FDC Registers

2.8.2 Logical Device 0 (FDC) Configuration

Table 17 lists theConfigurationregisterswhichaffecttheFDC.Onlythelasttwo registers (F0h and F1h) are described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 17. FDC Conﬁguration Registers

Offset

Note 1.

Note 1. This is the 8-byte aligned FDC base address.

Mnemonic Register Name Type

00h SRA Status A RO 01h SRB Status B RO 02h DOR Digital Output R/W 03h TDR Tape Drive R/W 04h MSR Main Status R

DSR Data Rate Select W 05h FIFO Data (FIFO) R/W 06h N/A X 07h DIR Digital Input R

CCR Conﬁguration Control W

Index Conﬁguration Register or Action Type Reset

30h Activate. See also bit 0 of the SIOCF1 register and bit 0 of the SIOCF6 register. R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 03h 61h Base Address LSB register. Bits 2 and 0 (for A2 and A0) are read only, 00b. R/W F2h 70h Interrupt Number and Wake-Up on IRQ Enable register R/W 06h 71h Interrupt Type. Bit 1 is read/write; other bits are read only. R/W 03h 74h DMA Channel Select R/W 02h

75h Report no second DMA assignment RO 04h F0h FDC Conﬁguration register R/W 24h F1h Drive ID register R/W 00h

2.0 Device Architecture and Configuration (Continued)

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2.8.3 FDC Configuration Register

This register is reset by hardware to 24h. Location: Index F0h Type: R/W

Bit 76543210

Name Reserved

TDR

Mode

DENSEL

Polarity Control

Reserved

Write

Protect

PC-AT or

PS/2 Drive

Mode Select

Reserved

TRI-STATE

Control

Reset 00100100 Required 0 0

Bit Description

7 Reserved. Must be 0. 6 TDR Register Mode

0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are 111111b (default) 1: Enhanced drive mode

5 DENSEL Polarity Control

0: Active low for 500 Kbps or 1 Mbps data rates

1: Active high for 500 Kbps or 1 Mbps data rates (default) 4 Reserved. Must be 0. 3 Write Protect. This bit allows forcing of write protect functionality by software. When set, writes to the floppy

disk drive are disabled. This effect is identical to

WP when it is active.

0: Write protected according to

WP signal (default)

1: Write protected regardless of value of

WP signal

2 PC-AT or PS/2 Drive Mode Select

0: PS/2 drive mode

1: PC-AT drive mode (default) 1 Reserved 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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2.8.4 Drive ID Register

This read/write register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in the Enhanced mode.

Location: Index F1h Type: R/W

Usage Hints: Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register in the Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic media sense, bits 1 and/or 3 of the Drive ID register should be set to 1 respectively (to indicate non-valid media sense) when the corresponding drive isselectedandtheDriveIDbitisreflectedonbit5of the TDR register in the Enhanced mode.

Bit 76543210 Name Reserved Drive 1 ID Drive 0 ID Reset 00000000

Bit Description

7-4 Reserved 3-2 Drive 1 ID. When drive 1 is accessed, these bits are reﬂected on bits 5-4 of the TDR register, respectively. 1-0 Drive 0 ID. When drive 0 is accessed, these bits are reﬂected on bits 5-4 of the TDR register, respectively.

2.0 Device Architecture and Configuration (Continued)

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2.9 PARALLEL PORT CONFIGURATION

2.9.1 General Description

The PC87360 Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).

The Parallel Port includes two groups of runtime registers, as follows:

• A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h)

are used only in the Extended ECP mode.

• A group of four registers, used only in the Extended ECP mode, accessed by a second level offset.

The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime registers are used and which address bits are used for the base address. See Tables 18 and 19 for a listing of all registers, their offset addresses, and the associated modes.

Table 18. Parallel Port Registers at First Level Offset

Table 19. Parallel Port Registers at Second Level Offset

Offset Mnemonic Mode(s) Type Register Name

00h DATAR 0,1 R/W Data

AFIFO 3 W ECP FIFO (Address)

DTR 4 R/W Data (for EPP)

01h DSR 0,1,2,3 RO Status

STR 4 RO Status (for EPP)

02h DCR 0,1,2,3 R/W Control

CTR 4 R/W Control (for EPP) 03h ADDR 4 R/W EPP Address 04h DATA0 4 R/W EPP Data Port 0 05h DATA1 4 R/W EPP Data Port 1 06h DATA2 4 R/W EPP Data Port 2 07h DATA3 4 R/W EPP Data Port 3

400h CFIFO

DFIFO

TFIFO

CNFGA

2 3 6 7

W R/W R/W

PP Data FIFO ECP Data FIFO Test FIFO

Conﬁguration A 401h CNFGB 7 RO Conﬁguration B 402h ECR 0,1,2,3 R/W Extended Control 403h

EIR

Note 1.

Note 1. These registers are extended to the standard IEEE1284 registers. They are

accessible only when enabledby bit 4 of the Parallel Port Conﬁguration register (see Section 2.9.3).

0,1,2,3 R/W Extended Index

404h

EDR

0,1,2,3 R/W Extended Data

405h

EAR

0,1,2,3 R/W Extended Auxiliary Status

Offset Mnemonic Type Register Name

00h Control0 R/W Extended Control 0 02h Control2 R/W Extended Control 1 04h Control4 R/W Extended Control 4 05h PP Confg0 R/W Conﬁguration 0

2.0 Device Architecture and Configuration (Continued)

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2.9.2 Logical Device 1 (PP) Configuration

Table 20 lists the configuration registers which affect the Parallel Port. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 20. Parallel Port Conﬁguration Registers

2.9.3 Parallel Port Configuration Register

This register is reset by hardware to F2h. Location: Index F0h Type: R/W

Index Conﬁguration Register or Action Type Reset

30h Activate. See also bit 0 of the SIOCF1 register. R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for

A10) should be 0b.

R/W 02h

61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP

Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.

R/W 78h

70h Interrupt Number and Wake-Up on IRQ Enable register R/W 07h 71h Interrupt Type

Bits 7-2 are read only. Bit 1 is a read/write bit. Bit 0 is read only. It reﬂects the interrupt type dictated by the Parallel Port operation

mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge interrupt) in all other modes.

R/W 02h

74h DMA Channel Select R/W 04h 75h Report no second DMA assignment RO 04h F0h Parallel Port Conﬁguration register R/W F2h

Bit 76543210

Name Reserved

Extended

Access

Reserved

Power

Mode

Control

TRI-STATE

Control

Reset 11110010 Required 1 1 1

Bit Description

7-5 Reserved. Must be 11.

4 Extended Register Access

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored). 1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-

time conﬁguration within the Parallel Port address space.

3-2 Reserved

1 Power Mode Control. When the logical device is active:

0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active.

Registers are maintained.

1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default).

0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default) 1: Enabled

2.0 Device Architecture and Configuration (Continued)

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2.10 SERIAL PORT 2 CONFIGURATION

2.10.1 General Description

Serial Port 2 includes IR functionality as described in the Serial Port 2 with IR chapter.

2.10.2 Logical Device 2 (SP2) Configuration

Table 21 lists the configuration registers which affect the Serial Port 2. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 21. Serial Port 2 Conﬁguration Registers

2.10.3 Serial Port 2 Configuration Register

This register is reset by hardware to 02h. Location: Index F0h Type: R/W

Index Conﬁguration Register or Action Type Reset

30h Activate. See also bit 0 of the SIOCF1 register and bit 2 of the SIOCF6 register. R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 02h 61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b. R/W F8h 70h Interrupt Number and Wake-Up on IRQ Enable register R/W 03h 71h Interrupt Type. Bit 1 is R/W; other bits are read only. R/W 03h 74h DMA Channel Select 0 (RX_DMA) R/W 04h 75h DMA Channel Select 1 (TX_DMA) R/W 04h F0h Serial Port 2 Conﬁguration register R/W 02h

Bit 76543210

Name

Bank

Select

Enable

Reserved

Busy

Indicator

Power

Mode

Control

TRI-STATE

Control

Reset 00000010

Bit Description

7 Bank Select Enable. Enables bank switching for Serial Port 2.

0: All attempts to access the extended registers in Serial Port 2 are ignored (default). 1: Enables bank switching for Serial Port 2.

6-3 Reserved

2 Busy Indicator. This read only bit can be used by power management software to decide when to power-down

the Serial Port 2 logical device. 0: No transfer in progress (default). 1: Transfer in progress.

1 Power Mode Control. When the logical device is active in:

0: Low power mode

Serial Port 2 Clock disabled. The output signals are set to their default states. The

RI input signal can be programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also prevents access to Serial Port 2 registers.)

1: Normal power mode

Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default).

0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

One exception is the IRTX pin, which is driven to 0 when Serial Port 2 is inactive and is not affected by this bit. 0: Disabled (default) 1: Enabled

2.0 Device Architecture and Configuration (Continued)

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2.11 SERIAL PORT 1 CONFIGURATION

2.11.1 Logical Device 3 (SP1) Configuration

Table 22 lists the configuration registers which affect the Serial Port 2. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 22. Serial Port 1 Conﬁguration Registers

2.11.2 Serial Port 1 Configuration Register

This register is reset by hardware to 02h. Location: Index F0h Type: R/W

Index Conﬁguration Register or Action Type Reset

30h Activate. See also bit 0 of the SIOCF1 register and bit 3 of the SIOCF6 register. R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 03h 61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b. R/W F8h 70h Interrupt Number and Wake-Up on IRQ Enable register R/W 04h 71h Interrupt Type. Bit 1 is R/W; other bits are read only. R/W 03h 74h Report no DMA Assignment RO 04h 75h Report no DMA Assignment RO 04h F0h Serial Port 1 Conﬁguration register R/W 02h

Bit 76543210

Name

Bank Select Enable

Reserved

Busy

Indicator

Power

Mode

Control

TRI-STATE

Control

Reset 00000010

Bit Description

7 Bank Select Enable. Enables bank switching for Serial Port 1.

0: Disabled (default). 1: Enabled

6-3 Reserved

2 Busy Indicator. This read only bit can be used by power management software to decide when to power-down

the Serial Port 1 logical device. 0: No transfer in progress (default). 1: Transfer in progress.

1 Power Mode Control. When the logical device is active in:

0: Low power mode

Serial Port 1 Clock disabled. The output signals are set to their default states. The

RI input signal can be programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also prevents access to Serial Port 1 registers.)

1: Normal power mode

Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default).

0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default) 1: Enabled

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2.12 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION

2.12.1 Logical Device 4 (SWC) Configuration

Table 23 lists the configuration registers which affect the SWC. See Sections 2.2.3 and 2.2.4 for a detailed description of these registers.

Table 23. System Wake-Up Control (SWC) Conﬁguration Registers

Index Conﬁguration Register or Action Type Reset

30h Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

Note 1.

Note 1. The logical device registers are maintained, and all wake-up detection mechanisms are func-

tional.

R/W 00h

60h Base Address MSB register R/W 00h 61h Base Address LSB register. Bits 4-0 (for A4-0) are read only, 00000b. R/W 00h 70h Interrupt Number R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h

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2.13 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION

2.13.1 General Description

The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse controller (Logical Device 5) and a Keyboard controller (Logical Device 6).

The hardware KBC module is integrated to provide the following pin functions: P12, P16, P17, KBRST (P20), GA20 (P21), KBDAT, KBCLK, MDAT, and MCLK. KBRST and GA20 are implemented as bi-directional, open-drain pins. The Keyboard and Mouse interfaces are implemented asbi-directional, open-drain pins. Their internal connections areshown in Figure 5.

P10, P11, P13-P15, P22-P27 of the KBC core are not available on dedicated pins; neither are T0 and T1. P10, P11, P22, P23, P26, P27, T0 and T1 are used to implement the Keyboard and Mouse interface.

Internal pull-ups are implemented only on P12, P16 and P17. The KBC executes a program fetched from an on-chip 2Kbyte ROM. The code programmed in this ROM is user-customiz-

able. The KBC has two interrupt request signals: one for the Keyboard and one for the Mouse. The interrupt requests are implemented using ports P24 and P25 of the KBC core. The interrupt requests are controlled exclusively by the KBC firmware, except for the type and number, which are affected by configuration registers (see Section 2.13.2 24).

The interrupt requests are implemented as bi-directional signals. When an I/O port is read, all unused bits return the value latched in the output registers of the ports.

For KBC firmware that implements interrupt-on-OBF schemes, it is recommended to implement it as follows:

1. Put the data in DBBOUT.

2. Set the appropriate port bit to issue an interrupt request.

Figure 5. Keyboard and Mouse Interfaces

KBD IRQ

Mouse IRQ

KBC

KBCLK

KBDAT

P10

MCLK

MDAT

P11

P26

P27

P23

P22

STATUS

DBBIN

DBBOUT

Matrix

P24

P25

P20 P21

P12

Internal Interface Bus

KBRST GA20

P12

P17

P16

2.0 Device Architecture and Configuration (Continued)

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2.13.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration

Tables 24 and 25listtheconfigurationregisterswhichaffecttheMouseandthe Keyboard respectively. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 24. Mouse Conﬁguration Registers

Table 25. Keyboard Conﬁguration Registers

Index Mouse Conﬁguration Register or Action Type Reset

30h Activate. See also bit 0 of the SIOCF1. When the Mouse of the KBC is inactive, the

IRQ selected by the Mouse Interrupt Number and Wak e-Up on IRQ Enable register (index 70h) is not asserted. This register has no effect on host KBC commands handling the PS/2 Mouse.

R/W 00h

70h Mouse Interrupt Number and Wake-Up on IRQ Enable register R/W 0Ch 71h Mouse Interrupt Type. Bits 1,0 are read/write; other bits are read only. R/W 02h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h

Index Keyboard Conﬁguration Register or Action Type Reset

30h Activate. See also bit 0 of the SIOCF1. R/W 01h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 00h 61h Base Address LSB register. Bits 2-0 are read only 000b. R/W 60h 62h Command Base Address MSB register. Bits 7-3 (for A15-11) are read only,

00000b.

R/W 00h

63h Command Base Address LSB. Bits 2-0 are read only 100b. R/W 64h 70h KBD Interrupt Number and Wake-Up on IRQ Enable register R/W 01h 71h KBD Interrupt Type. Bits 1,0 are read/write; others are read only. R/W 02h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h F0h KBC Conﬁguration register R/W 40h

2.0 Device Architecture and Configuration (Continued)

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2.13.3 KBC Configuration Register

This register is reset by hardware to 40h. Location: Index F0h Type: R/W

Usage Hints:

1. To change the clock frequency of the KBC, perform the following: a. Disable the KBC logical devices. b. Change the frequency setting. c. Enable the KBC logical devices.

Bit 76543210 Name KBC Clock Source Reserved

TRI-STATE

Control

Reset 01000000 Required 0

Bit Description 7-6 KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled).

Bits 7 6 Source

0 0 8 MHz 0 1 12 MHz (default) 1 0 16 MHz 1 1 Reserved

5-1 Reserved

0 TRI-STATE Control. If KBD is inactive (disabled) when this bit is set, the KBD pins (KBCLK and KBDAT) are in TRI-

STATE. If Mouse is inactive (disabled) when this bit is set, the Mouse pins (MCLK and MD AT) are in TRI-ST ATE. 0: Disabled (default) 1: Enabled

2.0 Device Architecture and Configuration (Continued)

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2.14 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION

2.14.1 General Description

The GPIO functional block includes 37 pins, arranged in four 8-bit ports (ports 0, 1, 2 and 4) and one 5-bit port (port 3). All pins in port 0 are I/O, and have full event detection capability, enabling them to trigger the assertion of IRQ,

SMI and PWUREQ signals. With the exception of bit 5 which is output only, port 1pinsarealsoI/Owithfulleventdetectioncapability. All pins in ports 2 and 3 are I/O, but none of them has event detection capability. The sixteen runtime registers associated withthefiveportsare arranged intheGPIOaddressspace as shown inTable26.The GPIO base addressis16-bytealigned. Address bits 3-0 are used to indicate the register offset.

Table 26. Runtime Registers in GPIO Address Space

2.14.2 Implementation

The standard GPIO port with event detection capability (such as ports 0, 1 and 4) has four runtime registers. Each pin is associated with a GPIO Pin Configuration register that includes seven configuration bits. Ports 2 and 3 are non-standard ports that do not support event detection, and therefore differ from the generic model as follows:

●

They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers GPEVEN2/3 and GPEVST2/3 are not available.

●

Only bits 3-0 are implemented in the GPIO Pin Conﬁguration registers of ports 2 and 3. Bits 6-4, associated with the event detection functionality, are reserved.

Offset Mnemonic Register Name Port Type

00h GPDO0 GPIO Data Out 0 0 R/W 01h GPDI0 GPIO Data In 0 RO 02h GPEVEN0 GPIO Event Enable 0 R/W 03h GPEVST0 GPIO Event Status 0 R/W1C 04h GPDO1 GPIO Data Out 1 1 R/W 05h GPDI1 GPIO Data In 1 RO 06h GPEVEN1 GPIO Event Enable 1 R/W 07h GPEVST1 GPIO Event Status 1 R/W1C 08h GPDO2 Data Out 2 2 R/W

09h GPDI2 Data In 2 RO 0Ah GPDO3 Data Out 3 3 R/W 0Bh GPDI3 Data In 3 RO 0Ch GPDO4 GPIO Data Out 4 4 R/W 0Dh GPDI4 GPIO Data In 4 RO 0Eh GPEVEN4 GPIO Event Enable 4 R/W

0Fh GPEVST4 GPIO Event Status 4 R/W1C

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2.14.3 Logical Device 7 (GPIO) Configuration

Table 27 lists the configuration registers whichaffectthe GPIO. Only the last three registers (F0h -F2h) are described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 27. GPIO Conﬁguration Register

Figure shows the organization of these registers.

Figure 6. Organization of GPIO Pin Registers

Index Conﬁguration Register or Action Type Reset

30h Activate. See also bit 7 of the SIOCF1 register. R/W 00h 60h Base Address MSB register R/W 00h 61h Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b. R/W 00h 70h Interrupt Number R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h F0h GPIO Pin Select register R/W 00h F1h GPIO Pin Conﬁguration register R/W 00h F2h GPIO Pin Event Routing register R/W 00h

GPIO Pin

Conﬁguration Register

Pin Select

Port Select

Port 0, Pin 0

GPIO Pin Select Register

GPIO Pin Event

Routing Register

Port 0, Pin 7

Port 0

Port 4

Pin 0

Pin 7

Port 1, Pin 0

Port 2, Pin 0

Port 3, Pin 0

Port 4, Pin 0

Port 0

Pin 0

Pin 7

Port 1

Port 4

Port 0, Pin 0

Port 1, Pin 0

Port 4, Pin 0

Port 0, Pin 7

Conﬁguration Registers

(Index F0h)

(Index F1h)

(Index F2h)

Event Routing

Registers

2.0 Device Architecture and Configuration (Continued)

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2.14.4 GPIO Pin Select Register

This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the GPIO Pin Configuration register). It is reset by hardware to 00h.

Location: Index F0h Type: R/W

Bit 76543210 Name Reserved Port Select Reserved Pin Select Reset 00000000

Bit Description

7 Reserved

6-4 Port Select. These bits select the GPIO port to be configured:

000: Port 0 (default) 001, 010, 011,100: Binary value of port numbers 1-4 respectively. All other values are reserved.

3 Reserved

2-0 Pin Select. These bits select the GPIO pin to be conﬁgured in the selected port:

000, 001, ... 111: Binary value of the pin number, 0, 1, ... 7 respectively (default=0)

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2.14.5 GPIO Pin Configuration Register

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO Pin registers that are accessed via this register have a common bitstructure,asshownbelow. This register is reset by hardware to 44h, except for ports 2 and 3, that are reset to 04h.

Location: Index F1h Type: R/W

Ports: 0,1 and 4 (with event detection capability)

Ports 2 and 3 (without event detection capability)

Bit 76543210

Name Reserved

Event

Debounce

Enable

Event

Polarity

Event Type Lock

Pull-Up

Control

Output

Type

Output Enable

Reset 01000100

Bit 76543210 Name Reserved Lock

Pull-Up

Control

Output

Type

Output Enable

Reset 00000100

Bit Description

7 Reserved 6 Event Debounce Enable. (Ports 0,1 and 4 with event detection capability). Enables transferring the signal only

after a predetermined debouncing period of time. 0: Disabled 1: Enabled (default) Reserved. (Ports 2 and 3). Always 0.

5 Event Polarity. (Ports 0,1 and 4 with event detection capability). This bit deﬁnes the polarity of the signal that

issues an interrupt from the corresponding GPIO pin (falling/low or rising/high). 0: Falling edge or low level input (default) 1: Rising edge or high level input Reserved. (Ports 2 and 3). Always 0.

4 Event Type. (Ports 0,1 and 4 with event detection capability). This bit deﬁnes the type of the signal that issues

an interrupt from the corresponding GPIO pin (edge or level). 0: Edge input (default) 1: Level input Reserved. (Ports 2 and 3). Always 0.

3 Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to

0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O Conﬁguration 3 register, SIOCF3).

0: No effect (default) 1: Direction, output type, pull-up and output value locked

2 Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.

It supports open-drain output signals with internal pull-ups and TTL input signals 0: Disabled 1: Enabled (default)

1 Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.

0: Open-drain (default) 1: Push-pull

0 Output Enable. This bit indicates the GPIO pin output state. It has no effect on the input path.

0: TRI-STATE (default) 1: Output enabled

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2.14.6 GPIO Event Routing Register

This register enables the routing of the GPIO event to IRQ,

SMI and/or PWUREQ signals. It is implemented only for ports

0,1 and 4 which have event detection capability. This register is reset by hardware to 00h. Location: Index F2h Type: R/W

Bit 76543210

Name Reserved

Enable

PWUREQ

Routing

Enable

SMI

Routing

Enable IRQ

Routing

Reset 00000001

Bit Description

7-3 Reserved

2 Enable

PWUREQ Routing

0: Disabled (default) 1: Enabled

1 Enable

SMI Routing

0: Disabled (default) 1: Enabled

0 Enable IRQ Routing

0: Disabled 1: Enabled (default)

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2.15 ACCESS.BUS INTERFACE (ACB) CONFIGURATION

2.15.1 General Description

The ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. The ACB uses a 24 MHz internal clock.

The six runtime registers are shown below.

Table 28. ACB Runtime Registers

2.15.2 Logical Device 8 (ACB) Configuration

Table 29 lists the configuration registers which affect the ACB. Only the last register (F0h) is described here. See Sections

2.2.3 and 2.2.4 for a detailed description of the others.

Table 29. ACB Conﬁguration Registers

Offset Mnemonic Register Name Type

00h ACBSDA ACB Serial Data R/W 01h ACBST ACB Status Varies per bit 02h ACBCST ACB Control Status Varies per bit 03h ACBCTL1 ACB Control 1 R/W 04h ACBADDR ACB Own Address R/W 05h ACBCTL2 ACB Control 2 R/W

Index Conﬁguration Register or Action Type Reset

30h Activate. See also bit 0 of the SIOCF1 register. R/W 00h 60h Base Address MSB register R/W 00h 61h Base Address LSB register. Bits 2-0 (for A2-0) are read only, 000b. R/W 00h 70h Interrupt Number and Wake-Up on IRQ Enable register R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h F0h ACB Conﬁguration register R/W 00h

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2.15.3 ACB Configuration Register

This register is reset by hardware to 00h. Location: Index F0h Type: R/W

Bit 76543210

Name Reserved

Internal

Pull-Up

Enable

Reserved

Reset 00000000

Bit Description

7-3 Reserved

2 Internal Pull-Up Enable

0: No internal pull-up resistors on SCL and SDA (default) 1: Internal pull-up resistors on SCL and SDA

1-0 Reserved

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2.16 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION

2.16.1 General Description

This module includes two Fan Speed Control units and two Fan Speed Monitor units. The 10 runtime registers of the four functional blocks are arranged in the address space shown in Table 30. The base address is 16-byte aligned. Address bits 0-3 are used to indicate the register offset.

Table 30. Runtime Registers in FSCM Address Space

2.16.2 Logical Device 9 (FSCM) Configuration

Table 31 lists the configuration registers which affect the Fan Speed Controls and the Fan Speed Monitors. Only the last one (F0h) is described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 31. FSCM Conﬁguration Registers

Offset Mnemonic Register Name Function

00h FCPSR0 Fan Control 0 Pre-Scale Fan Speed Control 0 01h FCDCR0 Fan Control 0 Duty Cycle 02h FCPSR1 Fan Control 1 Pre-Scale Fan Speed Control 1 03h FCDCR1 Fan Control 1 Duty Cycle

04h-05h Reserved

06h FMTHR0 Fan Monitor 0 Threshold Fan Speed Monitor 0 07h FMSPR0 Fan Monitor 0 Speed 08h FMCSR0 Fan Monitor 0 Control & Status 09h FMTHR1 Fan Monitor 1 Threshold Fan Speed Monitor 1 0Ah FMSPR1 Fan Monitor 1 Speed 0Bh FMCSR1 Fan Monitor 1 Control & Status

0Ch-0Fh Reserved

Index Conﬁguration Register or Action Type Reset

30h Activate. See also bit 0 of the SIOCF1 register. R/W 00h 60h Base Address MSB register R/W 00h 61h Base Address LSB register. Bit 3-0 (for A3-0) are read only, 0000b. R/W 00h 70h Interrupt Number and Wake-Up on IRQ Enable register R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h F0h Fan Speed Control and Monitor Conﬁguration 1 register R/W 00h

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2.16.3 Fan Speed Control and Monitor Configuration 1 Register

This register is reset by hardware to 00h. Location: Index F0h Type: R/W

Bit 76543210

Name

Fan Speed

Invert 1

Enable

Fan Speed

Control 1

Enable

Fan Speed

Monitor 1

Enable

Fan Speed

Invert 0

Enable

Fan Speed

Control 0

Enable

Fan Speed

Monitor 0

Enable

Reserved

TRI-STATE

Control

Reset 00000000

Bit Description

7 Fan Speed Invert 1 Enable

0: Disabled (default) 1: Enabled

6 Fan Speed Control 1 Enable

0: Disabled (default) 1: Enabled

5 Fan Speed Monitor 1 Enable

0: Disabled (default) 1: Enabled

4 Fan Speed Invert 0 Enable

0: Disabled (default) 1: Enabled

3 Fan Speed Control 0 Enable

0: Disabled (default) 1: Enabled

2 Fan Speed Monitor 0 Enable

0: Disabled (default)

1: Enabled 1 Reserved 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

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2.17 WATCHDOG TIMER (WDT) CONFIGURATION

2.17.1 Logical Device 10 (WDT) Configuration

Table 32 lists the configuration registerswhich affect the WATCHDOG Timer. Only the lastregister (F0h) is described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 32. WDT Conﬁguration Registers

2.17.2 WATCHDOG Timer Configuration Register

This register is reset by hardware to 02h. Location: Index F0h Type: R/W

Index Conﬁguration Register or Action Type Reset

30h Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W 00h

60h Base Address MSB register R/W 00h

61h Base Address LSB register. Bits 1 and 0 (for A1 and A0) are read only, 00b. R/W 00h

70h Interrupt Number (for routing the

WDO signal) and Wake-Up on IRQ Enable

R/W 00h

71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h

74h Report no DMA assignment RO 04h

75h Report no DMA assignment RO 04h

F0h WATCHDOG Timer Conﬁguration register R/W 02h

Bit 76543210

Name Reserved

Output

Type

Internal

Pull-Up

Enable

Power

Mode

Control

TRI-STATE

Control

Reset 00000010

Bit Description

7-4 Reserved

3 Output Type. This bit controls the buffer type (open-drain or push-pull) of the

WDO pin. 0: Open-drain (default) 1: Push-pull

2 Internal Pull-Up Enable. This bit controls the internal pull-up resistor on the

WDO pin. 0: Disabled (default) 1: Enabled

1 Power Mode Control

0: Low power mode:

WATCHDOG Timer clock disabled.

WDO output signal is set to 1. Registers are accessible and maintained

(unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers).

1: Normal power mode:

WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default).

0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default) 1: Enabled

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3.0 System Wake-Up Control (SWC)

3.1 OVERVIEW

The SWC recognizes the following maskable system events:

●

Modem ring (RI1 and RI2 pins)

●

Telephone ring (RING input pin)

●

Keyboard activity or speciﬁc programmable key sequence

●

Mouse activity or speciﬁc programmable sequence of clicks and movements

●

Programmable Consumer Electronics IR (CEIR) address

●

Wake-up on module IRQs for FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB, Fan Speed Control and Monitor (FSCM) and WATCHDOG Timer (WDT)

●

Eight VSB-powered, general-purpose input events (via GPIOE0-5 and GPIE6-7)

●

23 VDD-powered, GPIO-triggered events (via GPIO00-07, GPIO10-14, GPIO16-17 and GPIO40-47)

●

Software event.

The SWC notifies the device when any of these events occur by asserting one or more of the following output pins:

●

Power-Up Request (PWUREQ)

●

System Management Interrupt (SMI)

●

Interrupt Request (via SERIRQ)

Figure 7 shows the block diagram of the SWC.

Figure 7. SWC Block Diagram

In addition to the event detection and system notification capabilities, the SWC operates several general-purpose I/O pins powered by VSB. These pins can be used to perform various tasks while VSB is present and VDD is not.

3.2 FUNCTIONAL DESCRIPTION

The SWC monitors 16 system events or activities. Upon entering the SWC, the events pass through a filter (where applicable) and polarity adjustment logic.After filtering and polarity adjustment, eachevent enters the Wake-Up Mode Control (Extension) Logic which determines its effect during the various system power states. See Figure 7 for an illustration of this mechanism.

Filters

and

Polarity

Selection

Wake-Up

Extension

Mechanism

Wake-Up Event

Detection

and Routing

Wake-Up Event Sources

SWC IRQ SWC SMI

PWUREQ

16 16

Wake-Up

Extension

Enable

Registers

Wake-Up

Configuration

and Control

Registers

ACPI

Enable, Status

and Routing

Registers

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After the wake-up mode is determined for all events, each one of them is fed into a dedicated detector thatdetermineswhen this event is active, according to predetermined (either fixed or programmable) criteria. A set of dedicated registers is used to determine the wake-up criteria, including the CEIR address and the keyboard sequence.

Two Wake-Up Events Status registers (WK_STSn) hold a Status bit for each of the 16 events. Six Wake-Up Events Routing Control register s (WK_ENn WK_SMIENn and WK_IRQENn) hold three Routing Enable bits

for each of the 16 events, to allow selective routing of these events to

PWUREQ, SMI and/or the assigned SWC interrupt

request (IRQ) channel. Upon detection of any active event,the corresponding Status bit is set to1, regardless of any Routing Enable bit.If both the

Status bit and a Routing Enable bit corresponding to a specific event are set to 1 (no matter in what order), the output pin corresponding to that Routing Enable bit is asserted. The Status bit is deasserted by writing 1 to it. Writing 0 to a Routing Enable bitofanevent prevents it from issuingthecorrespondingsystemnotification, but does notaffecttheStatusbit. Figure 8 show the routing scheme of detected wake-up events to the various means of system notification.

Figure 8. Wake-Up Events Routing Scheme

To enable the assertion of

SMI by detected wake-up events,it is necessary to either selectthe SMI function on a device pin

or route it to an interrupt request channel via the device’s configuration registers.

Event i

Detection

WK_SMIENn.i

WK_IRQENn.i

WK_ENn.i

Wake-Up Event i

From Wake-Up

PWUREQ

SMI

IRQ

Event Routing Logic

WK_STSn.i

Extesion Logic

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Four Wake-Up Extension Enable registers (WK_X1EN0, 1 and WK_X2EN0,1)holdtwo configuration bits for each of the 16 events to control the wake-up mode for each one of them. Figure 9 illustrates the Wake-Up Mode Control (Extension) mechanism.

Figure 9. Wake-Up Mode Control (Extension) Mechanism

In addition to monitoring various system events, the SWC operates several general-purpose I/O (GPIO) pins powered by V

. Two runtime data registers (SB_GPDO0 and SBGPDI0) hold a Data Out bit and a Data In bit for each VSBpowered GPIO pin. In addition, each GPIO pin has a dedicated configuration register that controls its characteristics. These configuration registers are accessed via a set of Standby GPIO Pin Select and Pin Configuration registers (SBGPSEL and SBGPCFG). For a detailed description of the V

powered GPIO pins, see Section 3.4.28.

The SWC logic is powered by V

. The SWC control and configuration registers are battery backed, powered by VPP. The

setup of the wake-up events, includingprogrammable sequences, is retained throughout power failures (noV

) as long as

the battery is connected. V

is taken from VSBif VSBis greater than the minimum (Min) value defined in the

Device Char-

acteristics

chapter; otherwise, V

BAT

is used as the VPP source.

Hardware reset does not affect these registers. They are reset only by software reset or power-up of V

3.3 EVENT DETECTION

3.3.1 Modem Ring

High to low transitions on

RI1 or RI2 indicate the detection of ring in external modem connected to Serial Port 1 or Serial

Port 2, respectively, and can be used as wake-up events.

3.3.2 Telephone Ring

A telephone ring is detected by theSWC by processing the raw signal coming directly fromthe telephone line into the

RING input pin. Detection of a pulse-train with a frequency higher than 16 Hz that lasts at least 0.19 sec, is used as a wake-up event.

The

RING pulse-train detection is achieved by monitoring the falling edges on RING in time slots of 62.5 msec (a 16 Hz

cycle). A positive detection occurs if falling edges of

RING are detected in three consecutive time slots, following a time slot

in which no

RING falling edge is detected. This detection method guarantees the detection of a RING pulse-train with frequencies higher than 16 Hz. It ﬁlters out (does not detect) pulses of less than 10 Hz, and may detect pulses between 10 Hz to 16 Hz.

3.3.3 Keyboard and Mouse Activity

The detection of either any activity or a specific predetermined keyboard or mouse activity can be used as a wake-up event. The keyboard wake-up detection can be programmed to detect:

●

Any keystroke

●

A speciﬁc programmable sequence of up to eight alphanumeric keystrokes

●

Any programmable sequence of up to 8 bytes of data received from the keyboard.

The mouse wake-up detection can be programmed to detecteitherany mouse click or movement, or a specific programmable click (left or right) or double-clicks.

The keyboard or mouse event detection operates independently of the KBC (which is powereddownwiththerest of the system).

WK_X2ENn.i

WK_X1ENn.i

Wake-Up Filtered Event i

VDD Present

To Event i Detection Logic

Post VDD Power-On Silence Post VSB Power-On Silence

3.0 System Wake-Up Control (SWC) (Continued)

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3.3.4 CEIR Address

A CEIR transmission received on an IRRX pin in a pre-selected standard (NEC, RCA or RC-5) is matched against a programmable CEIR address. Detection of matching can be used as a wake-up event.

Whenever an IR signal is detected,the receiver immediately enters the active state. When thishappens, the receiver keeps sampling the IR inputsignal and generates a bit string where a logic 1 indicates an idle condition and a logic 0 indicates the presence of IR energy. The received bit string is de-serialized and assembled into 8-bit characters.

The expected CEIR protocol ofthe received signal should be configured through bits 5,4 at the CEIR Wake-UpControl register (see Section 3.4.20).

The CEIR Wake-Up Address register (IRWAD) holds the unique address to be compared with the addresscontained in the incoming CEIR message. If CEIR is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then the CEIR Event Status bit of the WK_STS0 register is set to 1 (see Section 3.4.2).

The CEIR Address Shift register holds the received address which is compared with the address contained in the IRWAD. The comparisonisaffectedalsobytheCEIR Wake-Up Address Mask register (IRWAM) in whicheachbitdetermineswhether to ignore the corresponding bit in the IRWAD.

If CEIR routing to interrupt request is enabled, the assigned SWC interrupt request may beused to indicate that a complete address has beenreceived.Togetthisinterruptwhenthe address is completely received, the IRWAM should be written with FFh. Once the interrupt is received, the value of the address can be read from the ADSR register.

Another parameter that is usedto determine whether a CEIR signalis to be considered valid isthe bit cell time width. There are four time ranges for the different protocols and carrier frequencies. Four pairs of registers define the low and high limits of each time range. (See Sections 3.4.27 through for more details regarding the recommended values for each protocol.)

The CEIR address detection operates independently of the serial port with the IR (which is powered down with the rest of the system).

3.3.5 Standby General-Purpose Input Events

A general-purpose event is defined as the detection of falling edge, rising edge, low level or high level on a specific signal. Each signal’s event is configurable via software. GPIOE0-5 and GPIE6-7 may trigger a system notification by any of the means mentioned in Section 3.1.

A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software.

3.3.6 GPIO-Triggered Events

A GPIO-triggered event is defined as the detection of falling edge, rising edge, low level or high level on a specific GPIO signal whose status bit is routed to

PWUREQ. Each signal’s event is configurable via software in the GPIO logical device configuration registers. GPIO00-07, GPIO10-14, GPIO16-17 and GPIO40-47 may trigger a system notification only by PWUREQ. Other means of system notiﬁcation triggered by GPIOs are available via the GPIO logical device conﬁguration registers.

A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software. All GPIO pins are powered by V

, and therefore can cause an assertion of PWUREQ only when VDD is present.

3.3.7 Software Event

A software event is defined as writing 1 to the Software Event Status bit of the WK_STS0 register. Once this bit is set to 1, it has the same effect as any other Event Status bit.

Since WK_STS0 is accessible only when V

is present, the Software Event can be activated only when VDD is present.

3.3.8 Module IRQ Wake-Up Event

A module IRQ wake-up event is defined as the leading edge of the IRQ assertion of any of the following logical devices: FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB and Fan Speed Control and Monitor (FSCM).

To enable the IRQ of a specific logical device to trigger a wake-up event, the associated Enable bit must be set to 1. This is bit 4 of the Interrupt Number and Wake-Up on IRQ Enable register, located at index 70h in the configuration space of the logical device (see Table 10 in

Device Architecture and Configuration

chapter). When this bit is set, any IRQ assertion of the corresponding logical device activates the moduleIRQ wake-up event. Therefore, the module IRQwake-up event is a combination of all IRQ signals of the logical devices for which wake-up on IRQ is enabled.

When the event is detected as active, its associated Status bit (bit 7 of the WK0_STS register) is set to 1. If the associated Enable bit (bit 7 of the WK_EN0 register) is also set to 1, the

PWUREQ output is asserted. It remains asserted until the

Status bit is cleared. Since all the logical devices listed above are powered by V

, a module IRQ event can be activated only when VDDis

present.

3.0 System Wake-Up Control (SWC) (Continued)

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3.4 SWC REGISTERS

The SWC registers are organized in four banks, all of which are battery-backed. The offsets are related to a base address that isdeterminedbytheSWCBaseAddress register in the device configuration registers. Thelower19offsetsarecommon to the four banks, while the upper offsets (13-1fh) are divided as follows:

●

Bank 0 holds the Keyboard/Mouse Control registers.

●

Bank 1 holds the CEIR Control registers.

●

Bank 2 holds the Event Routing Conﬁguration and Wake-Up Extension Control registers.

●

Bank 3 holds the Standby General-Purpose I/O (GPIO) Pins Conﬁguration registers.

The active bank is selected through the Configuration Bank Select field (bits 1-0) in the Wake-Up Configuration register (WK_CFG). See Section 3.4.6.

As a programming aid, the registers are described in this chapter according to the following functional groupings:

●

General status, enable, conﬁguration and routing registers

●

Extension enable registers

●

PS/2 event conﬁguration registers

●

CEIR event conﬁguration registers

●

Standby GPIO conﬁguration and control registers

The following abbreviations are used to indicate the Register Type:

●

R/W = Read/Write

●

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different register.

●

W=Write

●

RO = Read Only

●

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

3.4.1 SWC Register Map

The following tables list the SWC registers. For the SWC register bitmap, see Section 3.5.

Table 33. Banks 0, 1, 2 and 3 - The Common Control and Status Register Map

Table 34. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Conﬁguration and Control Register Map

Offset Mnemonic Register Name Type Section

00h WK_STS0 Wake-Up Events Status 0 R/W1C 3.4.2 01h WK_STS1 Wake-Up Events Status 1 R/W1C 3.4.3 02h WK_EN0 Wake-Up Enable 0 R/W 3.4.4 03h WK_EN1 Wake-Up Enable 1 R/W 3.4.5 04h WK_CFG Wake-Up Conﬁguration R/W 3.4.6

05h-07h Reserved

08h SB_GPDO0 Standby GPIOE/GPIE Data Out 0 R/W 3.4.31 09h SB_GPDI0 Standby GPIOE/GPIE Data In 0 RO 3.4.32

0Ah-12h Reserved

Offset Mnemonic Register Name Type Section

13h PS2CTL PS/2 Protocol Control R/W 3.4.16

14h-15h Reserved

16h KDSR Keyboard Data Shift RO 3.4.17 17h MDSR Mouse Data Shift RO 3.4.18

08h-1Fh PS2KEY0-PS2KEY7 PS/2 Keyboard Key Data R/W 3.4.19

3.0 System Wake-Up Control (SWC) (Continued)

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Table 35. Bank 1 - CEIR Wake-Up Conﬁguration and Control Register Map

Table 36. Bank 2 - Event Routing Conﬁguration Register Map

Table 37. Bank 3 - Standby GPIO Pin Conﬁguration Register Map

Offset Mnemonic Register Name Type Section

13h IRWCR CEIR Wake-Up Control R/W 3.4.20 14h Reserved 15h IRWAD CEIR Wake-Up Address R/W 3.4.21 16h IRWAM CEIR Wake-Up Address Mask R/W 3.4.22 17h ADSR CEIR Address Shift R/O 3.4.23 18h IRWTR0L CEIR Wake-Up, Range 0, Low Limit R/W 3.4.24

19h IRWTR0H CEIR Wake-Up, Range 0, High Limit R/W 3.4.24 1Ah IRWTR1L CEIR Wake-Up, Range 1, Low Limit R/W 3.4.25 1Bh IRWTR1H CEIR Wake-Up, Range 1, High Limit R/W 3.4.25 1Ch IRWTR2L CEIR Wake-Up, Range 2, Low Limit R/W 3.4.26 1Dh IRWTR2H CEIR Wake-Up, Range 2, High Limit R/W 3.4.26 1Eh IRWTR3L CEIR Wake-Up, Range 3, Low Limit R/W 3.4.27 1Fh IRWTR3H CEIR Wake-Up, Range 3, High Limit R/W 3.4.27

Offset Mnemonic Register Name Type Section

13h WK_SMIEN0 Wake-Up SMI Enable 0 R/W 3.4.7

14h WK_SMIEN1 Wake-Up SMI Enable 1 R/W 3.4.8

15h WK_IRQEN0 Wake-Up Interrupt Request Enable 0 R/W 3.4.9

16h WK_IRQEN1 Wake-Up Interrupt Request Enable 1 R/W 3.4.10

17h WK_X1EN0 Wake-Up Extension 1 Enable 0 R/W 3.4.11

18h WK_X1EN1 Wake-Up Extension 1 Enable 1 R/W 3.4.12

19h WK_X2EN0 Wake-Up Extension 2 Enable 0 R/W 3.4.13 1Ah WK_X2EN1 Wake-Up Extension 2 Enable 1 R/W 3.4.14

1Bh-1Fh Reserved

Offset Mnemonic Register Name Type Section

13h SBGPSEL Standby GPIO Pin Select R/W 3.4.29

14h SBGPCFG Standby GPIO Pin Conﬁguration R/W 3.4.30

15h-1Fh Reserved

3.0 System Wake-Up Control (SWC) (Continued)

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3.4.2 Wake-Up Events Status Register 0 (WK_STS0)

This register is set to 00h on power-up of V

PP,VSB

or software reset. It indicates which of the corresponding eight wake-up events have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bit 6 of this register has a special type, as described in the table below.

Location: Offset 00h Type: R/W1C

Bit 76543210

Name

Module IRQ

Event

Status

Software

Event

Status

GPIO Event

Status

CEIR

Event

Status

Mouse

Event

Status

KBD

Event

Status

RI2

Event

Status

RI1

Event

Status

Reset 00000000

Bit Description

7 Module IRQ Event Status. This sticky bit shows the status of the module IRQ event detection.

0: Event not active (default) 1: Event active

6 Software Event Status. Writing 1 to this bit inverts its value.

0: Event not active (default) 1: Event active

5 GPIO Event Status. This sticky bit shows the status of the V

GPIO event detection.

0: Event not detected (default) 1: Event detected

4 CEIR Event Status

0: Event not detected (default) 1: Event detected

3 Mouse Event Status

0: Event not detected (default) 1: Event detected

2 KBD Event Status

0: Event not detected (default) 1: Event detected

RI2 Event Status

0: Event not detected (default) 1: Event detected

RI1 Event Status

0: Event not detected (default) 1: Event detected

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3.4.3 Wake-Up Events Status Register (WK_STS1)

This register is set to 00h on power-up of V

PP,VSB

or software reset. It indicates which of the corresponding eight wake-up events have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

Location: Offset 01h Type: R/W1C

Bit 76543210

Name

GPIE7

Event

Status

GPIE6

Event

Status

GPIE5

Event

Status

GPIE4/

RING Event

Status

GPIE3

Event

Status

GPIE2

Event

Status

GPIE1

Event

Status

GPIE0

Event

Status

Reset 00000000

Bit Description

7 GPIE7 Event Status

0: Event not detected (default) 1: Event detected

6 GPIE6 Event Status

0: Event not detected (default) 1: Event detected

5 GPIE5 Event Status

0: Event not detected (default) 1: Event detected

4 GPIE4/

RING Event Status. This sticky bit shows the status of either GPIE4 or RING event detection, according

to the function currently selected on pin 27. 0: Event not detected (default) 1: Event detected

3 GPIE3 Event Status

0: Event not detected (default) 1: Event detected

2 GPIE2 Event Status

0: Event not detected (default) 1: Event detected

1 GPIE1 Event Status

0: Event not detected (default) 1: Event detected

0 GPIE0 Event Status

0: Event not detected (default) 1: Event detected

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3.4.4 Wake-Up Events Enable Register (WK_EN0)

This register is set to 00h on power-up of V

or software reset. Detected wake-up events that are enabled activate the

PWUREQ signal. Location: Offset 02h Type: R/W

Bit 76543210

Name

Module IRQ

Event

Enable

Software

Event

Enable

GPIO Event

Enable

CEIR

Event

Enable

Mouse

Event

Enable

KBD

Event

Enable

RI2

Event

Enable

RI1

Event

Enable

Reset 00000000

Bit Description

7 Module IRQ Event Enable

0: Disabled (default) 1: Enabled

6 Software Event Enable

0: Disabled (default) 1: Enabled

5 GPIO Event Enable

0: Disabled (default) 1: Enabled

4 CEIR Event Enable

0: Disabled (default) 1: Enabled

3 Mouse Event Enable

0: Disabled (default) 1: Enabled

2 KBD Event Enable

0: Disabled (default) 1: Enabled

RI2 Event Enable

0: Disabled (default) 1: Enabled

RI1 Event Enable

0: Disabled (default) 1: Enabled

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3.4.5 Wake-Up Events Enable Register 1 (WK_EN1)

This register is set to 00h on power-up of V

or software reset. Detected wake-up events that are enabled activate the

PWUREQ signal. Location: Offset 03h Type: R/W

Bit 76543210

Name

GPIE7

Event

Enable

GPIE6

Event

Enable

GPIE5

Event

Enable

GPIE4/

RING Event

Enable

GPIE3

Event

Enable

GPIE2

Event

Enable

GPIE1

Event

Enable

GPIE0

Event

Enable

Reset 00000000

Bit Description

7 GPIE7 Event Enable

0: Disabled (default) 1: Enabled

6 GPIE6 Event Enable

0: Disabled (default) 1: Enabled

5 GPIE5 Event Enable

0: Disabled (default) 1: Enabled

4 GPIE4/

RING Event Enable

0: Disabled (default) 1: Enabled

3 GPIE3 Event Enable

0: Disabled (default) 1: Enabled.

2 GPIE2 Event Enable

0: Disabled (default) 1: Enabled

1 GPIE1 Event Enable

0: Disabled (default) 1: Enabled

0 GPIE0 Event Enable

0: Disabled (default) 1: Enabled

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3.4.6 Wake-Up Configuration Register (WK_CFG)

This register is set to 00h on power-up of V

or software reset. It enables access to CEIR registers, keyboard/mouse reg-

isters, Event Routing Control registers or Standby GPIO registers. Location: Offset 04h Type: R/W

Bit 76543210 Name Reserved

Swap KBC

Inputs

Conﬁguration Bank

Select

Reset 00000000 Required 0 0

Bit Description

7-3 Reserved

2 Swap KBC Inputs

0: No swapping (default) 1: KBD (KBCLK, KBDAT) and Mouse (MCLK, MDAT) inputs swapped

1-0 Conﬁguration Bank Select

Bits 1 0 Bank Register

0 0 0 Keyboard/Mouse 0 1 1 CEIR 1 0 2 Event Routing, Wake-Up Extension 1 1 3 Standby GPIO

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3.4.7 Wake-Up Events Routing to SMI Enable Register 0 (WK_SMIEN0)

This register is set to 00h on power-up of V

or software reset. It controls the routing of detected wake-up events to the SMI signal. Detected wake-up events that are enabled activate the SMI signal regardless of the value of the WK_EN0 register.

Location: Bank 2, Offset 13h Type: R/W

Bit 76543210

Name Reserved

Software

Event to

SMI Enable

Reserved

CEIR

Event to

SMI Enable

Mouse

Event to

SMI Enable

KBD

Event to

SMI Enable

RI2

Event to

SMI Enable

RI1

Event to

SMI Enable

Reset 00000000

Bit Description

7 Reserved 6 Software Event to SMI Enable

0: Disabled (default)

1: Enabled 5 Reserved 4 CEIR Event to

SMI Enable

0: Disabled (default)

1: Enabled 3 Mouse Event to

SMI Enable

0: Disabled (default)

1: Enabled 2 KBD Event to

SMI Enable

0: Disabled (default)

1: Enabled 1

RI2 Event to SMI Enable

0: Disabled (default)

1: Enabled 0

RI1 Event to SMI Enable

0: Disabled (default)

1: Enabled

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3.4.8 Wake-Up Events Routing to SMI Enable Register 1 (WK_SMIEN1)

This register is set to 00h on power-up of V

Location: Bank 2, Offset 14h Type: R/W

Bit 76543210

Name

GPIE7

Event to

SMI Enable

GPIE6

Event to

SMI Enable

GPIE5

Event to

SMI Enable

GPIE4/

RING

Event to

SMI Enable

GPIE3

Event to

SMI Enable

GPIE2

Event to

SMI Enable

GPIE1

Event to

SMI Enable

GPIE0

Event to

SMI Enable

Reset 00000000

Bit Description

7 GPIE7 Event to

SMI Enable

0: Disabled (default) 1: Enabled

6 GPIE6 Event to

SMI Enable

0: Disabled (default) 1: Enabled

5 GPIE5 Event to

SMI Enable

0: Disabled (default) 1: Enabled

4 GPIE4/

RING Event to SMI Enable

0: Disabled (default) 1: Enabled

3 GPIE3 Event to

SMI Enable

0: Disabled (default) 1: Enabled.

2 GPIE2 Event to

SMI Enable

0: Disabled (default) 1: Enabled

1 GPIE1 Event to

SMI Enable

0: Disabled (default) 1: Enabled

0 GPIE0 Event to

SMI Enable

0: Disabled (default) 1: Enabled

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3.4.9 Wake-Up Events Routing to IRQ Enable Register 0 (WK_IRQEN0)

This register is set to 00h on power-up of V

or software reset. It controls the routing of detected wake-up events to the assigned SWC interrupt request (IRQ) channel. Detected wake-upevents that are enabled activate the assigned IRQ channel regardless of the value of the WK_EN0 register.

Location: Bank 2, Offset 15h Type: R/W

Bit 76543210

Name Reserved

Software

Event to

IRQ Enable

Reserved

CEIR

Event to

IRQ Enable

Mouse

Event to

IRQ Enable

KBD

Event to

IRQ Enable

RI2

Event to

IRQ Enable

RI1

Event to

IRQ Enable

Reset 00000000

Bit Description

7 Reserved 6 Software Event to IRQ Enable

0: Disabled (default)

1: Enabled 5 Reserved 4 CEIR Event to IRQ Enable

0: Disabled (default)

1: Enabled 3 Mouse Event to IRQ Enable

0: Disabled (default)

1: Enabled 2 KBD Event to IRQ Enable

0: Disabled (default)

1: Enabled. 1

RI2 Event to IRQ Enable

0: Disabled (default)

1: Enabled 0

RI1 Event to IRQ Enable

0: Disabled (default)

1: Enabled

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3.4.10 Wake-Up Events Routing to IRQ Enable Register 1 (WK_IRQEN1)

This register is set to 00h on power-up of V

or software reset. It controls the routing of detected wake-up events to the assigned SWC IRQ channel. Detected wake-up events that are enabled activate the IRQ signal regardless of the value of the WK_EN1 register.

Location: Bank 2, Offset 16h Type: R/W

Bit 76543210

Name

GPIE7

Event to

IRQ Enable

GPIE6

Event to

IRQ Enable

GPIE5

Event to

IRQ Enable

GPIE4/

RING

Event to

IRQ Enable

GPIE3

Event to

IRQ Enable

GPIE2

Event to

IRQ Enable

GPIE1

Event to

IRQ Enable

GPIE0

Event to

IRQ Enable

Reset 00000000

Bit Description

7 GPIE7 Event to IRQ Enable

0: Disabled (default) 1: Enabled

6 GPIE6 Event to IRQ Enable

0: Disabled (default) 1: Enabled

5 GPIOE5 Event to IRQ Enable

0: Disabled (default) 1: Enabled

4 GPIE4/

RING Event to IRQ Enable

0: Disabled (default) 1: Enabled

3 GPIE3 Event to IRQ Enable

0: Disabled (default) 1: Enabled.

2 GPIE2 Event to IRQ Enable

0: Disabled (default) 1: Enabled

1 GPIE1 Event to IRQ Enable

0: Disabled (default) 1: Enabled

0 GPIE0 Event to IRQ Enable

0: Disabled (default) 1: Enabled

3.0 System Wake-Up Control (SWC) (Continued)

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3.4.11 Wake-Up Extension 1 Enable Register 0 (WK_X1EN0)

This register is set to 1Fh on power-up of V

or software reset. It controls the routing of raw wake-up events to event de-

tectors while V

is present. Wake-up events that are enabled are routed to their event detectors while VDD is present. Location: Bank 2, Offset 17h Type: R/W

Bit 76543210

Name Reserved

CEIR

Event Ex. 1

Enable

Mouse

Event Ex. 1

Enable

KBD

Event Ex. 1

Enable

RI2

Event Ex. 1

Enable

RI1

Event Ex.1

Enable

Reset 00011111

Bit Description

7-5 Reserved

4 CEIR Event Extension 1 Enable

0: Disabled 1: Enabled (default)

3 Mouse Event Extension 1 Enable

0: Disabled 1: Enabled (default)

2 KBD Event Extension 1 Enable

0: Disabled 1: Enabled (default)

RI2 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

RI1 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

3.0 System Wake-Up Control (SWC) (Continued)

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3.4.12 Wake-Up Extension 1 Enable Register 1 (WK_X1EN1)

This register is set to FFh on power-up of V

or software reset. It controls the routing of raw wake-up events to event de-

tectors while V

is present. Wake-up events that are enabled are routed to their event detectors while VDD is present. Location: Bank 2, Offset 18h Type: R/W

Bit 76543210

Name

GPIE7

Event Ex. 1

Enable

GPIE6

Event Ex. 1

Enable

GPIE5

Event Ex. 1

Enable

GPIE4/

RING

Event Ex. 1

Enable

GPIE3

Event Ex. 1

Enable

GPIE2

Event Ex. 1

Enable

GPIE1

Event Ex. 1

Enable

GPIE0

Event Ex. 1

Enable

Reset 11111111

Bit Description

7 GPIE7 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

6 GPIE6 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

5 GPIE5 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

4 GPIE4/

RING Event Extension 1 Enable

0: Disabled 1: Enabled (default)

3 GPIE3 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

2 GPIE2 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

1 GPIE1 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

0 GPIE0 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

3.0 System Wake-Up Control (SWC) (Continued)

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3.4.13 Wake-Up Extension 2 Enable Register 0 (WK_X2EN0)

This register is set to 1Fh on power-up of V

or software reset. It controls the routing of raw wake-up events to event de-

tectors while V

is not present. Wake-up events that are enabled are routed to their event detectors while VDDis not

present. Location: Bank 2, Offset 19h Type: R/W

Bit 76543210

Name Reserved

CEIR

Event Ex. 2

Enable

Mouse

Event Ex. 2

Enable

KBD

Event Ex. 2

Enable

RI2

Event Ex. 2

Enable

RI1

Event Ex. 2

Enable

Reset 00011111

Bit Description

7-5 Reserved

4 CEIR Event Extension 2 Enable

0: Disabled 1: Enabled (default)

3 Mouse Event Extension 2 Enable

0: Disabled 1: Enabled (default)

2 KBD Event Extension 2 Enable

0: Disabled 1: Enabled (default)

RI2 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

RI1 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

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3.4.14 Wake-Up Extension 2 Enable Register 1 (WK_X2EN1)

This register is set to FFh on power-up of V

or software reset. It controls the routing of raw wake-up events to event de-

tectors while V

is not present. Wake-up events that are enabled are routed to their event detectors while VDDis not

present. Location: Bank 2, Offset 1Ah Type: R/W

Bit 76543210

Name

GPIE7

Event Ex. 2

Enable

GPIE6

Event Ex. 2

Enable

GPIE5

Event Ex. 2

Enable

GPIE4/

RING

Event Ex. 2

Enable

GPIE3

Event Ex. 2

Enable

GPIE2

Event Ex. 2

Enable

GPIE1

Event Ex. 2

Enable

GPIE0

Event Ex. 2

Enable

Reset 11111111

Bit Description

7 GPIE7 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

6 GPIE6 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

5 GPIE5 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

4 GPIE4/

RING Event Extension 2 Enable

0: Disabled 1: Enabled (default)

3 GPIE3 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

2 GPIE2 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

1 GPIE1 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

0 GPIE0 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

3.0 System Wake-Up Control (SWC) (Continued)

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3.4.15 PS/2 Keyboard and Mouse Wake-Up Events

The SWC can be configured to detect any predetermined PS/2 keyboard or mouse activity. The detection mechanisms for keyboard and mouse events are independent. Therefore, they can be operated simulta-

neously with no interference. Since both mechanisms are implemented by hardware which is independent of the device’s keyboard controller, the keyboard controller itself need not be activated to detect either keyboard or mouse events.

Keyboard Wake-Up Events

The keyboard wake-up detection mechanism can be programmed to detect:

●

Any keystroke

●

A speciﬁc programmable sequence of up to eight alphanumeric keystrokes (Password mode)

●

Any programmable sequence of up to 8 bytes of data received from the keyboard (Special Key Sequence mode).

To program the keyboard wake-up detection mechanism to wake-up on any keystroke, perform the following sequence:

1. Put the wake-up mechansim in Special Key Sequence mode by setting bits 3-0 of the PS2CTL register to 0001b.

2. Set the PS2KEY0 and PS2KEY1 registers to 00h. This forces the wake-up detection mechanism to ignorethe values of

incoming data, thus causing it to wake-up on any keystroke.

In Password mode, the Make and Breakbytestransmittedbythekeyboardarediscarded,andonlythescancodesarecompared against those programmed in the PS2KEYn registers. To simplify the detection mechanism, only keys with a scan code of 1 byte can be included in the sequence to be detected. To program the keyboard wake-up detection mechanism to operate in Password mode, proceed as follows:

1. Set bits 3-0 of the PS2CTL register with a value that indicates the desired number of keystrokes in the sequence. The

programmed value should be the number of keystrokes + 7. For example, to wake-up on a sequence of two keys, set bits 3-0 to 9h.

2. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers, in sequential order, with the scan codes of the

keys in the sequence. For example, if there are three keys in the sequence and the scan codes of these keys are 05h (first), 50h (second) and 44h (third), program PS2KEY0 to 05h, PS2KEY1 to 50h and PS2KEY2 to 44h (the scan codes are only examples).

In Special Key Sequence mode, all the bytes transmitted by the keyboard are compared against the ones programmed in the PS2KEYn registers. These include also the Make and Break bytes. This mode enables the detection of any sequence of keystrokes, including also keys such as Shiftand Alt. To program the keyboard wake-up detection mechanism tooperate in Special Key Sequence mode, proceed as follows:

1. Setbits 3-0 of the PS2CTL register to avalue that indicates the desired number of keystrokes inthe sequence. The pro-

grammedvalueshouldbethe number of keystrokes+1.For example, to wake-uponasequence of three receivedbytes, set bits 3-0 of PS2CTL to 2h.

2. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers, in sequential order, with the values of the data

bytes that comprise the sequence. For example, if the number of bytes in the sequence is four, and the values of these bytes areE0h(first),5Bh(second),E0h (third) and DBh (fourth), programPS2KEY0toE0h,PS2KEY1to 5Bh, PS2KEY2 to E0h and PS2KEY3 to DBh (the byte values are only examples).

Mouse Wake-Up Events

The mouse wake-up detection mechanism can be programmed to detect either any mouseclick or movement, or a specific programmable click (left or right) or double-click.

To program this mechanism to wake-up on a specific event, set bits 6-4 of the PS2CTL register to the required value, according to the description of these bits in Section 3.4.16.

3.0 System Wake-Up Control (SWC) (Continued)

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3.4.16 PS/2 Protocol Control Register (PS2CTL)

This register is set to 00h on power-up of V

or software reset. It configures the PS/2 keyboard and mouse wake-up fea-

tures. Before changing bits 6-4 or 3-0, clear them to 0 and then write the new value. Location: Bank 0, Offset 13h Type: R/W

3.4.17 Keyboard Data Shift Register (KDSR)

This register is set to 00h on power-up of V

or software reset. It stores the keyboard data shifted in from the keyboard

during transmission, only when keyboard wake-up detection is enabled. Location: Bank 0, Offset 16h Type: RO

Bit 76543210

Name

Disable

Parity

Check

Mouse Wake-Up Conﬁguration Keyboard Wake-Up Conﬁguration

Reset 00000000

Bit Description

7 Disable Parity Check

0: Enabled (default) 1: Disabled

6-4 Mouse Wake-Up Conﬁguration

Bits

6 5 4 Configuration

0 0 0 Disable mouse wake-up detection 0 0 1 Wake-up on any mouse movement or button click 0 1 0 Wake-up on left button click 0 1 1 Wake-up on left button double-click 1 0 0 Wake-up on right button click 1 0 1 Wake-up on right button double-click 1 1 0 Wake-up on any button single-click (left, right or middle) 1 1 1 Wake-up on any button double-click (left, right or middle)

3-0 Keyboard Wake-Up Conﬁguration

Bits 3 2 1 0 Configuration

0 0 0 0 Disable keyboard wake-up detection 0 0 0 1

to Special key sequence 2-8 PS/2 scan codes, “Make” and “Break” (including Shift and Alt keys) 0 1 1 1

1 0 0 0 to Password enabled with 1-8 keys “Make” code (excluding Shift and Alt keys) 1 1 1 1

Bit 76543210 Name Keyboard Data Reset 00000000

} }

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3.4.18 Mouse Data Shift Register (MDSR)

This register is set to 00h on power-up of V

or software reset. It stores the mouse data shifted in from the mouse during

transmission, only when mouse wake-up detection is enabled. Location: Bank 0, Offset 17h Type: RO

3.4.19 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7)

Eight registers (PS2KEY0-PS2KEY7) store the scan codes for thepasswordor key sequence of the keyboard wake-up feature, as follows:

●

PS2KEY0 register stores the scan code for the ﬁrst key in the password/key sequence.

●

PS2KEY1 register stores the scan code for the second key in the password/key sequence.

●

PS2KEY2 - PS2KEY7 registers store the scan codes for the third to eighth keys in the password/key sequence.

When one of these registers is set to 00h, it indicates that the value of the corresponding scan code byte is ignored (not compared). These registers are set to 00h on power-up of V

or software reset. Location: Bank 0, Offset 18h-1Fh Type: R/W

Bit 76543210 Name Reserved Mouse Data Reset 00000000

Bit 76543210 Name Scan Code of Keys 0-7 Reset 00000000

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3.4.20 CEIR Wake-Up Control Register (IRWCR)

This register is set to 00h on power-up of V

or software reset. Location: Bank 1, Offset 13h Type: R/W

Bit 76543210 Name Reserved CEIR Protocol Select

Select

IRRX2 Input

Invert

IRRXn Input

Reserved

CEIR

Enable

Reset 00000000

Bit Description

7-6 Reserved 5-4 CEIR Protocol Select

Bits 5 4 Protocol

0 0 RC5 (default) 0 1 NEC/RCA 1 X Reserved

3 Select IRRX2 Input. Selects the IRRX input.

0: IRRX1 (default) 1: IRRX2

2 Invert IRRXn Input

0: Not inverted (default)

1: Inverted 1 Reserved. 0 CEIR Enable

0: CEIR is disabled. Registers are maintained, but CEIR Event Status bit (of WK0_STS) does not reﬂect CEIR

events. (Unlike the CEIR Event Enable bit of WK0_EN that does not affect the CEIR Event Status bit.) (default)

1: CEIR is enabled

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3.4.21 CEIR Wake-Up Address Register (IRWAD)

This register holds the unique address to be compared with the address contained in the incoming CEIR message. If CEIR is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WK0_STS register is set to 1 (see Section 3.4.2).

This register is set to 00h on power-up of V

or software reset. Location: Bank 1, Offset 15h Type: R/W

3.4.22 CEIR Wake-Up Address Mask Register (IRWAM)

Each bit in this register determines whether the corresponding bit in the IRWAD register is enabled in the address comparison. Bits 5, 6 and 7 must be set to 1 if the RC-5 protocol is selected.

This register is set to E0h on power-up of V

or software reset. Location: Bank 1, Offset 16h Type: R/W

Bit 76543210 Name CEIR Wake-Up Address Reset 00000000

Bit 76543210 Name CEIR Wake-Up Address Mask Reset 11100000

Bit Description

7-0 CEIR Wake-Up Address Mask. If the corresponding bit is 0, the address bit is not masked (enabled for

compare). If the corresponding bit is 1, the address bit is masked (ignored during compare).

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3.4.23 CEIR Address Shift Register (ADSR)

This register holds the received address to be compared with the address contained in the IRWAD register. This register is set to 00h on power-up of V

or software reset. Location: Bank 1, Offset 17h Type: RO

3.4.24 CEIR Wake-Up Range 0 Registers

These registers define the low and high limits of time range 0. The values are represented in units of 0.1 msec. For the RC-5 protocol, the bit cell width must fall within this range for the cell to be considered valid. The nominal cell width

is 1.778 msec for a 36 KHz carrier. IRWTR0L and IRWTR0H should be set to 10h and 14h respectively (default). For the NEC protocol, the time distance between two consecutive CEIR pulses that encodes a bit value of 0 must fall within

this range. The nominal distance for a 0 is 1.125 msec for a 38 KHz carrier. IRWTR0L and IRWTR0H should be set to 09h and 0Dh respectively.

IRWTR0L Register

This register is set to 10h on power-up of V

or software reset. Location: Bank 1, Offset 18h Type: R/W

IRWTR0H Register

This register is set to 14h on power-up of V

or software reset. Location: Bank 1, Offset 19h Type: R/W

Bit 76543210 Name CEIR Address Reset 00000000

Bit 76543210 Name Reserved CEIR Pulse Change, Range 0, Low Limit Reset 00010000

Bit 76543210 Name Reserved CEIR Pulse Change, Range 0, High Limit Reset 00010100

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3.4.25 CEIR Wake-Up Range 1 Registers

These registers define the low and high limits of time range 1. The values are represented in units of 0.1 msec. For the RC-5 protocol, thepulse width defining a half-bit cell must fall within this range in orderfor the cell to be considered valid.

The nominal pulse width is 0.889 for a 38 KHz carrier. IRWTR1L and IRWTR1H should be set to 07h and 0Bh respectively (default).

For the NEC protocol, the time between twoconsecutive CEIR pulses that encodes a bit value of 1 must fall within this range. The nominal time for a 1 is 2.25 msec fora36KHz carrier. IRWTR1L and IRWTR1H should be set to 14h and 19h respectively.

IRWTR1L Register

This register is set to 07h on power-up of VPP or software reset. Location: Bank 1, Offset 1Ah Type: R/W

IRWTR1H Register

This register is set to 0Bh on power-up of V

or software reset. Location: Bank 1, Offset 1Bh Type: R/W

3.4.26 CEIR Wake-Up Range 2 Registers

These registers define the low and high limits of time range 2. The values are represented in units of 0.1 msec. These registers are not used when the RC-5 protocol is selected.

For the NEC protocol, the header pulse width must fall within this range in order for the header to be considered valid. The nominal value is 9 msec for a 38 KHzcarrier. IRWTR2L and IRWTR2H should be set to 50h and 64h respectively (default).

IRWTR2L Register

This register is set to 50h on power-up of V

or software reset. Location: Bank 1, Offset 1Ch Type: R/W

IRWTR2H Register

This register is set to 64h on power-up of V

or software reset. Location: Bank 1, Offset 1Dh Type: R/W

Bit 76543210 Name Reserved CEIR Pulse Change, Range 1, Low Limit Reset 00000111

Bit 76543210 Name Reserved CEIR Pulse Change, Range 1, High Limit Reset 00001011

Bit 76543210 Name CEIR Pulse Change, Range 2, Low Limit Reset 01010000

Bit 76543210 Name CEIR Pulse Change, Range 2, High Limit Reset 01100100

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3.4.27 CEIR Wake-Up Range 3 Registers

These registers define the low and high limits of time range 3. The values are represented in units of 0.1 msec. These registers are not used when the RC-5 protocol is selected.

For the NEC protocol, the post header gap width must fall within this range in order for the gap to be considered valid. The nominal value is 4.5 msec for a36KHz carrier. IRWTR3L and IRWTR3H should be set to 28hand32h respectively (default).

IRWTR3L Register

This register is set to 28h on power-up of V

or software reset. Location: Bank1, Offset 1Eh Type: R/WS

IRWTR3H Register

This register is set to 32h on power-up of V

or software reset. Location: Bank 1, Offset 1Fh Type: R/W

CEIR Recommended Values

Table 38 lists the recommended time ranges limits for the different protocols and their four applicable ranges. The values are represented in hexadecimal code where the units are of 0.1 msec.

Bit 76543210 Name CEIR Pulse Change, Range 3, Low Limit Reset 00101000

Bit 76543210 Name CEIR Pulse Change, Range 3, High Limit Reset 00110010

Table 38. Time Range Limits for CEIR Protocols

Range

RC-5 NEC RCA

Low Limit High Limit Low Limit High Limit Low Limit High Limit

0 10h 14h 09h 0Dh 0Ch 12h 1 07h 0Bh 14h 19h 16h 1Ch 2 −−50h 64h B4h DCh 3 −−28h 32h 23h 2Dh

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3.4.28 Standby General-Purpose I/O (SBGPIO) Register Overview

The SWC can be used to operate up to 8 V

-powered general-purpose input/output (GPIO), input (GPI) pins, all of which

support event detection. These are as follows:

●

GPIOE0-5 are GPIO pins.

●

GPIE6,7 are GPI pins.

For programming convenience, these pins are associated with an SBGPIO port. Speciﬁcally, GPIE0-5 and GPIE6,7 areassociated with bits 0 to 7 of SBGPIO port 0, respectively.

Table 39 provides a summary of the SBGPIO pin-to-port assignment and pin types.

Table 39. SBGPIO Pin Types and Associated Port

An SBGPIO port is structured as an 8-bit port, based on eight pins. It features:

• Software capability to manipulate and read pin levels

• Controllable system notiﬁcation by several means based on the pin level or level transition

• Ability to capture and manipulate events and their associated status

• Back-drive protected pins.

SBGPIO port operation is associated with two sets of registers:

• Pin conﬁguration registers, mapped in the SWC register bank 3. These registers are used to statically set up the log-

ical behavior of each pin. There is one 8-bit register for each SBGPIO pin.

• Two 8-bit runtime registers: SBGPIO Data Out (SBGPDO) and SBGPIO Data In (SBGPDI). These registers are

mapped in the SWC device I/O space (determined by the base address registers in the SWC Device Conﬁguration). They are used to manipulate and/or read the pin values. Each runtime register corresponds to the 8-pin port described above (see Table 39).

Each SBGPIO pin is associated with up to six configuration bits and the corresponding bitslice of the two runtime registers, as shown in Figure 10.

The SBGPIO port has basic as well as enhanced functionality. Basic functionality includes the manipulation and reading of the SBGPIO pins, as described in Section . Enhanced functionality includes event detection, as described in

Event Detec-

tion

Pin(s) Port Type

Event

Detection

GPIOE0-5 0 I/O Yes

GPIE6,7 0 I Yes

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Figure 10. SBGPIO Port Architecture

Basic Functionality

The basic functionality of each SBGPIO pin is based on four configuration bits and a bit slice of runtime registers SBGPDO and SBGPDI. The configuration and operation of a single pin (pin n in port X) is shown in Figure 11.

Figure 11. SBGPIO Basic Functionality

SBGPIO Pin

Select Register

Conﬁguration Register

SBGPDOX SBGPDIX

Runtime

Registers

SBGPIOX Base Address

Event

Bit n

Port and Pin

8 SBGPIO Pin Conﬁguration

Registers

SBGPIO Port X

Pin n

SBGPIOXn CNFG

SBGPIOXn

Pin Logic

X = port number n = pin number, 0 to 7

Pending Indicator

Select

To Wake-Up Logic

Data Out

Data In

Output

Enable

Output

Internal

Bus

Lock

Type

Static

Pull-Up

Pull-Up Enable

SBGPIO Pin Conﬁguration Register

Push-Pull=1

Pull-Up

Control

Read Only

Read/Write

Bit 3 Bit 2 Bit 1 Bit 0

NSC PC87360-IBM-VLA, PC87360-ICK-VLA Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual