NSC SCAN18374TMDA Datasheet
SCAN18374T
D Flip-Flop with TRI-STATE
®
Outputs
General Description
The SCAN18374T is a high speed, low-power D-type
flip-flop featuring separate D-type inputs organized into dual
9-bit byteswith byte-oriented clock and output enable control
signals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and BOUNDARY-SCAN Architecture with
the incorporation of the defined BOUNDARY-SCAN test
logic and test access port consisting of TestData Input (TDI),
Test Data Out (TDO), Test Mode Select (TMS), and Test
Clock (TCK).
Features
n IEEE 1149.1 (JTAG) Compliant
n Buffered positive edge-triggered clock
n TRI-STATE outputs for bus-oriented applications
n 9-bit data busses for parity applications
n Reduced-swing outputs source 24 mA/sink 48 mA (Mil)
n Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
n TTL compatible inputs
n 25 mil pitch Cerpack packaging
n Includes CLAMP and HIGHZ instructions
n Standard Microcircuit Drawing (SMD) 5962-9320701
Connection Diagram
Pin Names Description
AI
(0–8)
,BI
(0–8)
Data Inputs
ACP, BCP Clock Pulse Inputs
Pin Names Description
AOE
1
, BOE
1
TRI-STATE Output Enable Inputs
AO
(0–8)
,BO
(0–8)
TRI-STATE Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS100322-1
September 1998
SCAN18374T D Flip-Flop with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100322 www.national.com
Truth Tables
Inputs AO
(0–8)
ACP AOE
1
AI
(0–8)
XHXZ
NLLL
NLHH
Inputs BO
(0–8)
BCP BOE
1
BI
(0–8)
XHXZ
NLLL
NLHH
H
=
HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
N=L-to-H Transition
Functional Description
The SCAN18374 consists of two sets of nine edge-triggered
flip-flops with individual D-type inputs and TRI-STATE true
outputs. The buffered clock and buffered Output Enable pins
are common to all flip-flops. Each set of the nine flip-flops will
store the state of their individual D inputs that meet the setup
and hold time requirements on the LOW-to-HIGH Clock
(ACP or BCP) transition. With the Output Enable (AOE
1
or
BOE1) LOW, the contents of the nine flip-flops are available
at the outputs. When the Output Enable is HIGH, the outputs
go to the high impedance state. Operation of the Output Enable input does not affect the state of the flip-flops.
Logic Diagram
Block Diagrams
DS100322-13
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte-A
DS100322-2
Note: BSR stands for Boundary Scan Register
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Block Diagrams (Continued)
Tap Controller
DS100322-3
Byte-B
DS100322-4
Note: BSR stands for Boundary Scan Register
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Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location.
Scan cell TYPE1 is intended to solely observe system data,
while TYPE2 has the additional ability to control system
data. (See IEEE Standard 1149.1
Figure 10–11
for a further
description of scan cell TYPE1 and
Figure 10–12
for a fur-
ther description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as well
as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE
controls the activity of the B-outputs. Each will activate their
respective outputs by loading a logic high.
The BYPASSregister is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18374T device. SCAN CMOS TestAccessLogic
devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be
used as a “pseudo ID” code to confirm that the correct device
is placed in the appropriate location in the boundary scan
chain.
MSB→LSB
Instruction Code Instruction
00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGHZ
All Others BYPASS
Bypass Register Scan Chain Definition
Logic 0
DS100322-9
Instruction Register Scan Chain Definition
DS100322-10
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Description of Boundary-Scan Circuitry (Continued)
Scan Cell TYPE1
DS100322-7
Scan Cell TYPE2
DS100322-8
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