NSC SCAN18373TMDA Datasheet

SCAN18373T
Transparent Latch with TRI-STATE

®

Outputs

General Description

The SCAN18373T is a high speed, low-power transparent
latch featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented latchenableand output enable con­trol signals. This device is compliant with IEEE 1149.1 Stan­dard Test Access Port and Boundary Scan Architecture with
the incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), and Test Clock
(TCK).

Features

n IEEE 1149.1 (JTAG) Compliant
n Buffered active-low latch enable
n TRI-STATE outputs for bus-oriented applications
n 9-bit data busses for parity applications
n Reduced-swing outputs source 24 mA/sink 48 mA
n Guaranteed to drive 50Ω transmission line to TTL input

levels of 0.8V and 2.0V

n TTL compatible inputs
n 25 mil pitch Cerpack packaging
n Includes CLAMP and HIGHZ instructions
n Standard Microcircuit Drawing (SMD) 5962-9311801

Connection Diagram

Pin Names Description

AI

(0–8)

,BI

(0–8)

Data Inputs
ALE, BLE Latch Enable Inputs
AOE

1

, BOE

1

TRI-STATE Output Enable Inputs
AO

(0–8)

,BO

(0–8)

TRI-STATE Latch Outputs

Truth Tables

Inputs AO (0–8)

ALE AOE

1

AI (0–8)

XH X Z
HL L L
HL H H
LL X AO

0

Inputs BO (0–8)

BLE BOE

1

BI (0–8)

XH X Z
HL L L
HL H H
LL X BO

0

H

=

HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
AO

0

=

Previous AO before H-to-L transition of ALE

BO

0

=

Previous BO before H-to-L transition of BLE

Functional Description

The SCAN18373T consists of two sets of nine D-type
latches with TRI-STATE standard outputs. When the Latch
Enable (ALE or BLE) input is HIGH, data on the inputs
(AI

(0–8)

or BI

(0–8)

) enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its input changes. When Latch Enable is LOW, the
latches store the information that was present on the inputs
a set-up time preceding the HIGH-to-LOW transition of the

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

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September 1998

SCAN18373T Transparent Latch with TRI-STATE Outputs

© 1998 National Semiconductor Corporation DS100321 www.national.com

Functional Description (Continued)

Latch Enable. The TRI-STATE standard outputs are con­trolled by the Output Enable (AOE

1

or BOE1) input. When

Output Enable is LOW, the standard outputs are in the

2-state mode. When Output Enable is HIGH, the standard
outputs are in the high impedance mode, but this does not
interfere with entering new data into the latches.

Logic Diagram

Block Diagrams

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Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Byte-A

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Block Diagrams (Continued)

Tap Controller

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Byte-B

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Note 1: BSR stands for Boundary Scan Register.

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Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location.
Scan cell TYPE1 is intended to solely observe system data,
while TYPE2 has the additional ability to control system
data. (See IEEE Standard 1149.1 for a further description of
scan cell TYPE1 and for a further description of scan cell
TYPE2.)

Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as well
as at each of the two internal active-high output enable sig­nals. AOE controls the activity of the A-outputs while BOE
controls the activity of the B-outputs. Each will activate their
respective outputs by loading a logic high.

The BYPASSregister is a single bit shift register stage iden­tical to scan cell TYPE1. It captures a fixed logic low.

The INSTRUCTION register is an eight-bit register which
captures the value 00111101.

The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18373T device. SCAN CMOS TestAccess Logic
devices do not include the IEEE 1149.1 optional identifica­tion register. Therefore, this unique captured value can be
used as a “pseudo ID” code to confirm that the correct device
is placed in the appropriate location in the boundary scan
chain.

MSB→LSB

Instruction Code Instruction

00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGHZ
All Others BYPASS

Bypass Register Scan Chain Definition Logic 0

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Instruction Register Scan Chain Definition

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Scan Cell TYPE1

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Description of Boundary-Scan Circuitry (Continued)

Scan Cell TYPE2

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