NSC PCM16C010VJG Datasheet

TL/F/12147

PCM16C010 Configurable PC Card Interface Chip

August 1996

PCM16C010
Configurable PC Card Interface Chip

General Description

National’s PCM16C010 acts as a standard interface be­tween the PC Card Host bus and local card busses found on
I/O and memory PC Cards. This device allows the card de­signer to focus on the design of the I/O functions while
providing a one-chip solution for I/O memory window con­trol, EEPROM interfacing, and power management.

The PCM16C010 provides a PC Card interface for any ISA
like function which allows it to be placed on a PC Card.

In addition, the PCM16C010 provides the capability to con­figure the function as a NAND Flash (NM29N16) interface;
supporting all of the necessary control signals required to
handshake with NAND Flash (NM29N16) memory devices.

The PCM16C010 is fully compliant with the PC Card Stan­dard. This IC allows the system software to setup an I/O
decode window and provides the Attribute memory decode
control that allow attribute read and write data transfers.

Note, PC Card refers to technology developed to the PC
Card Standards determined by the PCMCIA Standards
Committee.

Features

Y

PC Card bus interface

Y

PC Card Standard configuration registers

Y

100 pin TQFP package

Y

Configurable as NAND Flash (NM29N16) interface

Y

Serial EEPROM Interface compatible with
MICROWIRE

TM

EEPROM protocol

Y

1-kbyte on chip RAM for attribute memory which shad­ows the CIS and is used for loading static registers

Y

Address decoding and control for I/O functions

Y

Power management and clock control

Y

Common memory logic for common memory devices in­cluding NOR Flash devices

Y

Operating voltage rangeeVCC(opr)e3VE5.0V

1.0 System Diagram

TL/F/12147– 1

FIGURE 1-1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
MICROWIRE

TM

is a trademark of National Semiconductor Corporation.

C

1996 National Semiconductor Corporation RRD-B30M17/Printed in U. S. A.

http://www.national.com

Table of Contents

GENERAL DESCRIPTION AND PRODUCT FEATURES АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 1

1.0 SYSTEM DIAGRAM АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 1

2.0 CONNECTION DIAGRAM ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 3

3.0 PINOUT DESCRIPTION AND DETAILED TABLES ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 4

4.0 BLOCK DIAGRAM ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 7

5.0 FUNCTIONAL DESCRIPTION ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

5.1 Address Maps АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

5.1.1 Attribute Memory Addressing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

5.1.2 I/O Memory Addressing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 9

5.1.3 Common Memory Addressing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 9

5.2 CIS (Card Information Structure) АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 9

5.3 Registers АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 9

5.3.1 PCM16C010 Specific Registers ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 9

5.3.2 PC Card Register АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА11

5.4 Logic Descriptions АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА14

5.4.1 I/O Card Interface Logic for PC Card Host I/O Access ААААААААААААААААААААААААААААААААААААААААААААААААААА14

5.4.2 EEPROM Interface АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА14

5.4.3 Power Management ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА15

5.4.4 NAND Flash (NM29N16) Interface ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА15

NAND Flash (NM29N16) Mode Register Set (Table 5-2) АААААААААААААААААААААААААААААААААААААААААААААААААА16

NAND Flash (NM29N16) Interface Block Diagram

(Figure 5-2)

ААААААААААААААААААААААААААААААААААААААААААААА17

Typical PCM16C010 to NAND Flash (NM29N16) Read to I/O Space Sequence (

Figures 5-3, 5-4

and Table 5-3) À18

6.0 OPERATIONAL MODES АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА20

6.1 Initial Setup (Reset) and Configuration ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА20

6.2 Reset Conditions ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА20

6.3 16-Bit/8-Bit Operation ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА20

6.4 Special Testability Modes АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА20

SOFTWARE ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА20

ABSOLUTE MAXIMUM RATINGSАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА21

RECOMMENDED OPERATING CONDITIONS ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА21

RELIABILITY REQUIREMENTS ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА21

DC ELECTRICAL CHARACTERISTICS ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА21

TIMING SPECIFICATIONS AND DIAGRAMS АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА23

CAPACITANCE АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА37

TYPICAL APPLICATIONS АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА37

REFERENCES ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА37

PHYSICAL DIMENSIONS ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА38

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2.0 Connection Diagram

TL/F/12147– 2

NCeNo Connect

Order Number PCM16C010VJG

See NSC Package Number VJG100A

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3.0 Pinout Description

TABLE 3-1. PC Card Host-Side Pins

Pin Pin Pin Level Internal

Description

Name Type No. Compatibility Resistor

HDATA(15:0) I/O 39–41, 43, 45, TTL 6 mA

l

100k to GND PC Card Host Data Bus.

46, 66–71, 73 –76

HADDR(12:0) I 47 –52, 54 – 56, TTL

l

100k to GND PC Card Host Address Bus.

59, 60, 62, 64

HOE

Ý

I 63 TTL

l

100k to V

CC

PC Card Host uses this pin to read
common or attribute memory space.

HWE

Ý

I 58 TTL

l

100k to V

CC

PC Card Host uses this pin to write
common or attribute memory space.

HIORD

Ý

I 79 TTL

l

100k to V

CC

PC Card Host uses this pin to read I/O
memory space.

HIOWR

Ý

I 80 TTL

l

100k to V

CC

PC Card Host uses this pin to write I/O
memory space.

IREQ

Ý

O 57 CMOS 6 mA Interrupt Request signal to PC Card Host.

HWAIT

Ý

O 33 CMOS 6 mA This pin allows the PCM16C02 to insert

wait states in a PC Card transaction.

IOIS16

Ý

O 42 CMOS 6 mA Low indicates this I/O access to the card

is capable of 16-bit access. The Function
may use IOCS16Ýto control this signal
and inform the host if a 16-bit access to
the target is feasible.

INPACK

Ý

O 34 CMOS 6 mA Signals a valid I/O read.

CE1

Ý

I 65 TTL

l

100k to V

CC

Indicates even address byte. Odd
addresses are not released. CE1

Ý

and

CE2

Ý

assertion encodings are specified

by the PC Card Standard.

CE2

Ý

I 78 TTL

l

100k to V

CC

Indicates odd addressing only. CE1Ýand
CE2

Ý

assertion encodings are specified

by the PC Card Standard.

REG

Ý

I 35 TTL

l

100k to V

CC

Indicates access to attribute memory
space or I/O address space. REG

Ý

must
be high to access common memory
space.

RESET I 32 TTL Schmitt

l

100k to V

CC

Asynchronously resets the PCM16C02.

SPKR

Ý

O 37 CMOS 6 mA If Audio bits are set in the Card

Configuration Status Register and in the
Function Configuration Status Register
then SPKR

Ý

is invert of SPKÐIN pin,

else SPKR

Ý

is high.

STSCHG

Ý

O 38 CMOS 6 mA STSCHGÝis asserted when the

Changed bit and SigChg bit are set in the
Card Configuration Status Register.

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3.0 Pinout Description (Continued)

TABLE 3-2. Serial EEPROM Interface Pins

Pin Pin Pin Level Internal

Description

Name Type No. Compatibility Resistor

EEDI/EEDO I/O 81 TTL 6 mA Serial Data in to/from EEPROM.

EECS O 83 CMOS 6 mA EEPROM Chip Select.

EESK O 82 CMOS 6 mA EEPROM Clock. FreqeMCLK(0)/32.

Note: The Enable EEPROM function is performed in software by writing to the EEPROM Control Register. The Enable EEPROM bit will default to low (disabled)
upon power on.

TABLE 3-3. Card-Side Interface Pins

Pin Pin Pin Level Internal

Description

Name Type No. Compatibility Resistor

LDATA(15:0) I/O 1– 5, 7 –13, TTL 6 mA Hold Circuit Card-side Data Bus.

97–100 (Note 1)

SPKÐIN I 86 TTL Schmitt Input Audio Signal.

RIÐIN

Ý

I (Note 2) 23 TTL Schmitt Ring Indicator for function 0.

CIORD

Ý

O 19 CMOS 6 mA I/O read signals are passed through from HIORD

Ý

according to the expression shown below when a
valid address is decoded.
CIORD

Ý

e

HIORD

Ý

a

REG

Ý

a

(CE1Ý* CE2Ý)

CIOWR

Ý

O 18 CMOS 6 mA I/O write signals are passed through from HIOWR

Ý

according to the expression shown below when a
valid address is decoded.
CIOWR

Ý

e

HIOWR

Ý

a

REG

Ý

a

(CE1Ý* CE2Ý)

CWAIT I (Note 2) 31 TTL Card-side transaction wait state input.

CS

Ý

O 30 CMOS 6 mA Chip select for function.

BHE

Ý

O 17 CMOS 6 mA Byte high enable. When de-asserted and CS( )

Ý

asserted, an 8-bit access on LDATA(7:0) is in
progress. This holds for both odd and even
addresses. When asserted and CS( )

Ý

asserted, a

16-bit access on LDATA(15:0) is in progress.

READY I 27 TTL

l

100k to VCCIndicates that the function is either READY or

E

READY (i.e. - Busy). This signal is used to assert

the Rdy/Bsy

Ý

bit in Pin Replacement Registers.

CINT I (Note 2) 29 TTL Schmitt Card-side interrupt input signal.

SRESET O 28 CMOS 6 mA Signals reset to Card-side function.

IOCS16

Ý

I (Note 2) 26 TTL This pin is asserted during an access to a function if

that function is capable of a 16-bit access.

PCNTL O 14 CMOS 6 mA Power management control signals or general

output.

MCLK I 24 TTL Schmitt Input clock for function.

FCLK O 25 CMOS 6 mA Output clock signal for function. This may be gated

on/off or be a divided value of MCLK.

MEMWEH

Ý

O Tri 21 CMOS 6 mA

l

10k to V

CC

Common Memory write output for upper byte of data
word.

MEMWEL

Ý

O Tri 22 CMOS 6 mA

l

10k to V

CC

Common Memory write output for lower byte of data
word.

Note 1: The Hold Circuit will hold the signal to the logic value it was last set to when the line is TRI-STATEÉ. This will insure that inputs do not float during a
TRI-STATE condition.

Note 2: The CWAIT, CINT, RIÐIN and IOCS16

Ý

pins are outputs (O) when the function is configured for the NAND Flash (NM29N16) Mode.

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3.0 Pinout Description (Continued)

TABLE 3-4. Miscellaneous Pins

Pin Pin Pin Level Internal

Description

Name Type No. Compatibility Resistor

TEST(0) I 85 TTL

l

100k to GND Test pin. This pin should be left disconnected for

normal operation.

VCC(5:0) Power 84, 61, 44, Power Voltage.

16, 87, 91

GND(9:0) Power 88, 77, 72, Return Voltage.

53, 36, 20, 6,

90, 94, 96

TABLE 3-5. NAND Flash (NM29N16) Mode Pins

Pin Pin Pin Level Internal

Description

Name Type No. Compatibility Resistor

ALE O 31 CMOS 6 mA Address Latch Enable

(Note 1)

CLE O 28 CMOS 6 mA Command Latch Enable

WE

Ý

O 29 CMOS 6 mA Write Enable

(Note 1)

RE

Ý

O 30 CMOS 6 mA Read Enable

RDY/BSY

Ý

I 27 TTL

l

100k to VCCReady/Busy Input

CEÐNAND (3:0)

Ý

O 23, 26, CMOS 6 mA Chip Enables for NAND Flash (NM29N16) Devices

(Note 1) 14, 25

Note 1: The ALE, WEÝ,CEÐNAND(0)Ý, and CEÐNAND(1)Ýpins are inputs (I) when function 0 is NOT configured for the NAND Flash (NM29N16) Mode.

Pin Total:
Host-Side Interface Pins 44
EEPROM Interface Pins 4
Card-Side Interface Pins 30
Miscellaneous Pins 22

Total Pins 100

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4.0 Block Diagram

TL/F/12147– 3

FIGURE 4-1

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5.0 Functional Description

The PCM16C02 provides an integrated solution to interfac­ing dual function I/O cards with the PC Card Bus. The part
has a contiguous 1-kbyte RAM block to store attribute mem­ory. The IC also provides an EEPROM interface to serial
EEPROMs that use the MICROWIRE protocol. At a mini­mum, a 16-kbit serial EEPROM is required. The part allows
I/O address windows to be programmed independently for
each function.

5.1 ADDRESS MAPS

5.1.1 Attribute Memory Addressing

The Attribute Memory space contains both the Card Infor­mation Structure (CIS), PC Card Registers for both I/O func­tions, and PCM16C02 implementation specific registers.
Note that PC Card Standard specifies that Attribute memory
may only be accessed on even address byte boundaries.
The Attribute Memory space fragmentation is shown in Ta­ble 5-1.

TABLE 5-1. Attribute Memory Map

Register Description Register Type Address (Hex) EEPROM

Card Information Structure PC Card CIS 0x000–0x03E2 Yes

Pin Polarity Register PCM16C02 Specific 0x03E4 Yes

PMGR and Clock Register PCM16C02 Specific 0x03E6 Yes

CTERM Register PCM16C02 Specific 0x03E8 Yes

Unused PCM16C02 Specific 0x03EA Yes

Reserved for Future Use Registers PCM16C02 Specific 0x03EC –0x03EE Yes

Miscellaneous Register PCM16C02 Specific 0x03F0 Yes

Reserved for Future Use Registers PCM16C02 Specific 0x03F2 –0x03F4 Yes

Wait State Timer Registers PCM16C02 Specific 0x03F6 Yes

NAND Flash (NM29N16) Config Register PCM16C02 Specific 0x03F8 Yes

Reserved for Future Use Register PCM16C02 Specific 0x03FA Yes

Watchdog Timer Register PCM16C02 Specific 0x03FC Yes

Reserved for Future Use Registers PCM16C02 Specific 0x03FE Yes

Card Information Structure PC Card CIS 0x0400– 0x07FE Optional

ID Register PCM16C02 Specific 0x1000 No

EEPROM Control Register PCM16C02 Specific 0x1002 No

EEPROM Security Register PCM16C02 Specific 0x1004 No

Reserved for Future Use Registers PCM16C02 Specific 0x1006 –0x101E No

Function Configuration Option Register PC Card 0x1020 No

Function Configuration Status Register PC Card 0x1022 No

Function Pin Replacement Register PC Card 0x1024 No

Unused PC Card 0x1026 No

Function I/O Event Register PC Card 0x1028 No

Function Base A Register PC Card Extension 0x102A No

Function Base B Register PC Card Extension 0x102C No

Unused PC Card Extension 0x102E –0x1030 No

Function Limit Register PC Card Extension 0x1032 No

Reserved for Future Use Registers PC Card Extension 0x1034 –0x103E No

Reserved for Future Use Registers PC Card Extension 0x1040 –0x105E No

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5.0 Functional Description (Continued)

5.1.2 I/O Memory Addressing

National’s PCM16C010 uses address base and limit regis­ters to steer I/O transactions from the PC Card Host to the
card function.

TL/F/12147– 4

I/O Address Space

FIGURE 5-1. I/O Address Decoding for

Two Functions on a PC Card

5.1.3 Common Memory Addressing

The NSC PCM16C010 does not specifically decode com­mon memory address accesses initiated by the host. Rath­er, it will pass a host access of HDATA(15:0) through to
LDATA(15:0) while passing the address lines around the
PCM16C010. In addition, PCM16C010 will pass the host
HWE

Ý

signal assertion to the MEMWEHÝ/

MEMWEL

Ý

signals appropriately based upon the proper

assertion of CE1

Ý

, CE2Ý, and REGÝ. The assertion of

MEMWEH

Ý

, MEMWELÝ, or both is determined by an 8-bit

or 16-bit access as specified in the PC Card Standard.

If a function is mapped to common memory, and requires
further address lines, it may use the HADDR(25:13) lines
from the PC Card socket as additional address lines around
the PCM16C010. The card design is free to use external
decoding logic for common memory.

5.2 CIS (CARD INFORMATION STRUCTURE)

[

0x000–0x03E2

]

When the PCM16C010 powers on, the contents of the lower
1-kbyte of the EEPROM are loaded into the device’s shad­ow RAM. This not only allows attribute memory accesses to
the CIS, but, it also provides defaults for 9 PCM16C010 spe­cific registers to be loaded. This allows default loading of
parameters that are transparent to system or device soft­ware. The best use is for the card manufacturer to deter­mine what values these should be and program them into
the EEPROM when the CIS is programmed. Either system
software such as Card Services/Socket Services or device
software may read and parse the CIS by accessing attribute
memory on the PC Card. If desired, this software agent may
write to the CIS or default EEPROM registers and, if desired,
have these new values saved to the EEPROM. The actual
contents of the CIS and the static registers is PC Card de­sign dependent.

5.3 REGISTERS

5.3.1 PCM16C010 Specific Registers

These registers are defined specifically for National’s
PCM16C010 IC, allowing the PCM16C010 to perform its
base functionality. These registers are not part of the PC
Card Standard.

Pin Polarity Register

[

0x03E4

]

This register sets the polarity of the card side interface sig­nals.

D7 D6 D5 D4 D3 D2 D1 D0

CIOWR CIORD Unused SRESET BHE Memls8 Unused CWAIT

CIOWR, CIORDÐSets the polarity of the CIOWRÝand
CIORD

Ý

pins respectively. A high indicates active high. The

default polarity is active-low.

SRESETÐSets the polarity of the SRESET pin. When this
bit is set to a zero (0), the output signal is asserted in the
high (1) state. When this bit is set to a one (1), the output
signal is asserted in the low (0) state. The bit default is zero
(0), i.e. the SRESET signal is active high.

BHEÐSets the polarity of the BHE

Ý

pin. A high indicates

active-high. The default polarity is active-low.

Memls8ÐThis bit is set to one (1) if common memory is
organized for 8-bit access. This bit is set to zero (0) if com­mon memory is organized for 16-bit access. The default val­ue is zero (0). This information allows the PCM16C010 to
properly access memory using the MEMWEH

Ý

, and

MEMWEL

Ý

, signals.

CWAITÐWhen this bit is set to one (1), the PCM16C010
interprets this input signal active when it is low (0). When
this bit is set to zero (0), the PCM16C010 interprets this
input signal as active when it is high (1). The default bit
value is zero (0), i.e. the CWAIT input signal is asserted high
(1).

UnusedÐThese bits are not used for operation of the
PCM16C010. These bits must be set to zero (0) in the CIS
for initialization and must not be changed from zero (0) to
ensure proper operation of the card.

PMGR and Clock Register

[

0x03E6

]

The Power Manager (PMGR) and Clock Register is used for
controlling the PCNTL and FCLK pins for power manage­ment purposes.

Hardware power management is enabled using the Func­tion Configuration Option Register’s PMGMTÐEN(D3) bit.
Its use is intended for functions that can be sequenced on/
off or into idle or sleep states with a quick (

k

10 ms) re­sponse time when powered on again. That is, the function
may use its CWAIT signal to extend a transaction that
caused the PCM16C010 to turn it on. Use of the READY
signal in a dynamic hardware power managed environment
to set the RRdy/Bsy bits in order to achieve

l

10 ms re­sponse times for power on is not guaranteed to work since
system software may not inspect the RRdy/Bsy bit in all
such instances.

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5.0 Functional Description (Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Unused Unused Unused Unused FCLKEN DIV PPOL PCNTL

FCLKENÐIf set, these enable the FCLK pin to receive a
clock out. If clear, FCLK will be forced low. These are set
and cleared by software if desired or statically loaded upon
card power up from the EEPROM.

DIVÐIf set, the respective clock output from FCLK will be
divided by 32 from the input clocks MCLK. If clear, the clock
output FCLK will equal the respective clock input MCLK.
These are set and cleared by software if desired or statically
loaded upon card power up from the EEPROM.

PPOLÐSets the active polarity of the PCNTL signal such
that the function is asserted. If PPOL is set to zero (0),
PCNTL is asserted when in the high state. If set to one (1),
PCNTL is asserted when in the low state. The default is set
to zero (0), i.e. PCNTL defaults to active high.

PCNTLÐThis bit controls the PCNTL Pin. If hardware pow­er management is not selected in the Function Configura­tion Option Register’s Function Configuration Index, then
this bit may be used as an output signal by software for
general purposes. If the hardware power management con­figuration is selected, this bit is de-asserted (defined by
PPOL) when the PCM16C010’s CTERM counter expires.
This bit will be asserted if a transaction occurs to the func­tion through an I/O window or the function requests service
by issuing a RIÐIN( ). In either strategy, software may al­ways write and read back these bits. This bit defaults to zero
(0) during power-on until the PMGR and Clock Register can
be loaded from the EEPROM.

UnusedÐThese bits are not used for operation of the
PCM16C010. These bits must be set to zero (0) in the CIS
for initialization and must not be changed from zero (0) to
insure proper operation of the card.

CTERM Register

[

0x03E8

]

This register is used to define the value of the function’s
power time-out counter. If the function’s power time-out
counter expires, the PCNTL bit for the function in the PMGR
and Clock Register is de-asserted. This will occur if a func­tion is in-active long enough for it’s power time-out counter
to expire. Active is defined as having either an I/O access
from the host or receiving a RIÐIN( )

Ý

. Devices that may
operate for long periods of time without a host I/O access
should follow a software controlled power management
strategy that uses the PwrDn bits in the Function Configura­tion Status Register.

D7–D0

NeTime-Out Counter Terminal Count Value

The function’s terminal counter is 8 bits wide and counts at
a rate of MCLK(0)/(2

17

). For example, if the MCLK frequen­cy is 30 MHz the device can be programmed to time-out
between 0.0s to 1.114s. The general formula is:

Time

e

(1/mclk) * 217* N,

where NeÀ0, 1, 2, . . . , 255

Ó

For a 5 MHz MCLK frequency, the equation is:

TimeeN (26.2144 ms) where NeÀ0,1,2, . . . ,255

Ó

Note: A value of zero implies the function is powered down.

Miscellaneous Register

[

0x03F0

]

D7 D6 D5 D4 –D0

FastEE RFU RFU EEPROMStartAddr

FastEEÐIf this bit is set to one (1), then the clock used to
access the EEPROM shall be MCLK/2. If this bit is set to
zero (0), the clock used to access the EEPROM shall be
MCLK/32.

EEPROMStartAddrÐThis field contains a starting address
for EEPROM read or write access. This is ordinarily set to
zero and is used for debug/test purposes.

Wait State Timer Register

[

0x03F6

]

This register allows the insertion of default wait states from
the PCM16C010 using HWAIT

Ý

. It is intended to be used in
situations where either the function is too slow to respond
with a CWAIT or the unique wait timing constraints between
the system and PC Card design necessitate a default wait
state.

D7–D4 D3–D2 D1–D0

Reserved Unused Func0Wait

Func0WaitÐThis value is the number (0, 1, 2, or 3) of
MCLK time periods that the PCM16C010 will assert
HWAIT

Ý

during a valid access to a particular function. For

Zero wait states, program this value to 00b.

NAND Flash (NM29N16) Configuration Register[0x03F8

]

D7–D4 D3 D2 D1 D0

Reserved memÐioÐspace NANDÐIOCS16 BC NANDÐEN

memÐioÐspaceÐMemÐioÐspace selects whether
NAND Read/Write strobes are generated by accesses to
common memory space or I/O space. When Function 0 is
configured for NAND Flash (NM29N16) Mode, if memÐio

Ð

space is set to 0, NAND (NM29N16) Read/Write strobes
are generated by an I/O access to the function 0 base ad­dress

a

4. If memÐioÐspace is set to 1, Read/Write
strobes are generated by any read/write access to common
memory.

NANDÐIOCS16ÐWhen the Function is configured for
NAND Flash (NM29N16) Mode, D2 replaces the external
pin IOCS16

Ý

to allow the host to know if the NAND
(NM29N16) is organized for 8- or 16-bit accesses. If the
Function is NOT configured for NAND Flash (NM29N16)
Mode, the bit performs no function. This register gets down­loaded during EEPROM reads.

BCÐIf set to zero (0), PCM16C010 will assert only one of
the four external CE

Ý

pins at a time, (based on the value of
bits D0 and D1 in the Device Select Register), allowing up to
four unique enable control lines. If set to one (1),
PCM16C010 will place on the external CE

Ý

lines the exact
binary number placed in bits D0 – D3 of the Device Select
Register. This will allow external decoding to produce up to
15 unique CE

Ý

control lines which can control up to 30
pairs of NAND Flash (NM29N16) devices. (Reference table
in Section 5.4.4 for details.)

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5.0 Functional Description (Continued)

NANDÐENÐThis bit, if set to one (1), configures the func-

tion as a NAND Flash (NM29N16) interface (see Section

5.4.4 for specific function details). If set to zero (0), the func­tion assumes normal I/O interface functionality.

Watchdog Time-Out Register

[

0x03FC

]

D7 D6 D5– D0

RFU WaitÐTout Enable RFU

WaitÐTout EnableÐWhen this bit is set to a one (1), the
HWAIT

Ý

time-out watchdog timer is enabled. In addition,

the ability to set

Intr

in the Function Configuration Option

Register,

Intr

in the Card Configuration Register, and

IREQ

Ý

is enabled once the watchdog timer expires. The

watchdog timer may expire if HWAIT

Ý

is asserted for more
than approximately 11.2 ms when MCLK is set to 20 MHz.
This prevents the system from hanging due to prolonged
HWAIT

Ý

assertions. If this bit is reset to zero (0), Wait

Ð

Tout and its associated interrupt capability is disabled during
HWAIT assertions.

ID Register

[

0x1000

]

This read only register provides the software with IC revision
information.

D7–D3 D2–D0

PCM16C010 Codee00010b Revision Codee001b

NSC PCM16C010 CodeÐThis code may be used to identi­fy the NSC PCM16C010 IC. The value of bits D7 –D3 of this
register is 00010, which when appended to the three bits of
the revision code produce: 00010 xxx; which is 1x hex.

Revision CodeÐThis will uniquely identify the silicon ver­sion of the PCM16C010 IC as 001b.

EEPROM Access

In order to avoid accidental EEPROM overwrite, the
PCM16C010 utilizes two registers that must be written with
the proper byte sequence in order to enable EEPROM
writes. In order to initiate an EEPROM write, the following
register write sequence must be executed:

Register Attribute Register Address Hex Data

EE Control Reg 1002 2E
EE Security Reg 1004 B7
EE Control Reg 1002 91

Failure to initiate the exact sequence will disable writes
regardless of the value placed in the WriteEEPROM or
EEPROMWriteEn bits of the EEPROM Control Register.

EEPROM Control Register

[

0x1002

]

This register (in conjunction with the EEPROM Security
Register for writes) controls reading and writing the
EEPROM as well as the EEPROM enable.

D7 D6 D5 –D1 D0

WriteEEPROM ReadEEPROM Reserved EEPROMWriteEn

WriteEEPROMÐWhen set, this tells the EEPROM control­ler to copy the contents of the PCM16C010 Shadow RAM to
the EEPROM, provided the proper write security sequence
listed above has been executed. Once the EEPROM write
has completed, the EEPROM controller clears this bit.

ReadEEPROMÐWhen set, this tells the EEPROM control­ler to copy the contents of the EEPROM to the shadow
RAM. Once done, the EEPROM controller clears this bit.
Any data modified in the Shadow RAM that has not first
been written back to the EEPROM will be lost. The
EEPROM may be read independent of the value in the
EEPROMWriteEnable bit.

EEPROMWriteEnÐThis must be set to allow EEPROM
writes. If clear, the EEPROM may not be written. The default
value at reset is low. The EEPROM may be read indepen­dent of the value of this bit.

Note 1: Upon power-up, the PCM16C010 EEPROM controller copies the

entire contents of the lower 1 kbytes of the EEPROM into the Shad­ow RAM independent of writing to the EEPROM Control Register.

Note 2: The PCM16C010 EEPROM controller stores data in a 16-bit orga-

nized EEPROM in low/high format. Although Attribute Memory is
on even byte boundaries only, the entire EEPROM’s address space
is used. This eliminates waste of EEPROM memory. Therefore the
Attribute space used by the Shadow RAM is double the actual size
of the EEPROM. For example, if a 16-bit EEPROM is pre-pro­grammed, the low byte at word 0 in the EEPROM will be shadowed
at Attribute location 0x0000 and the high byte will be shadowed at
Attribute location 0x0002. The low byte at EEPROM word 1 will be
shadowed to Attribute location 0x0004, etc.

EEPROM Security Register

[

0x1004

]

This register in conjunction with the EEPROM Control Reg­ister is used to prevent accidental EEPROM overwriting.
When written in the proper sequence as outlined above with
hex data B7, it allows EEPROM write access.

5.3.2 PC Card Register

Function Configuration Option Register

[

0x1020

]

D7 D6 D5– D0

SRESET LevIREQ Function Configuration Index

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5.0 Functional Description (Continued)

SRESETÐIf the host sets this field to one (1), the

PCM16C010 shall place the given function in the reset
state. When the host returns this field to zero (0), the func­tion shall enter the same unconfigured, reset state as it
does following a power-up and hardware reset. Note that
SRESET does not reset the PCM16C010 thus the Attribute
memory is not reloaded.

LevIREQÐWhen the PCM16C010 is being used as a PC
Card I/O interface and this field is set to one (1), the
PCM16C010 shall generate Level Mode interrupts for the
function using the IREQ

Ý

signal. If the PCM16C010 is being
used as a PC Card I/O interface and this field is set to zero
(0), the PCM16C010 shall generate Pulse Mode interrupts
for the function. Use of Level Mode interrupts is strongly
recommended. The PCM16C010 will also only allow a write
to the LevIREQ bit value to change the interfaces Interrupt
level mode if the given function is configured using
ConfFunc and interrupts are enabled using EnbIREQ.
In addition, the PCM16C010 provides an enhanced interrupt
protocol scheme described by the IntrReset bit in the Func­tion Configuration Status Register. Function configurations
may use Level Mode or Pulse Mode interrupt schemes.
Pulsed Mode interrupt width is given by:

TwidthIREQ

e

16/(FreqMCLK(0))

Using MCLK from 5 MHz – 30 MHz will insure pulse widths
from 0.53 ms –3.2 ms which exceed the 0.5 ms minimum
requirement for the PC Card Standard.

Function Configuration IndexÐWhen the host system
sets this field to the value of the Configuration Entry Number
field of a Configuration Table Entry Tuple, the function shall
enter the configuration described by that tuple. This field
shall be reset to zero (0) by the PCM16C010 when the host
sets the SRESET field to one (1) or the host asserts
RESET. If this field is set to zero (0) explicitly by the host or
implicitly by SRESET or RESET, the function shall use the
Memory Only interface and I/O cycles from the host shall
be ignored by the function.

The following configurations are supported by the Function
Configuration Index.

ConfFunc (D0)ÐIf this is set to one (1), then the PC Card is
configured for that function.

EnbBaseÐLimit (D1)ÐIf this is set to a one (1), the base
and limit register pair for the function is enabled. That is, the
PCM16C010 will only pass I/O transactions whose address
falls within the I/O window specified by the base and limit
pair. If this is set to a zero (0), the PCM16C010 will not test
transactions’ addresses against the base and limit pair for

that function and will, therefore, pass all I/O transactions to
the function. For function operation, the EnbBaseÐLimit
would be enabled for operation with host controllers that
support overlapping windowing and the INPACK

Ý

signal.

For host controllers that do not support INPACK

Ý

but are
capable of windowing granularity required for the function,
EnbBaseÐLimit may be set to zero (0) so that all I/O trans­actions are passed to the function.

EnbIREQ (D2)ÐWhen the PCM16C010 is being used as a
PC Card I/O interface and this field is set to one (1), the
PCM16C010 shall enable this function to interrupt the host
using the IREQ

Ý

signal. Normally this bit would be set to
one (1). In environments where the function’s software driv­er will use a polling technique for status information, this bit
could be set to zero (0) to disable interrupts from that func­tion.

PMGMTÐEN (D3)ÐThis bit, if set to a one (1), enables the
hardware power management controller to control the
PCNTL pin for that function. See the PMGR and Clock Reg­ister description.

TESTÐMODE(D4)ÐThe TESTÐMODE bit

MUST

be set to
zero (0) for the function to operate in the normal I/O mode
(default state). TESTÐMODE is for NSC factory use only.
Normal card functionallity is not guaranteed in TEST

Ð

MODE.

(D5) is reserved.

Function Configuration Status Register

[

0x1022

]

These PC Card registers are used for function control/
status information.

D7 D6 D5 D4 D3 D2 D1 D0

Changed SigChg IOis8 Reserved Audio PwrDn Intr IntrReset

ChangedÐIf one or more of the state change signals in the
Function Pin Replacement Register are set to one (1), the
PCM16C010 shall set this field to a one (1). If the
PCM16C010 is being operated as a I/O interface, (PC Card
using I/O Interface), and both the Changed and SigChg
fields are set to one (1), the PCM16C010 shall assert the
STSCHG

Ý

signal. If the PC Card, and hence PCM16C010,
is not using the I/O interface, this field is undefined and
ignored.

SigChgÐThis field serves as a gate for asserting the
STSCHG signal. If the PCM16C010 is operated as an I/O
interface, and both the Changed and SigChg fields are set
to one (1), the PCM16C010 shall assert the PC Card
STSCHG

Ý

signal. If the PCM16C010 is operated as an I/O
interface and this field is reset to a zero (0), the

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