NSC PC97317-IBW-VUL, PC97317-ICK-VUL, PC97317-ICL-VUL Datasheet
1
- February 1998
Highlights
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©
1998 National Semiconductor Corporation
PRELIMINARY
February 1998
PC87317VUL/PC97317VUL SuperI/O Plug and Play
Compatible with ACPI Compliant Controller/Extender
Highlights
General Description
The PC87317VUL/PC97317VUL are functionally identical
parts that offer a single-chip solution to the most commonly
used ISA, EISA and MicroChannel
®
peripherals. This fully
Plug and Play (PnP) compatible chip conforms to the
Plug
and Play ISA Specification
Version 1.0a, May 5, 1994, and
meets specifications defined in the
PC97 Hardware Design
Guide
. It features a Controller/Extender that is fully compliant with Advanced Configuration and Power Interface (ACPI) Revision 1.0 requirements.
Note: All references to the PC87317VUL in this document
also refer to the PC97317VUL, unless otherwise specified.
References which are applicable to the PC97317VUL only
are italicized.
The PC87317VUL incorporates: an advanced Real-Time
Clock (RTC) device that provides both RTC timekeeping and
Advanced Power Control (APC) functionality, a Floppy Disk
Controller (FDC), a Keyboard and Mouse Controller (KBC),
two enhanced Serial Ports (UARTs) with Infrared (IR) support, a full IEEE 1284 Parallel Port, 24 General-Purpose Input/Output (GPIO) bit ports, three general-purpose chip
select signals that can be programmed for game port control
and a separate configuration register set for each module.
The PC87317VUL provides a LED drive output to comply
with PC97 specifications. The chip also provides support for
Power Management (PM), including a WATCHDOG timer,
and standard PC-AT address decoding for on-chip functions.
The PC87317VUL Infrared (IR) interface complies with the
HP-SIR and SHARP-IR standards, and supports all four basic protocols for Consumer Remote Control circuitry (RC-5,
RC-5 extended, RECS80 and NEC).
Outstanding Features
Among the most advanced members of National Semiconductor’s highly successful SuperI/O family, the PC87317VUL
offers:
●
Full compatibility with ACPI Revision 1.0 requirements
●
Compliancy with
PC97 Hardware Design Guide
speci-
fications, including PC97 LED support
●
Advanced RTC, including timekeeping and APC functionality
●
24 GPIO bit ports
●
FDC, KBC, two enhanced UARTs, IR support, IEEE
1284 parallel port
Block Diagram
Real-Time Clock
Floppy Disk
Controller (FDC)
Keyboard + Mouse
Controller (KBC)
Management (PM
)
µP Address
Floppy Drive
Interface
Data Handshake
Data
X-Bus
Control
Parallel Port
(PnP)
IRQ
Control
DMA
Channels
(RTC and APC)
Plug and Play
Data and
Control
General-Purpose I/O
(GPIO) Registers
I/O Ports
Control
Control
Data and
IEEE 1284
(Logical Device 2)
(Logical Devices 0 & 1)
(Logical Device 8)
(Logical Device 4)
(Logical Device 7)
(Logical Device 3)
Ports
Serial
with IR (UART2)
Interface
Infrared
Interface
(Logical Devices 5)
Power
Serial
(UART1)
Interface
(Logical Devices 6)
Serial Port Serial Port
TRI-STATE® and WATCHDOG are trademarks of National Semiconductor Corporation.
IBM
®
, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft
®
and Windows® are registered trademarks of Microsoft Corporation.
2
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Features
●
100% compatibility with PnP requirements specified in
the “
Plug and Play ISA Specification
”, ISA, EISA, and
MicroChannel architectures
●
A special PnP module that includes:
— Flexible IRQs, DMAs and base addresses that meet
the PnP requirements specified by Microsoft
®
in
their 1995 hardware design guide for Windows
®
and
PnP ISA Revision 1.0A
— PnP ISA mode (with isolation mechanism – Wait for
Key state)
— Motherboard PnP mode
●
An FDC that provides:
— A modifiable address that is referenced by a 16-bit
programmable register
— Software compatibility with the PC8477, which con-
tains a superset of the floppy disk controller functions in the µDP8473, the NEC µPD765A and the
N82077
— 13 IRQ channel options
— Four 8-bit DMA channel options
— 16-byte FIFO
— Burst and non-burst modes
— A new, high-performance, internal, digital data sep-
arator that does not require any external filter components
— Support for standard 5.25" and 3.5" floppy disk
drives
— Automatic media sense support
— Perpendicular recording drive support
— Three-mode Floppy Disk Drive (FDD) support
— Full suppor t for the IBM Tape Dr ive Register (TDR)
implementation of AT and PS/2 drive types
●
A KBC with:
— A modifiable address that is referenced by a 16-bit
programmable register, reported as a fixed address
in resource data
— 13 IRQ options for the Keyboard Controller
— 13 IRQ options for the Mouse Controller
— An 8-bit microcontroller
— Software compatibility with 8042AH and PC87911
microcontrollers
— 2 KB of custom-designed program ROM
— 256 bytes of RAM for data
— Five programmable dedicated open drain I/O lines
for keyboard controller applications
— Asynchronous access to two data registers and one
status register during normal operation
— Support for both interrupt and polling
— 93 instructions
— An 8-bit timer/counter
— Support for binary and BCD arithmetic
— Operation at 8 MHz,12 MHz or 16 MHz (programma-
ble option)
— Customizing by using the PC87323VUL, which in-
cludes a RAM-based KBC, as a development platform for keyboard controller code for the
PC87317VUL
●
An RTC that has:
— A modifiable address that is referenced by a 16-bit
programmable register
— 13 IRQ options, with programmable polarity
— DS1287, MC146818 and PC87911 compatibility
— 242 bytes of battery backed up CMOS RAM in two
banks
— Selective lock mechanisms for the RTC RAM
— Battery backed up century calendar in days, day of
the week, date of month, months, years and century ,
with automatic leap-year adjustment
— Battery backed-up time of day in seconds, minutes
and hours that allows a 12 or 24 hour format and adjustments for daylight savings time
— BCD or binary format for time keeping
— Three different maskable interrupt flags:
• Periodic interrupts - At intervals from 122 msec
to 500 msec
• Time-of-Month alarm - At intervals from once per
second to once per Month
• Updated Ended Interrupt - Once per second
upon completion of update
— Separate battery pin, 2.4 V operation that includes
an internal UL protection resistor
— 2 µA maximum power consumption during power
down
— Double-buffer time registers
●
ACPI Controller/Extender that supports the requirements of the ACPI spec (rev 1.0):
— Power Management Timer
— Power Button
— Real Time Clock Alarm
— Suspend modes via software emulation
— PnP SCI
— Global Lock mechanism
— General Purpose events
— Date of Month Alarm
— Century byte
●
An APC that controls the main power supply to the system, using open-drain output, as follows:
Power turned on when:
— The RTC reaches a pre-determined wake-up centu-
ry, date and time selection
— A high to low transition occurs on the RI input signals
of the UARTs
— A ring pulse or pulse train is detected on the RING
input signal
— A SWITCH input signal indicates a Switch On event
with a debounce-protection
— Any one of seven programmable Power Manage-
ment external trigger events occur
Powered turned off when:
— A SWITCH input signal indicates a Switch Off event
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— A Fail-safe ev ent occurs (power-sav e mode detected
but the system is hung up)
— Software turns power off
— Any one of 10 programmable Power Management
trigger events occur
●
Two Serial Ports (UART1 and 2) that provide:
— Fully compatible with the 16550A and the 16450
— Extended UART mode
— 13 IRQ channel options
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
●
An enhanced UART with IR interface on the UART2 that
supports:
— IrDA 1.0-SIR
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control circuitry
— DMA handshake signal routing for either 1 or 2 chan-
nels
— A PnP compatible external transceiver
●
A bidirectional parallel port that includes:
— A modifiable address that is referenced by a 16-bit
programmable register
— Software or hardware control
— 13 IRQ channel options
— Four 8-bit DMA channel options
— Demand mode DMA support
— An Enhanced Parallel Port (EPP) that is compatible
with the new version EPP 1.9, and is IEEE 1284
compliant
— An Enhanced Parallel Port (EPP) that also supports
version EPP 1.7 of the Xircom specification
— Support for an Enhanced Parallel Port (EPP) as
mode 4 of the Extended Capabilities Port (ECP)
— An Extended Capabilities Port (ECP) that is IEEE
1284 compliant, including level 2
— Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
— Reduction of PCI bus utilization by supporting a de-
mand DMA mode mechanism and a DMA fairness
mechanism
— A protection circuit that prevents damage to the par-
allel port when a printer connected to it powers up or
is operated at high voltages
— Output buffers that can sink and source14 mA
●
Three general-purpose pins for three separate programmable chip select signals, as follows:
— Can be programmed for game port control
— The Chip Select 0 (
CS0) signal produces open drain
output and is powered by the V
CCH
— The Chip Select 1 (CS1) and 2 (CS2) signals have
push-pull buffers and are pow ered b y the main V
DD
— Decoding of chip select signals depends on the ad-
dress and the Address Enable (AEN) signals, and
can be qualified using the Read (
RD) and Write
(
WR) signals.
●
24 single-bit GPIO ports:
— Modifiable addresses that are referenced by a 16-bit
programmable register
— Programmable direction for each signal (input or out-
put)
— Programmable drive type for each output pin (open-
drain or push-pull)
— Programmable option for internal pull-up resistor on
each input pin
— Configuration-Lock options
— Several signals may be selected as interrupt triggers
— A back-drive protection circuit
●
An X-bus data buffer that connects the 8-bit X data bus
to the ISA data bus
●
Clock source options:
— Source is a 32.768 KHz crystal - an internal frequen-
cy multiplier generates all the required internal fre-
quencies.
— Source may be either a 48 MHz or 24 MHz clock in-
put signal.
●
Enhanced Power Management (PM), including:
— Special configuration registers for power down
— WATCHDOG timer for power-saving strategies
— Reduced current leakage from pins
— Low-power CMOS technology
— Ability to shut off clocks to all modules
— LED control powered by V
CCH
●
General features include:
— All accesses to the SuperI/O chip activate a Zero
Wait State (
ZWS) signal, except for accesses to the
Enhanced Parallel Por t (EPP) and to configuration
registers
— Access to all configuration registers is through an In-
dex and a Data register, which can be relocated
within the ISA I/O address space
— 160-pin Plastic Quad Flatpack (PQFP) package
4
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Basic Configuration
DRATE0
Parallel
Port
Connector
Configuration
Select Logic
Clock
EIA
Drivers
EIA
Drivers
FDC
ONCTL
ISA Bus
X1
MR
AEN
A15-0
D7-0
RD
WR
TC
PD7-0
SLIN/ASTRB
STB/WRITE
AFD/DSTRB
INIT
ACK
ERR
SLCT
PE
BUSY/
WAIT
BADDR1,0
CFG1,0
V
CCH
SWITCH
RING
SIN1
SOUT1
RTS1
DTR1/BOUT1
CTS1
DSR1
DCD1
RI1
SIN2
SOUT2
RTS2
DTR2/BOUT2
CTS2
DSR2
DCD2
RI2
RDATA
WDATA
WGATE
HDSEL
DIR
STEP
TRK0
INDEX
DSKCHG
WP
MTR1,0
DR1,0
DENSEL
IOCHRDY
ZWS
Real-Time Clock (RTC)
Crystal and Power
V
BAT
X1C X2C
DRQ3-0
DACK3-0
P17,16,12
P21,20
KBCLK
KBDAT
MDAT
MCLK
Keyboard I/O
Interface
(GPIO)
CS2,0
MSEN1,0
GPIO27-20
GPIO17-10
IRQ1
Infrared (IR)
Interface
IRRX2,1
IRTX
PC87317VUL
IRQ12-3
IRQ15-14
IRSL2-0
SELCS
X-Bus
XDCS
XD7-0
XDRD
WDO
POR
ID3-0
GPIO37-30
LED
LED
Power
Management
(PM)
Connector
General Purpose I/O
5
Table of Contents
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Table of Contents
Highlights.......................................................................................................................................................1
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM .........................................................................................................16
1.2 SIGNAL/PIN DESCRIPTIONS ...................................................................................................17
2.0 Configuration
2.1 HARDWARE CONFIGURATION ...............................................................................................27
2.1.1 Wake Up Options ........................................................................................................27
2.1.2 The Index and Data Register Pair ...............................................................................27
2.1.3 The Strap Pins .............................................................................................................28
2.2 SOFTWARE CONFIGURATION ...............................................................................................28
2.2.1 Accessing the Configuration Registers ........................................................................28
2.2.2 Address Decoding .......................................................................................................28
2.3 THE CONFIGURATION REGISTERS .......................................................................................29
2.3.1 Standard Plug and Play (PnP) Register Definitions ....................................................30
2.3.2 Configuration Register Summary ................................................................................33
2.4 CARD CONTROL REGISTERS ................................................................................................37
2.4.1 PC87317 SID Register ................................................................................................37
2.4.2 PC97317 SID Register ................................................................................................37
2.4.3 SuperI/O Configuration 1 Register (SIOC1) ................................................................37
2.4.4 SuperI/O Configuration 2 Register (SIOC2) ................................................................38
2.4.5 Programmable Chip Select Configuration Index Register ...........................................38
2.4.6 Programmable Chip Select Configuration Data Register ............................................39
2.4.7 SuperI/O Configuration 3 Register (SIOC3) ................................................................39
2.4.8 PC97317 SRID Register ..............................................................................................39
2.4.9 SuperI/O Configuration F Register (SIOCF), Index 2Fh ..............................................40
2.5 KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) ....................................................40
2.5.1 SuperI/O KBC Configuration Register .........................................................................40
2.6 FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 3) ..................................................40
2.6.1 SuperI/O FDC Configuration Register .........................................................................40
2.6.2 Drive ID Register .........................................................................................................41
2.7 PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4) ...............................41
2.7.1 SuperI/O Parallel Port Configuration Register .............................................................41
2.8 UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5) ....................42
2.8.1 SuperI/O UART2 Configuration Register .....................................................................42
2.9 UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 6) ................................................42
2.9.1 SuperI/O UART1 Configuration Register .....................................................................42
2.10 PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS ......................................42
2.10.1 CS0 Base Address MSB Register ...............................................................................43
2.10.2 CS0 Base Address LSB Register ................................................................................43
2.10.3 CS0 Configuration Register .........................................................................................43
2.10.4 Reserved .....................................................................................................................43
2.10.5 CS1 Base Address MSB Register ...............................................................................43
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2.10.6 CS1 Base Address LSB Register ................................................................................43
2.10.7 CS1 Configuration Register .........................................................................................43
2.10.8 Reserved .....................................................................................................................44
2.10.9 CS2 Base Address MSB Register ...............................................................................44
2.10.10 CS2 Base Address LSB Register ................................................................................44
2.10.11 CS2 Configuration Register .........................................................................................44
2.10.12 Reserved, Second Level Indexes 0Bh-0Fh .................................................................44
2.10.13 Not Accessible, Second Level Indexes 10h-FFh .........................................................44
2.11 CONFIGURATION REGISTER BITMAPS ................................................................................44
3.0 Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
3.1 SYSTEM ARCHITECTURE .......................................................................................................47
3.2 FUNCTIONAL OVERVIEW .......................................................................................................48
3.3 DEVICE CONFIGURATION ......................................................................................................48
3.3.1 I/O Address Space ......................................................................................................48
3.3.2 Interrupt Request Signals ............................................................................................48
3.3.3 KBC Clock ...................................................................................................................49
3.3.4 Timer or Event Counter ...............................................................................................50
3.4 EXTERNAL I/O INTERFACES ..................................................................................................50
3.4.1 Keyboard and Mouse Interface ...................................................................................50
3.4.2 General Purpose I/O Signals .......................................................................................50
3.5 INTERNAL KBC - PC87317VUL INTERFACE ..........................................................................51
3.5.1 The KBC DBBOUT Register, Offset 60h, Read Only ..................................................52
3.5.2 The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ............52
3.5.3 The KBC STATUS Register ........................................................................................52
3.6 INSTRUCTION TIMING .............................................................................................................52
4.0 Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.1 RTC OVERVIEW .......................................................................................................................53
4.1.1 RTC Hardware and Functional Description .................................................................53
4.1.2 Timekeeping ................................................................................................................54
4.1.3 Power Management ....................................................................................................55
4.1.4 Interrupt Handling ........................................................................................................56
4.2 THE RTC REGISTERS .............................................................................................................56
4.2.1 RTC Control Register A (CRA) ....................................................................................56
4.2.2 RTC Control Register B (CRB) ....................................................................................57
4.2.3 RTC Control Register C (CRC) ...................................................................................58
4.2.4 RTC Control Register D (CRD) ...................................................................................58
4.2.5 Date-of-Month Alarm Register (DMAR ........................................................................59
4.2.6 Month Alarm Register (MAR) ......................................................................................59
4.2.7 Century Register (CR) .................................................................................................59
4.3 APC OVERVIEW .......................................................................................................................59
4.3.1 System Power States ..................................................................................................61
4.3.2 System Power Switching Logic ...................................................................................62
4.4 APC DETAILED DESCRIPTION ...............................................................................................62
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4.4.1 The ONCTL Flip-Flop and Signal ................................................................................62
4.4.2 Entering Power States .................................................................................................65
4.4.3 System Power-Up and Power-Off Activation Event Description ..................................67
4.5 APC REGISTERS ......................................................................................................................69
4.5.1 APC Control Register 1 (APCR1) ................................................................................70
4.5.2 APC Control Register 2 (APCR2) ................................................................................70
4.5.3 APC Status Register (APSR) ......................................................................................71
4.5.4 Wake up Day of Week Register (WDWR) ...................................................................71
4.5.5 Wake up Date of Month Register (WDMR) .................................................................72
4.5.6 Wake up Month Register (WMR) .................................................................................72
4.5.7 Wake up Year Register (WYR) ....................................................................................72
4.5.8 RAM Lock Register (RLR) ...........................................................................................72
4.5.9 Wake up Century Register (WCR) ..............................................................................73
4.5.10 APC Control Register 3 (APCR3) ................................................................................73
4.5.11 APC Control Register 4 (APCR4), Bank 2, Index 4Ah ................................................74
4.5.12 APC Control Register 5 (APCR5) ................................................................................75
4.5.13 APC Control Register 6 (APCR6) ................................................................................75
4.5.14 APC Control Register 7 (APCR7) ................................................................................76
4.5.15 APC Status Register 1 (APSR1) .................................................................................77
4.5.16 Day-of-Month Alarm Address Register (DADDR) ........................................................77
4.5.17 Month Alarm Address Register (MADDR) ...................................................................77
4.5.18 Century Address Register (CADDR) ...........................................................................77
4.6 ACPI FIXED REGISTERS .........................................................................................................78
4.6.1 Power Management 1 Status Low Byte Register (PM1_STS_LOW) ..........................78
4.6.2 Power Management 1 Status High Byte Register (PM1_STS_HIGH) ........................78
4.6.3 Power Management 1 Enable Low Byte Register (PM1_EN_LOW) ...........................79
4.6.4 Power Management 1 Enable High Byte Register (PM1_EN_HIGH) .........................79
4.6.5 Power Management 1 Control Low Byte Register (PM1_CNT_LOW) ........................80
4.6.6 Power Management 1 Control High Byte Register (PM1_CNT_HIGH) .......................80
4.6.7 Power Management Timer Low Byte Register (PM1_TMR_LOW) .............................80
4.6.8 Power Management Timer Middle Byte Register (PM1_TMR_MID) ...........................81
4.6.9 Power Management Timer High Byte Register (PM1_TMR_HIGH) ............................81
4.6.10 Power Management Timer Extended Byte Register (PM1_TMR_EXT) ......................81
4.7 GENERAL PURPOSE EVENT REGISTERS ............................................................................81
4.7.1 General Purpose 1 Status Register (GP1_STS0) .......................................................81
4.7.2 General Purpose 1 Status 1 Register (GP1_STS1), Offset 01h ..................................82
4.7.3 General Purpose 1 Status 2 Register (GP1_STS2), Offset 02h ..................................82
4.7.4 General Purpose 1 Status 3 Register (GP1_STS3), Offset 03h ..................................82
4.7.5 General Purpose 1 Enable 0 Register (GP1_EN0) .....................................................82
4.7.6 General Purpose 1 Enable 1 Register (GP1_EN1), Offset 05h ...................................83
4.7.7 General Purpose 1 Enable 2 Register (GP1_EN2), Offset 06hr .................................83
4.7.8 General Purpose 1 Enable 3 Register (GP1_EN3), Offset 07h ...................................83
4.7.9 General Purpose 2 Enable 0 Register (GP2_EN0) .....................................................83
4.7.10 Bit 3 - IRRX2 Enable (IRRX2_E) .................................................................................83
4.7.11 SMI Command Register (SMI_CMD), Offset 0Ch .......................................................83
4.8 RTC AND APC REGISTER BITMAPS ......................................................................................84
4.8.1 RTC Register Bitmaps .................................................................................................84
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4.8.2 APC Register Bitmaps .................................................................................................84
4.9 REGISTER BANK TABLES .......................................................................................................89
5.0 The Digital Floppy Disk Controller (FDC) (Logical Device 3)
5.1 FDC FUNCTIONS .....................................................................................................................92
5.1.1 Microprocessor Interface .............................................................................................92
5.1.2 System Operation Modes ............................................................................................92
5.2 DATA TRANSFER .....................................................................................................................93
5.2.1 Data Rates ...................................................................................................................93
5.2.2 The Data Separator .....................................................................................................93
5.2.3 Perpendicular Recording Mode Support .....................................................................94
5.2.4 Data Rate Selection .....................................................................................................94
5.2.5 Write Precompensation ...............................................................................................95
5.2.6 FDC Low-Power Mode Logic .......................................................................................95
5.2.7 Reset ...........................................................................................................................95
5.3 THE FDC REGISTERS .............................................................................................................96
5.3.1 Status Register A (SRA) ..............................................................................................96
5.3.2 Status Register B (SRB) ..............................................................................................97
5.3.3 Digital Output Register (DOR) .....................................................................................97
5.3.4 Tape Drive Register (TDR) ..........................................................................................99
5.3.5 Main Status Register (MSR) ......................................................................................100
5.3.6 Data Rate Select Register (DSR) ..............................................................................101
5.3.7 Data Register (FIFO) .................................................................................................102
5.3.8 Digital Input Register (DIR) ........................................................................................103
5.3.9 Configuration Control Register (CCR) .......................................................................104
5.4 THE PHASES OF FDC COMMANDS .....................................................................................104
5.4.1 Command Phase .......................................................................................................104
5.4.2 Execution Phase ........................................................................................................104
5.4.3 Result Phase .............................................................................................................106
5.4.4 Idle Phase ..................................................................................................................106
5.4.5 Drive Polling Phase ...................................................................................................106
5.5 THE RESULT PHASE STATUS REGISTERS ........................................................................107
5.5.1 Result Phase Status Register 0 (ST0) .......................................................................107
5.5.2 Result Phase Status Register 1 (ST1) .......................................................................107
5.5.3 Result Phase Status Register 2 (ST2) .......................................................................108
5.5.4 Result Phase Status Register 3 (ST3) .......................................................................109
5.6 FDC REGISTER BITMAPS .....................................................................................................109
5.6.1 Standard ....................................................................................................................109
5.6.2 Result Phase Status ..................................................................................................111
5.7 THE FDC COMMAND SET .....................................................................................................112
5.7.1 Abbreviations Used in FDC Commands ....................................................................113
5.7.2 The CONFIGURE Command ....................................................................................114
5.7.3 The DUMPREG Command .......................................................................................114
5.7.4 The FORMAT TRACK Command .............................................................................115
5.7.5 The INVALID Command ............................................................................................117
5.7.6 The LOCK Command ................................................................................................118
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5.7.7 The MODE Command ...............................................................................................119
5.7.8 The NSC Command ..................................................................................................121
5.7.9 The PERPENDICULAR MODE Command ...............................................................121
5.7.10 The READ DATA Command .....................................................................................122
5.7.11 The READ DELETED DATA Command ....................................................................124
5.7.12 The READ ID Command ...........................................................................................125
5.7.13 The READ A TRACK Command ...............................................................................126
5.7.14 The RECALIBRATE Command .................................................................................127
5.7.15 The RELATIVE SEEK Command ..............................................................................127
5.7.16 The SCAN EQUAL, the SCAN LOW OR EQUAL and the SCAN HIGH OR EQUAL
Commands ................................................................................................................128
5.7.17 The SEEK Command ................................................................................................129
5.7.18 The SENSE DRIVE STATUS Command ..................................................................129
5.7.19 The SENSE INTERRUPT Command ........................................................................130
5.7.20 The SET TRACK Command ......................................................................................131
5.7.21 The SPECIFY Command ..........................................................................................131
5.7.22 The VERIFY Command .............................................................................................133
5.7.23 The VERSION Command ..........................................................................................134
5.7.24 The WRITE DATA Command ....................................................................................134
5.7.25 The WRITE DELETED DATA Command ..................................................................135
5.8 EXAMPLE OF A FOUR-DRIVE CIRCUIT ...............................................................................136
6.0 Parallel Port (Logical Device 4)
6.1 PARALLEL PORT CONFIGURATION ....................................................................................137
6.1.1 Parallel Port Operation Modes ..................................................................................137
6.1.2 Configuring Operation Modes ....................................................................................137
6.1.3 Output Pin Protection ................................................................................................137
6.2 STANDARD PARALLEL PORT (SPP) MODES ......................................................................137
6.2.1 SPP Modes Register Set ...........................................................................................138
6.2.2 SPP Data Register (DTR) ..........................................................................................138
6.2.3 Status Register (STR) ...............................................................................................139
6.2.4 SPP Control Register (CTR) ......................................................................................140
6.3 ENHANCED PARALLEL PORT (EPP) MODES ......................................................................141
6.3.1 EPP Register Set .......................................................................................................141
6.3.2 SPP or EPP Data Register (DTR) .............................................................................141
6.3.3 SPP or EPP Status Register (STR) ...........................................................................141
6.3.4 SPP or EPP Control Register (CTR) .........................................................................142
6.3.5 EPP Address Register (ADDR) .................................................................................142
6.3.6 EPP Data Register 0 (DATA0) ..................................................................................142
6.3.7 EPP Data Register 1 (DATA1) ..................................................................................142
6.3.8 EPP Data Register 2 (DATA2) ..................................................................................142
6.3.9 EPP Data Register 3 (DATA3) ..................................................................................143
6.3.10 EPP Mode Transfer Operations ................................................................................143
6.3.11 EPP 1.7 and 1.9 Zero Wait State Data Write and Read Operations .........................144
6.4 EXTENDED CAPABILITIES PARALLEL PORT (ECP) ...........................................................145
6.4.1 ECP Modes ...............................................................................................................145
6.4.2 Software Operation ....................................................................................................145
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6.4.3 Hardware Operation ..................................................................................................145
6.5 ECP MODE REGISTERS ........................................................................................................145
6.5.1 Accessing the ECP Registers ....................................................................................146
6.5.2 Second Level Offsets ................................................................................................146
6.5.3 ECP Data Register (DATAR) .....................................................................................147
6.5.4 ECP Address FIFO (AFIFO) Register .......................................................................147
6.5.5 ECP Status Register (DSR) .......................................................................................147
6.5.6 ECP Control Register (DCR) .....................................................................................148
6.5.7 Parallel Port Data FIFO (CFIFO) Register .................................................................148
6.5.8 ECP Data FIFO (DFIFO) Register .............................................................................148
6.5.9 Test FIFO (TFIFO) Register ......................................................................................149
6.5.10 Configuration Register A (CNFGA) ...........................................................................149
6.5.11 Configuration Register B (CNFGB) ...........................................................................149
6.5.12 Extended Control Register (ECR) .............................................................................150
6.5.13 ECP Extended Index Register (EIR) .........................................................................151
6.5.14 ECP Extended Data Register (EDR) .........................................................................152
6.5.15 ECP Extended Auxiliary Status Register (EAR) ........................................................152
6.5.16 Control0 Register .......................................................................................................152
6.5.17 Control2 Register .......................................................................................................152
6.5.18 Control4 Register .......................................................................................................153
6.5.19 PP Confg0 Register ...................................................................................................153
6.6 DETAILED ECP MODE DESCRIPTIONS ...............................................................................154
6.6.1 Software Controlled Data Transfer
(Modes 000 and 001) ................................................................................................154
6.6.2 Automatic Data Transfer
(Modes 010 and 011) ................................................................................................154
6.6.3 Automatic Address and Data Transfers (Mode 100) .................................................156
6.6.4 FIFO Test Access (Mode 110) ..................................................................................156
6.6.5 Configuration Registers Access
(Mode 111) ................................................................................................................156
6.6.6 Interrupt Generation ..................................................................................................156
6.7 PARALLEL PORT REGISTER BITMAPS ...............................................................................157
6.7.1 EPP Modes ................................................................................................................157
6.7.2 ECP Modes ...............................................................................................................158
6.8 PARALLEL PORT PIN/SIGNAL LIST ......................................................................................160
7.0 Enhanced Serial Port with IR - UART2 (Logical Device 5)
7.1 FEATURES ..............................................................................................................................161
7.2 FUNCTIONAL MODES OVERVIEW .......................................................................................161
7.2.1 UART Modes: 16450 or 16550, and Extended ..........................................................161
7.2.2 Sharp-IR, IrDA SIR Infrared Modes ...........................................................................161
7.2.3 Consumer IR Mode ...................................................................................................161
7.3 REGISTER BANK OVERVIEW ...............................................................................................161
7.4 UART MODES – DETAILED DESCRIPTION ..........................................................................162
7.4.1 16450 or 16550 UART Mode .....................................................................................162
7.4.2 Extended UART Mode ...............................................................................................163
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7.5 SHARP-IR MODE – DETAILED DESCRIPTION .....................................................................163
7.6 SIR MODE – DETAILED DESCRIPTION ................................................................................163
7.7 CONSUMER-IR MODE – DETAILED DESCRIPTION ............................................................164
7.7.1 Consumer-IR Transmission .......................................................................................164
7.7.2 Consumer-IR Reception ............................................................................................164
7.8 FIFO TIME-OUTS ....................................................................................................................165
7.8.1 UART, SIR or Sharp-IR Mode Time-Out Conditions .................................................165
7.8.2 Consumer-IR Mode Time-Out Conditions .................................................................165
7.8.3 Transmission Deferral ...............................................................................................165
7.9 AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE ..........................................165
7.11 BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS .................................................166
7.11.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD) .................................166
7.11.2 Interrupt Enable Register (IER) .................................................................................167
7.11.3 Event Identification Register (EIR) ............................................................................168
7.11.4 FIFO Control Register (FCR) .....................................................................................170
7.11.5 Link Control Register (LCR) and Bank Selection Register (BSR) .............................171
7.11.6 Bank Selection Register (BSR) .................................................................................172
7.11.7 Modem/Mode Control Register (MCR) ......................................................................172
7.11.8 Link Status Register (LSR) ........................................................................................174
7.11.9 Modem Status Register (MSR) ..................................................................................175
7.11.10 Scratchpad Register (SPR) .......................................................................................175
7.11.11 Auxiliary Status and Control Register (ASCR) ..........................................................176
7.12 BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS .........................................176
7.12.1 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), ..............................177
7.12.2 Link Control Register (LCR) and Bank Select Register (BSR) ..................................177
7.13 BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................177
7.13.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ...........................178
7.13.2 Extended Control Register 1 (EXCR1) ......................................................................179
7.13.3 Link Control Register (LCR) and Bank Select Register (BSR) ..................................180
7.13.4 Extended Control and Status Register 2 (EXCR2) ....................................................180
7.13.5 Reserved Register .....................................................................................................180
7.13.6 TX_FIFO Current Level Register (TXFLV) ................................................................180
7.13.7 RX_FIFO Current Level Register (RXFLV) ...............................................................181
7.14 BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS ..........................................181
7.14.1 Module Revision ID Register (MRID) ........................................................................181
7.14.2 Shadow of Link Control Register (SH_LCR) .............................................................181
7.14.3 Shadow of FIFO Control Register (SH_FCR) ............................................................182
7.14.4 Link Control Register (LCR) and Bank Select Register (BSR) ..................................182
7.15 BANK 4 – IR MODE SETUP REGISTER ................................................................................182
7.15.1 Reserved Registers ...................................................................................................182
7.15.2 Infrared Control Register 1 (IRCR1) ..........................................................................182
7.15.3 Link Control Register (LCR) and Bank Select Register (BSR) ..................................182
7.15.4 Reserved Registers ...................................................................................................182
7.16 BANK 5 – INFRARED CONTROL REGISTERS .....................................................................183
7.16.1 Reserved Registers ...................................................................................................183
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7.16.2 (LCR/BSR) Register ..................................................................................................183
7.16.3 Infrared Control Register 2 (IRCR2) ..........................................................................183
7.16.4 Reserved Registers ...................................................................................................183
7.17 BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS .........................183
7.17.1 Infrared Control Register 3 (IRCR3) ..........................................................................183
7.17.2 Reserved Register .....................................................................................................184
7.17.3 SIR Pulse Width Register (SIR_PW) .........................................................................184
7.17.4 Link Control Register (LCR) and Bank Select Register (BSR) ..................................184
7.17.5 Reserved Registers ...................................................................................................184
7.18 BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS 184
7.18.1 Infrared Receiver Demodulator Control Register (IRRXDC) .....................................184
7.18.2 Infrared Transmitter Modulator Control Register (IRTXMC) ......................................185
7.18.3 Consumer-IR Configuration Register (RCCFG), .......................................................187
7.18.4 Link Control/Bank Select Registers (LCR/BSR) ........................................................188
7.18.5 Infrared Interface Configuration Register 1 (IRCFG1) ...............................................188
7.18.6 Reserved Register .....................................................................................................189
7.18.7 Infrared Interface Configuration 3 Register (IRCFG3) ...............................................189
7.18.8 Infrared Interface Configuration Register 4 (IRCFG4) ...............................................189
7.19 UART2 WITH IR REGISTER BITMAPS ..................................................................................190
8.0 Enhanced Serial Port - UART1 (Logical Device 6)
8.1 REGISTER BANK OVERVIEW ...............................................................................................195
8.2 DETAILED DESCRIPTION ......................................................................................................195
8.2.1 16450 or 16550 UART Mode .....................................................................................196
8.2.2 Extended UART Mode ...............................................................................................196
8.3 FIFO TIME-OUTS ....................................................................................................................196
8.4 AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE ..........................................197
8.4.1 Transmission Deferral ...............................................................................................197
8.5 BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS .................................................197
8.5.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD) .................................197
8.5.2 Interrupt Enable Register (IER) .................................................................................198
8.5.3 Event Identification Register (EIR) ............................................................................199
8.5.4 FIFO Control Register (FCR) .....................................................................................200
8.5.5 Line Control Register (LCR) and Bank Selection Register (BSR) .............................201
8.5.6 Bank Selection Register (BSR) .................................................................................202
8.5.7 Modem/Mode Control Register (MCR) ......................................................................203
8.5.8 Line Status Register (LSR) ........................................................................................204
8.5.9 Modem Status Register (MSR) ..................................................................................205
8.5.10 Scratchpad Register (SPR) .......................................................................................205
8.5.11 Auxiliary Status and Control Register (ASCR) ..........................................................205
8.6 BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS .........................................206
8.6.1 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), ..............................206
8.6.2 Line Control Register (LCR) and Bank Select Register (BSR) ..................................207
8.7 BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................207
8.7.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ...........................207
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8.7.2 Extended Control Register 1 (EXCR1) ......................................................................208
8.7.3 Line Control Register (LCR) and Bank Select Register (BSR) ..................................209
8.7.4 Extended Control and Status Register 2 (EXCR2) ....................................................209
8.7.5 Reserved Register .....................................................................................................209
8.7.6 TX_FIFO Current Level Register (TXFLV) ................................................................209
8.7.7 RX_FIFO Current Level Register (RXFLV) ...............................................................210
8.8 BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS ..........................................210
8.8.1 Module Revision ID Register (MRID) ........................................................................210
8.8.2 Shadow of Line Control Register (SH_LCR) .............................................................210
8.8.3 Shadow of FIFO Control Register (SH_FCR) ............................................................211
8.8.4 Line Control Register (LCR) and Bank Select Register (BSR) ..................................211
8.9 UART1 REGISTER BITMAPS .................................................................................................211
9.0 General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip
Select Output Signals
9.1 GPIO PORT ACTIVATION ......................................................................................................215
9.2 GPIO CONTROL REGISTERS ...............................................................................................215
9.2.1 Special GPIO Signal Features ...................................................................................215
9.2.2 Reading and Writing to GPIO Pins ............................................................................215
9.2.3 Multiplexed GPIO Signals ..........................................................................................215
9.2.4 Multiplexed GPIO Signal Selection ............................................................................215
9.3 PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS .........................................................216
10.0 Power Management (Logical Device 8)
10.1 POWER MANAGEMENT OPTIONS .......................................................................................218
10.1.1 Configuration Options ................................................................................................218
10.1.2 WATCHDOG Feature ................................................................................................218
10.2 POWER MANAGEMENT REGISTERS ...................................................................................218
10.2.1 Power Management Index Register ..........................................................................218
10.2.2 Power Management Data Register ...........................................................................219
10.2.3 Function Enable Register 1 (FER1) ...........................................................................219
10.2.4 Function Enable Register 2 (FER2) ...........................................................................219
10.2.5 Power Management Control Register (PMC1) ..........................................................220
10.2.6 Power Management Control 2 Register (PMC2) .......................................................221
10.2.7 Power Management Control 3 Register (PMC3) .......................................................221
10.2.8 WATCHDOG Time-Out Register (WDTO) ................................................................222
10.2.9 WATCHDOG Configuration Register (WDCF) ..........................................................222
10.2.10 WATCHDOG Status Register (WDST) ......................................................................223
10.2.11 PM1 Event Base Address Register (Bits 7-0) ............................................................223
10.2.12 PM1 Event Base Address Register (Bits 15-8) ..........................................................223
10.2.13 PM Timer Base Address (Bits 7-0) ............................................................................223
10.2.14 PM Timer Base Address Register (Bits 15-8) ............................................................224
10.2.15 PM1 Control Base Address Register (Bits 7-0) .........................................................224
10.2.16 PM1 Control Base Address Register (Bits 15-8) .......................................................224
10.2.17 General Purpose Status Base Address Register (Bits 7-0) .......................................224
10.2.18 General Purpose Status Base Address Register (Bits 15-8) .....................................224
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10.2.19 ACPI Support Register ..............................................................................................225
10.3 POWER MANAGEMENT REGISTER BITMAPS ....................................................................226
11.0 X-Bus Data Buffer
12.0 The Internal Clock
12.1 THE CLOCK SOURCE ............................................................................................................230
12.2 THE INTERNAL ON-CHIP CLOCK MULTIPLIER ...................................................................230
12.3 SPECIFICATIONS ...................................................................................................................230
12.4 POWER-ON PROCEDURE WHEN CFG0 = 0 ........................................................................230
13.0 Interrupt and DMA Mapping
13.1 IRQ MAPPING .........................................................................................................................231
13.2 DMA MAPPING .......................................................................................................................231
14.0 Device Specifications
14.1 GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................232
14.1.1 Recommended Operating Conditions .......................................................................232
14.1.2 Absolute Maximum Ratings .......................................................................................232
14.1.3 Capacitance ...............................................................................................................232
14.1.4 Power Consumption Under Recommended Operating Conditions ...........................233
14.2 DC CHARACTERISTICS OF PINS, BY GROUP ....................................................................233
14.2.1 Group 1 ......................................................................................................................233
14.2.2 Group 2 ......................................................................................................................234
14.2.3 Group 3 ......................................................................................................................234
14.2.4 Group 4 ......................................................................................................................235
14.2.5 Group 5 ......................................................................................................................235
14.2.6 Group 6 ......................................................................................................................235
14.2.7 Group 7 ......................................................................................................................236
14.2.8 Group 8 ......................................................................................................................236
14.2.9 Group 9 ......................................................................................................................237
14.2.10 Group 10 ....................................................................................................................237
14.2.11 Group 11 ....................................................................................................................238
14.2.12 Group 12 ....................................................................................................................238
14.2.13 Group 13 ....................................................................................................................239
14.2.14 Group 14 ....................................................................................................................239
14.2.15 Group 15 ....................................................................................................................240
14.2.16 Group 16 ....................................................................................................................240
14.2.17 Group 17 ....................................................................................................................240
14.2.18 Group 18 ....................................................................................................................240
14.2.19 Group 19 ....................................................................................................................241
14.2.20 Group 20 ....................................................................................................................241
14.2.21 Group 21 ....................................................................................................................241
14.2.22 Group 22 ....................................................................................................................241
14.2.23 Group 23 ....................................................................................................................241
14.2.24 Group 24 ....................................................................................................................242
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14.2.25 Group 25 ....................................................................................................................242
14.2.26 Group 26 ....................................................................................................................243
14.2.27 Group 27 ....................................................................................................................243
14.2.28 Group 28 ....................................................................................................................243
14.3 AC ELECTRICAL CHARACTERISTICS ..................................................................................244
14.3.1 AC Test Conditions TA = 0 °C to 70 °C, VDD = 5.0 V ±10% ......................................244
14.3.2 Clock Timing ..............................................................................................................244
14.3.3 Microprocessor Interface Timing ...............................................................................245
14.3.4 Baud Output Timing ...................................................................................................247
14.3.5 Transmitter Timing .....................................................................................................248
14.3.6 Receiver Timing .........................................................................................................249
14.3.7 UART, Sharp-IR, SIR and Consumer Remote Control Timing ..................................251
14.3.8 IRSLn Write Timing ...................................................................................................252
14.3.9 Modem Control Timing ..............................................................................................252
14.3.10 DMA Timing ...............................................................................................................253
14.3.11 Reset Timing .............................................................................................................256
14.3.12 Write Data Timing ......................................................................................................257
14.3.13 Drive Control Timing ..................................................................................................258
14.3.14 Read Data Timing ......................................................................................................258
14.3.15 Parallel Port Timing ...................................................................................................259
14.3.16 Enhanced Parallel Port 1.7 Timing ............................................................................260
14.3.17 Enhanced Parallel Port 1.9 Timing ............................................................................261
14.3.18 Extended Capabilities Port (ECP) Timing ..................................................................262
14.3.19 GPIO Write Timing ....................................................................................................263
14.3.20 RTC Timing ...............................................................................................................263
14.3.21 APC Timing ...............................................................................................................264
14.3.22 Chip Select Timing ....................................................................................................267
14.3.23 LED Timing ................................................................................................................267
Glossary .....................................................................................................................................................268
Signal/Pin Connection and Description
16
1.0 Signal/Pin Connection and Description
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1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM
80
75
70
65
60
55
50
1 5 10 15 20 25 30
859095100
4035
PC87317VUL
105110115120
45
41
81
121
125
130
135
140
145
150
155
160
A1
A2
V
SS
V
DD
A3A4A5A6A7A8A9
A10
A11
A12
A13
IOCHRDY
RD
ZWS
WGATE
TRK0WPRDATA
HDSEL
A0
MTR1
DSKCHG
DIR
STEP
WDATA
MSEN1
DENSEL
INDEX
MTR0
DR1
DR0
XDRD/ID3
MSEN0
V
DD
P21
P20
P17
P16/GPIO25
P12/
CS0
GPIO10
GPIO11
GPIO12
GPIO13
CS2/XD1
STB/WRITE
V
SS
V
DD
SLIN/ASTRB
SLCT
PE
BUSY/
WAIT
ACK
V
DD
INIT
D7
CS1/XD0/CSOUT-NSC-Test
X1
V
SS
D0D1D2D3D4D5D6
MR
X2C
V
CCH
A15
A14
V
BAT
X1C
VSSVDDKBCLK
KBDAT
MDAT
MCLK
IRQ15
IRQ14
IRQ12
IRQ11
DACK3
DRATE0
DTR1/BADDR0/BOUT1
RI1
DCD1
DSR1
SIN1
RTS1/BADDR1
SOUT1/CFG0
CTS1
IRQ10
AEN
WR
TC
IRQ9
IRQ8
IRQ7
IRQ6
IRQ1
IRQ3
IRQ4
IRQ5
GPIO14
GPIO15/PME2
GPIO16/PME1
GPIO17/WDO
GPIO20/IRSL1/ID1
GPIO21/IRSL0/IRSL2/ID2
GPIO22/POR
V
SS
V
DD
DRQ1
DRQ0
DACK2
DACK1
DACK0
DRQ2
DRQ3
ERR
V
SS
V
SS
V
SS
DTR2/CFG1/BOUT2
GPIO33/RI2
GPIO31/DCD2
GPIO32/DSR2
GPIO35/SIN2
GPIO34/RTS2
GPIO36/SOUT2
GPIO30/CTS2
AFD/DSTRB
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
V
SS
IRTX
GPIO24/IRRX1
GPIO37/IRRX2/IRSL0/ID0
IRSL1/ID1/XD7
IRSL2/SELCS/GPIO21/XD6
GPIO27/XD5
GPIO26/XD4
GPIO25/XD3
GPIO24/XD2
LED/
CS0
ONCTL
SWITCH
RING/XDCS
GPIO23/
RING
PlasticQuad Flatpack (PQFP), EIAJ
Order Number PC87317VUL/PC97317VUL
NS Package Number VUL160A
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
17
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1.2 SIGNAL/PIN DESCRIPTIONS
TABLE 1-1 "Signal/Pin Description Table" lists the signals
of the PC87317VUL in alphabetical order and shows the
pin(s) associated with each. TABLE 1-2 "Multiplexed X-Bus
Data Buffer (XDB) Pins" on page 25 lists the X-Bus Data
Buffer (XDB) signals that are multiplexed and TABLE 1-6
"Pins with a Strap Function During Reset" on page 26 lists
the pins that have strap functions during reset.
The Module column indicates the functional module that is
associated with these pins. In this column, the System label
indicates internal functions that are common to more than
one module. The I/O and Group # column describes whether the pin is an input, output, or bidirectional pin (marked as
Input, Output or I/O, respectively).
TABLE 1-1. Signal/Pin Description Table
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
A15-0 29-26,
23-12
ISA-Bus Input
Group 1
ISA-Bus Address – A15-0 are used for address decoding on any
access except DMA accesses, on condition that the AEN signal is
low.
See Section 2.2.2 on page 28.
ACK 113 Parallel Port Input
Group 3
Acknowledge – This input signal is pulsed low by the printer to
indicate that it has received data from the parallel port. This pin is
internally connected to a weak pull-up.
AFD 119 Parallel Por t I/O
Group 13
Automatic Feed – When this signal is low the printer should
automatically feed a line after printing each line. This pin is in TRISTATE after a 0 is loaded into the corresponding control register bit.
An external 4.7 KΩ pull-up resistor should be attached to this pin.
For Input mode see bit 5 in Section 6.5.16 on page 152.
This signal is multiplexed with
DSTRB. See TABLE 6-12 on page 160
for more information.
AEN 30 ISA-Bus Input
Group 1
DMA Address Enable – This input signal disables function selection
via A15-0 when it is high. Access during DMA transfer is not affected
by this signal.
ASTRB 118 Parallel Port Output
Group 13
Address Strobe (EPP) – This signal is used in EPP mode as an
address strobe. It is active low.
This signal is multiplexed with
SLIN.See TABLE 6-12 on page 160 for
more information.
BADDR1,0 136, 134 Configuration Input
Group 5
Base Address Strap Pins 0 and 1 – These pins determine the base
addresses of the Index and Data registers, the value of the Plug and
Play ISA Serial Identifier and the configuration state immediately after
reset. These pins are pulled down by internal 30 KΩ resistors.
External 10 KΩ pull-up resistors to V
DD
should be employed.
BADDR1 is multiplexed with
RTS1.
BADDR0 is multiplexed with
DTR1 and BOUT1.
See TABLE 2-2 on page 28 and Section 2.1 on page 27.
BOUT2,1 148, 138 UART1,
UART 2
Output
Group 17
Baud Output – This multi-function pin provides the associated serial
channel Baud Rate generator output signal if test mode is selected,
i.e., bit 7 of the EXCR1 register is set. See “Bit 7 - Baud Generator
Test (BTEST)” on page 180.
After Master Reset this pin provides the SOUT function.
BOUT2 is multiplexed with DTR2 and CFG1.
BOUT1 is multiplexed with DTR1 and BADDR0.
BUSY 111 Parallel Port Input
Group 2
Busy – This pin is set to high by the printer when it cannot accept
another character. It is internally connected to a weak pull-down
resistor.
This signal is multiplexed with
WAIT. See TABLE 6-12 on page 160 for
more information.
Signal/Pin Connection and Description
18
SIGNAL/PIN DESCRIPTIONS
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CFG1-0 144, 138 Configuration Input
Group 5
Configuration Strap Pins 1-0 – These pins determine the default
configuration upon power up. These pins are pulled down by internal
30 KΩ resistors. Use external 10 KΩ pull-up resistors to V
DD
.
CFG1 is multiplexed with DTR2 and BOUT2. CFG0 is multiplexed with
SOUT1. See Table 2-2 on page 28.
CS0
68
106
General
Purpose
Output
Group 21
Group 12
Programmable Chip Select –
CS0, CS1 and CS2 are programmable
chip select and/or latch enable and/or output enable signals that have
many uses, for example, as game ports or for I/O port expansion.
The decoded address and the assertion conditions are configured via
the chip configuration registers. See Section 2.3 on page 29.
CS0 is multiplexed with LED on pin 68 and with P12 on pin 106. On
pin 68 is an open-drain output that is in TRI-STATE unless V
DD
is
applied.
CS1 is multiplexed with CSOUT-NSC-Test/XD0.
CS2 is multiplexed with XD1.
CS2,1 72, 71 General
Purpose
I/O
Group 9
CSOUTNSC-Test
71 NSC-use Output
Group 21
Chip Select Read Output, NSC-Test – National Semiconductor test
output. This is an open-drain output signal.
This signal is multiplexed with
CS1 and XD0.
CTS2,1 141, 131 UART1,
UART 2
Input
Group 1
UART1 and UART2 Clear to Send – When low, these signals indicate
that the modem or other data transfer device is ready to exchange data.
CTS2 is multiplexed with GPIO30.
D7-0 10-3 ISA-Bus I/O
Group 8
ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is
the LSB and D7 is the MSB. These signals have 24 mA (sink)
buffered outputs.
DACK3-0 59-56 ISA-Bus Input
Group 1
DMA Acknowledge 0,1,2 and 3 – These active low input signals
acknowledge a request for DMA services and enable the
IOWR and
IORD input signals during a DMA transfer. These DMA signals can be
mapped to the following logical devices: FDC, UART1, UART2 or
parallel port.
DCD2,1 142, 132 UART1,
UART 2
Input
Group 1
UART1 and UART2 Data Carrier Detected – When low, this signal
indicates that the modem or other data transfer device has detected
the data carrier.
DCD2 is multiplexed with GPIO31
DENSEL 94 FDC Output
Group 16
Density Select – Indicates that a high FDC density data rate (500
Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is
selected.
DENSELs polarity is controlled by bit 5 of the SuperI/O FDC
Configuration register as described in Section 2.6.1 on page 40.
DIR 90 FDC Output
Group 16
Direction – This output signal determines the direction of the Floppy
Disk Drive (FDD) head movement (active = step in, inactive = step
out) during a seek operation. During reads or writes,
DIR is inactive.
DR1,0 88, 87 FDC Output
Group 16
Drive Select 0 and 1 – These active low output signals are the
decoded drive select output signals.
DR0 and DR1 are controlled by
Digital Output Register (DOR) bits 0 and 1. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is 1, as described in Section 2.6.1.
See
MTR0,1 for more information.
DRATE0 84 FDC Output
Group 20
Data Rate 0 – This output signal reflects the value of bit 0 of the
Configuration Control Register (CCR) or the Data Rate Select Register
(DSR), whichever was written to last. Output from the pin is totem-pole
buffered (6 mA sink, 6 mA source).
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
19
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DRQ3-0 55-52 ISA-Bus Output
Group 18
DMA Request 0, 1, 2 and 3 – These active high output signals inform
the DMA controller that a data transfer is needed. These DMA signals
can be mapped to the following logical devices: Floppy Disk Controller
(FDC), UART1, UART2 or parallel port.
DSKCHG 99 FDC Input
Group 1
Disk Change – This input signal indicates whether or not the drive
door has been opened. The state of this pin is available from the
Digital Input Register (DIR). This pin can also be configured as the
RGATE data separator diagnostic input signal via the MODE
command. See the MODE command in Section 5.7.7.
DSR2,1 143, 133 UART1,
UART 2
Input
Group 1
Data Set Ready – When low, this signal indicates that the data
transfer device, e.g., modem, is ready to establish a communications
link.
DSR2 is multiplexed with GPIO32.
DSTRB 119 Parallel Port Output
Group 13
Data Strobe – This signal is used in EPP mode as a data strobe. It
is active low.
DSTRB is multiplexed with AFD. See TABLE 6-12 for more
information.
DTR2,1 144, 134 UART1,
UART 2
Output
Group 17
Data Terminal Ready – When low, this output signal indicates to the
modem or other data transfer device that the UART1 or UART2 is
ready to establish a communications link.
A Master Reset (MR) deactivates this signal high, and loopback
operation holds this signal inactive.
DTR2 is multiplexed with CFG1 and BOUT2.
DTR1 is multiplexed with BADDR0 and BOUT1.
ERR 116 Parallel Port Input
Group 3
Error – This input signal is set active low by the printer when it has
detected an error. This pin is internally connected to a weak pull-up.
GPIO17-15
GPIO14
GPIO13,12
GPIO11
GPIO10
156-154
153
152,151
150
149
General
Purpose
I/O
Group 10
Group 25
Group 10
Group 24
Group 10
General Purpose I/O Signals 17-10 – General purpose I/O signals of
I/O Port 1.
GPIO17 is multiplexed with
WDO.
GPIO16 is multiplexed with PME1.
GPIO15 is multiplexed with PME2.
GPIO27,26
GPIO25
GPIO24
GPIO23,22
GPIO21
GPIO20
76,75,
74 or 107,
73 or 80,
160-159,
158 or 77
157.
General
Purpose
I/O
Group 10
Group 25
Group 10
Group 10
Group 10
Group 10
General Purpose I/O Signals 27-20 – General purpose I/O por t 2
signals.
GPIO27-26 are multiplexed with XD5-4, respectively.
GPIO25 is multiplexed with XD3 on pin 74 and with P16 on pin107.
GPIO24 is multiplexed with XD2 on pin 73 and with IRRX1 on pin 80.
GPIO23 is multiplexed with
RING.
GPIO22 is multiplexed with
POR.
GPIO21 is multiplexed on pin 158 with IRSL2, IRSL0 and ID2 and on pin
77 with IRSL2, SELCS and XD6. See Bits 4,3 - GPIO21, IRSL2/ID2 or
IRSL0 Pin Select in Section 2.4.4.
GPIO20 is multiplexed with IRSL1 and ID1.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Signal/Pin Connection and Description
20
SIGNAL/PIN DESCRIPTIONS
www.national.com
GPIO37-30 79,
148-145,
143-141
General
Purpose
I/O
Group 10
General Purpose I/O Signals 37-30 – General purpose I/O por t 3
signals.
GPIO37 is multiplexed with IRRX2, IRSL0 and ID0.
GPIO36 is multiplexed with SOUT2.
GPIO35 is multiplexed with SIN2.
GPIO34 is multiplexed with
RTS2.
GPIO33 is multiplexed with
RI2.
GPIO32 is multiplexed with
DSR2.
GPIO31 is multiplexed with
DCD2.
GPIO30 is multiplexed with
CTS2.
HDSEL 92 FDC Output
Group 16
Head Select – This output signal determines which side of the FDD
is accessed. Active low selects side 1, inactive selects side 0.
ID3-0 70, 158,
78 or 157,
79
UART2 Input
Group 1
Identification – These ID signals identify the infrared transceiver for
Plug and Play support. These pins are read after reset.
ID3 is multiplexed with
XDRD.
ID2 is multiplexed with GPIO21, IRSL2 and IRSL0. ID1 is multiplexed
on pin 78 with IRS L1 and XD7 or pin 78, or on pin 157 with GPIO20
and IRSL1.
ID0 is multiplexed with GPIO37,IRRX2 and IRSL0.
See TABLE 1-2 for more information.
INDEX 97 FDC Input
Group 1
Index – This input signal indicates the beginning of an FDD track.
INIT 117 Parallel Port I/O
Group 13
Initialize – When this signal is active low, it causes the printer to be
initialized. This signal is in TRI-STATE after a 1 is loaded into the
corresponding control register bit.
For Input mode see bit 5 in Section 6.5.16.
An external 4.7 KΩ pull-up resistor should be employed.
IOCHRDY 32 ISA-Bus Output
Group 22
I/O Channel Ready – This is the I/O channel ready open drain output
signal. When IOCHRDY is driven low, the EPP extends the host cycle.
IRQ1
IRQ5-3
IRQ12-6
IRQ15,14
36
39-37
47-41
49,48
ISA-Bus I/O
Group 15
Interrupt Requests 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14 and 15 – IRQ
polarity and push-pull or open-drain output selection is software
configurable by the logical device mapped to the IRQ line.
Keyboard Controller (KBC) or Mouse interrupts can be configured by
the Interrupt Request Type Select 0 register (index 71h) as either
edge or level.
The internal SCI
1
signal may be routed to these pins.
IRRX2,1 79, 80 UART2 Input
Group 27
Infrared Reception 1 and 2 – Infrared serial input data. IRRX1
and/or IRRX2 may be routed to POR or ONCTL. The pins are
powered by V
CCH
.
IRRX1 is multiplexed with GPIO24.
IRRX2 is multiplexed with GPIO37,IRSL0 and ID0.
IRSL0
IRSL1
IRSL2
79 or 158
78 or 157
77 or 158
UART2 Output Infrared Control Signals 0, 1 and 2 – These signals control the
Infrared analog front end. The pins on which these signals are driven
is determined by the SuperI/O Configuration 2 register (index 22h).
See TABLE 1-2 for more information.
IRSL0 is multiplexed on pin 79 with GPIO37, IRRX2 and ID0, or on
pin 158 with GPIO21, IRSL2 and ID2.
IRSL1 is multiplexed on pin 78 with XD7 and ID1, or on pin 157 with
GPIO20 and ID1.
IRSL2 is multiplexed on pin 77 with XD6, SELCS and GPIO21, or on
pin 158 with GPIO21, IRSL0 and ID2.
Pins:
77, 78,79
Group 17
Pins:
157, 158
Group 10
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
21
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IRTX 81 UART2 Output
Group 19
Infrared Transmit – Infrared serial output data.
KBCLK 102 KBC I/O
Group 11
Keyboard Clock – This I/O pin transfers the keyboard clock between
the SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to the internal TO signal of the KBC.
KBDAT 103 KBC I/O
Group 11
Keyboard Data – This I/O pin transfers the keyboard data between
the SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s P10.
LED 68 APC OUTPUT
Group 26
LED Control - Drives an externally connected LED, according to the
user selection (on, off or a 1 Hz blink). This open-drain output is
powered by V
CCH
, it is multiplexed with CSO and can sink 16 mA.
MCLK 104 KBC I/O
Group 11
Mouse Clock – This I/O pin transfers the mouse clock between the
SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s T1.
MDAT 105 KBC I/O
Group 11
Mouse Data – This I/O pin transfers the mouse data between the
SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s P11.
MR 51 ISA-Bus Input
Group 1
Master Reset – An active high MR input signal resets the controller
to the idle state, and resets all disk interface output signals to their
inactive states. MR also clears the DOR, DSR and CCR registers,
and resets the MODE command, CONFIGURE command, and LOCK
command parameters to their default values. MR does not affect the
SPECIFY command parameters. MR sets the configuration registers
to their selected default values.
MSEN1,0 83, 82 FDC Input
Group 4
Media Sense – These input pins are used for media sensing when bit
6 of the SuperI/O FDC Configuration register (at index F0h) is 1. See
TABLE 1-2 for more information.
Each pin has a 40 KΩ internal pull-up resistor.
MTR1,0 86, 85 FDC Output
Group 16
Motor Select 1,0 – These motor enable lines for drives 0 and 1 are
controlled by bits D7-4 of the Digital Output Register (DOR). They are
output signals that are active when they are low. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is set See TABLE 1-2 for more information. See
DR1,0.
ONCTL 67 APC Output
Group 23
On/Off Control for the RTC’s Advanced Power Control (APC) –
This signal indicates to the main power supply to turn on power.
ONCTL is an open-drain output signal that is powered by V
CCH
.
P17,16
P12
108, 107
106
KBC I/O
Group 12
I/O Port – KBC quasi-bidirectional port for general purpose input and
output.
P12 may be routed internally (via APC) to
POR and/or SCI1.
P12 is multiplexed with
CS0.
P16 is multiplexed with GPIO25.
P21,20 110, 109 KBC I/O
Group 12
I/O Port – KBC open-drain signals for general purpose input and
output. These signals are controlled by KBC firmware.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Signal/Pin Connection and Description
22
SIGNAL/PIN DESCRIPTIONS
www.national.com
PD7-0 129-122 Parallel Por t I/O
Group 14
Parallel Port Data – These bidirectional signals transfer data to and
from the peripheral data bus and the appropriate parallel port data
register. These signals have a high current dr ive capability. See
Section 14.1 on page 232.
PE 115 Parallel Port Input
Group 2
Group 3
Paper End – This input signal is set high by the printer when it is out
of paper. This pin has an internal weak pull-up or pull-down resistor.
PME2,1 154,155 APC Input
Group 28
Power Management Event 1 and 2 - These signals indicate that a
power Management Event has occurred. They may be routed to
POR,
SCI
1
or ONCTL. Event characteristics (low/high, rise/fall) are software
configurable. The pins are powered by V
CCH
.
PME1 is multiplexed with GPIO16.
PME2 is multiplexed with GPIO15.
POR 159 APC Output
Group 21
Power Off Request – This signal is activated by various events,
including the APC Switch Off event (regardless of the fail-safe delay).
Selection of edge or level for
POR is via the APCR1 register of the
APC. Selection of an output buffer is via GPIO22 output buffer control
bits (in the Port 2 Output Type and Port 2 Pull-up Control registers
described in TABLE 9-2). See Section 4.3.
This signal is multiplexed with GPIO22
RD 33 ISA-Bus Input
Group 1
I/O Read – An active low RD input signal indicates that the
microprocessor has read data.
RDATA 95 FDC Input
Group 1
Read Data – This input signal holds raw serial data read from the
Floppy Disk Drive (FDD).
RI2,1 145, 135 UART1, APC Input
Group 7
Ring Indicators (Modem) – When low, this signal indicates that a
telephone ring signal has been received by the modem.
When enabled, a high to low transition on
RI1 or RI2 activates the
ONCTL pin. The RI1 and RI2 pins have schmitt-trigger input buffers.
RI2 is multiplexed with GPIO33.
RING 69 or 160 APC Input
Group 7
Ring Indicator (APC) – Detection of an active low RING pulse or
pulse train activates the
ONCTL signal. The APC’s APCR2 register
determines which pin the
RING signal uses. The pins have a schmitt-
trigger input buffer.
RING is multiplexed on pin 69 with XDCS and on pin 160 with
GPIO23.
RTS2,1 146, 136 UART1,
UART 2
Output
Group 17
Request to Send – When low, these output signals indicate to the
modem or other data transfer device that the corresponding UART1
or UART2 is ready to exchange data.
A Master Reset (MR) sets
RTS to inactive high. Loopback operation
holds it inactive.
RTS2 is multiplexed with GPIO34. RTS1 is multiplexed with BADDR1.
SELCS 77 Configuration Input
Group 4
Select CSOUT – During reset, this signal is sampled into bit 1 of the
SuperI/O Configuration 1 register (index 21h).
A 40 KΩ internal pull-up resistor (or a 10 KΩ external pull-down
resistor for National Semiconductor testing) controls this pin during
reset. Do not pull this signal low during reset.
This signal is multiplexed with GPIO21, IRSL2 and XD6.
SIN2,1 147, 137 UART1,
UART 2
Input
Group 1
Serial Input – This input signal receives composite serial data from
the communications link (peripheral device, modem or other data
transfer device.)
SIN2 is multiplexed with GPIO35.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
23
www.national.com
SLCT 114 Parallel Por t Input
Group 2
Select – This input signal is set active high by the printer when the
printer is selected. This pin is internally connected to a nominal 25 KΩ
pull-down resistor.
SLIN 118 Parallel Port I/O
Group 13
Select Input – When this signal is active low it selects the printer.
This signal is in TRI-STATE after a 0 is loaded into the corresponding
control register bit. Use an external 4.7 KΩ pull-up resistor.
For Input mode see bit 5, described in Section 6.5.16.
This signal is multiplexed with
ASTRB.
SOUT2,1 148, 138 UART1,
UART 2
Output
Group 17
Serial Output – This output signal sends composite serial data to the
communications link (peripheral device, modem or other data transfer
device).
The SOUT2,1 signals are set active high after a Master Reset (MR).
SOUT2 is multiplexed with GPIO36.
SOUT1 is multiplexed with CFG0.
STB 112 Parallel Port I/O
Group 13
Data Strobe – This output signal indicates to the printer that valid
data is available at the printer port.
This signal is in TRI-STATE after a 0 is loaded into the corresponding
control register bit.
An external 4.7 KΩ pull-up resistor should be employed.
For Input mode see bit 5, described in Section 6.5.16.
This signal is multiplexed with
WRITE.
STEP 91 FDC Output
Group 16
Step – This output signal issues pulses to the disk drive at a software
programmable rate to move the head during a seek operation.
SWITCH 66 APC Input
Group 7
Switch On/Off – A physical momentary switch attached to this pin
indicates a user request (to the APC) to switch the power on or off.
(See “The SWITCH Input Signal” on page 67).
The pin has an internal pull-up of 1 MΩ (nominal), a schmitt-trigger
input buffer and debounce protection of at least 16 msec.
TC 35 ISA-Bus Input
Group 1
DMA Terminal Count – The DMA controller issues TC to indicate the
termination of a DMA transfer. TC is accepted only when a
DACK
signal is active.
TC is active high in PC-AT mode, and active low in PS/2 mode.
TRK0 96 FDC Input
Group 1
Track 0 – This input signal indicates to the controller that the head of
the selected floppy disk drive is at track 0.
V
BAT
64 RTC and
APC
Input Battery Power Supply – Power signal from the battery to the Real-
Time Clock (RTC) or for Advanced Power Control (APC) when V
CCH
is less than V
BAT
(by at least 0.5V). V
BAT
includes a UL protection
resistor.
V
CCH
65 RTC and
APC
Input VCC Help Power Supply – This signal provides power to the RTC or
APC when V
CCH
is higher than V
BAT
(by at least 0.5V).
V
DD
1, 24, 61,
100, 121,
140
Power
Supply
Input Main 5 V Power Supply – This signal is the 5 V supply voltage for
the digital circuitry.
V
SS
2, 11, 25,
40, 60,
101, 120,
130, 139
Power
Supply
Output Ground – This signal provides the ground for the digital circuitry.
WAIT 111 Parallel Port Input
Group 2
Wait – In EPP mode, the parallel port device uses this signal to
extend its access cycle.
WAIT is active low. This signal is multiplexed
with BUSY. See TABLE 6-12 on page 160 for more information.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Signal/Pin Connection and Description
24
SIGNAL/PIN DESCRIPTIONS
www.national.com
1. SCI is an internal signal used to send ACPI-relevant notifications to the host operating system.
WDATA 89 FDC Output
Group 16
Write Data (FDC) – This output signal holds the write
precompensated serial data that is written to the selected floppy disk
drive. Precompensation is software selectable.
WDO 156 Power Man-
agement
Output
Group 10
WATCHDOG Out – This output pin becomes low when a
WATCHDOG time-out occurs. See Section 10.1.2 on page 218.This
pin is configured by bit 6 of the SuperI/O Configuration Register 2.
This signal is multiplexed with GPIO17.
WGATE 93 FDC Output
Group 16
Write Gate (FDC) – This output signal enables the write circuitry of
the selected disk drive.
WGATE is designed to prevent glitches during
power up and power down. This prevents writing to the disk when
power is cycled.
WP 98 FDC Input
Group 1
Write Protected – This input signal indicates that the disk in the
selected drive is write protected.
WR 34 ISA-Bus Input
Group 1
I/O Write – WR is an active low input signal that indicates a write
operation from the microprocessor to the controller.
WRITE 112 Parallel Por t Output
Group 23
Write Strobe – In EPP mode, this active low signal is a write strobe.
This signal is multiplexed with
STB. See TABLE 6-12 for more
information.
X1 50 Clock Input
Group 6
Clock In – A TTL or CMOS compatible 14.31818MHz, 24 MHz or 48
MHz clock. When this pin is fed by the 14.31818MHz clock, the chip
must be configured to work with the on-chip clock multiplier.See
Chapter 12 on page 230.
X1C 62 RTC Input Crystal 1 Slow – Input signal to the internal Real-Time Clock (RTC)
crystal oscillator amplifier. Clock source is set by CFG0 during reset.
X2C 63 RTC Output Crystal 2 Slow – Output signal from the internal Real-Time Clock
(RTC) crystal oscillator amplifier.
XD7,6,
XD1,0
78, 77
72, 71
X-Bus I/O
Group 9
X-Bus Data – These bidirectional signals hold the data in the X Data
Buffer (XDB).
XD7 is multiplexed with IRSL1 and ID1.
XD6 is multiplexed with IRSL2, SELCS and GPIO21.
XD5-2 are multiplexed with GPIO27-24, respectively.
XD1 is multiplexed with
CS2.
XD0 is multiplexed with
CS1/CSOUT-NSC-Test
See TABLE 1-2 on page 25.
XD5-2 76-73 X-Bus I/O
Group 10
XDCS 69 X-Bus Input
Group 7
X-Bus Data Buffer (XDB) Chip Select – This signal enables and
disables the bidirectional XD7-0 data buffer signals.
This signal is multiplexed with
RING.
XDRD 70 X-Bus Input
Group 1
X-Bus Data Buffer (XDB) Read Command – This signal controls the
direction of the bidirectional XD7-0 data buffer signals.
This signal is multiplexed with ID3.
ZWS 31 ISA-Bus Output
Group 22
Zero Wait State – When this open-drain output signal is activated
(driven low), it indicates that the access time can be shortened, i.e.,
zero wait states.
ZWS is never activated (driven low) on access to SuperI/O chip
configuration registers (including during the Isolation state) or on
access to the parallel port in SPP or EPP 1.9 mode.
ZWS is always activated (driven low) on access to the parallel port in
ECP mode.
Signal/Pin
Name
Pin
Number
Module
I/O and
Group #
Function
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
25
www.national.com
TABLE 1-3. UART2/GPIO Port 3 Pin Designation
TABLE 1-4. APC/Power Management or GPIO/Chip Select Pin Designation
1. Unselected (XDB or alternate function) input signals are internally blocked high.
TABLE 1-2. Multiplexed X-Bus Data Buffer (XDB) Pins
Pin
X-Bus Data Buffer (XDB)
1
Bit 4 of SuperI/O Configuration
Register 1 = 1
I/O
Alternate Function
a
Bit 4 of SuperI/O Configuration 1
Register = 0
I/O
69
XDCS Input RING Input
70
XDRD Input ID3
71 XD0 I/O
CS1/CSOUT-NSC-Test Output
72 XD1 I/O
CS2 Output
73 XD2 I/O GPIO24 I/O
73 XD3 I/O GPIO25 I/O
75 XD4 I/O GPIO26 I/O
76 XD5 I/O GPIO27 I/O
77 XD6/SELCS I/O GPIO21/IRSL2/SELCS I/O
78 XD7 I/O IRSL1/ID1 Output
Pin
UAR T 2
Bit 3 of SuperI/O Configuration
Register 1 = 1
I/O
General Purpose I/O port 3
Bit 3 of SuperI/O Configuration
Register 1 = 0
I/O
141
CTS2 Input GPIO30 I/O
142
DCD2 Input GPIO31 I/O
143
DSR2 Input GPIO32 I/O
146
RTS2 Output GPIO34 I/O
147 SIN2 Input GPIO35 I/O
148 SOUT2 Output GPIO36 I/O
Pin APC, Power Management I/O General Purpose I/O, Chip Select I/O
154 PME2 Input GPIO15 I/O
155 PME1 Input GPIO16 I/O
156
WDO Output GPIO17 I/O
159
POR Output GPIO22 I/O
160
RING Input GPIO23 I/O
68 LED Output
CS0 Output
Signal/Pin Connection and Description
26
SIGNAL/PIN DESCRIPTIONS
www.national.com
TABLE 1-5. Infrared/KBC or GPIO/Chip-Select Pin Designation
TABLE 1-6. Pins with a Strap Function During Reset
Pin Infrared, KBC, UART2 I/O General Purpose I/O, Chip Select I/O
157 IRSL1/ID1 I/O GPIO20 I/O
158 IRSL2/IRSL0/ID2 I/O GPIO21 I/O
80 IRRX1 Input GPIO24 I/O
107 P16 I/O GPIO25 I/O
145
RI2 Input GPIO33 I/O
79 IRRX2/IRSL0/ID0 I/O GPIO37 I/O
106 P12 I/O
CS0 Output
Strap Function Pin No. Symbols
BADDR1,0 134
DTR1/BADDR0/BOUT1
136
RTS1/BADDR1
CFG1,0 138 SOUT1/CFG0
144
DTR2/CFG1
SELCS 77 GPIO21/IRSL2/XD6/SELCS
Configuration
27
2.0 Configuration
www.national.com
2.0 Configuration
The PC87317VUL is partially configured by hardware, during reset. The configuration can also be changed by software, by changing the values of the configuration registers.
The configuration registers are accessed using an Index
register and a Data register. During reset, hardware strapping options define the addresses of the configuration registers. See Section 2.1.2 "The Index and Data Register
Pair".
After the Index and Data register pair have determined the
addresses of the configuration registers, the addresses of
the Index and Data registers can be changed within the ISA
I/O address space, and a 16-bit programmable register controls references to their addresses and to the addresses of
the other registers.
This chapter describes the hardware and software configuration processes. For each, it describes configuration of the
Index and Data register pair first. See Sections 2.1 "HARDWARE CONFIGURATION" and 2.2 "SOFTWARE CONFIGURATION" on page 28.
Section 2.3 "THE CONFIGURATION REGISTERS" on
page 29 presents an overview of the configuration registers
of the PC87317VUL and describes each in detail.
2.1 HARDWARE CONFIGURATION
The PC87317VUL supports two Plug and Play (PnP) configuration modes that determine the status of register addresses upon wake up from a hardware reset, Full Plug and
Play ISA mode and Plug and Play Motherboard mode.
2.1.1 Wake Up Options
During reset, strapping options on the BADDR0 and
BADDR1 pins determine one of the following modes.
●
Full Plug and Play ISA mode – System wakes up in
Wait for Key state.
Index and Data register addresses are as defined by Microsoft and Intel in the
“Plug and Play ISA Specification,
Version 1.0a, May 5, 1994.”
●
Plug and Play Motherboard mode – system wakes up
in Config state.
The BIOS configures the PC87317VUL. Index and Data
register addresses are different from the addresses of
the Plug and Play (PnP) Index and Data registers. Configuration registers can be accessed as if the serial isolation procedure had already been done, and the
PC87317VUL is selected.
The BIOS may switch the addresses of the Index and
Data registers to the PnP ISA addresses of the Index
and Data registers, by using software to modify the base
address bits, as shown in Section 2.4.4 "SuperI/O Configuration 2 Register (SIOC2)" on page 38.
2.1.2 The Index and Data Register Pair
During reset, a hardware strapping option on the BADDR0
and BADDR1 pins defines an address for the Index and
Data Register pair. This prevents contention between the
registers for I/O address space.
TABLE 2-1 "Base Addresses" shows the base addresses
for the Index and Data registers that hardware sets for each
combination of values of the Base Address strap pins
(BADDR0 and BADDR1). You can access and change the
content of the configuration registers at any time, as long as
the base addresses of the Index and Data registers are defined.
When BADDR1 is low (0), the Plug and Play (PnP) protocol
defines the addresses of the Index and Data register, and
the system wakes up from reset in the Wait for Key state.
When BADDR1 is high (1), the addresses of the Index and
Data register are according to TABLE 2-1 "Base Addresses", and the system wakes up from reset in the Config state.
This configures the PC87317VUL with default values, automatically, without software intervention. After reset, use
software as described in Section 2.2 "SOFTWARE CONFIGURATION" on page 28 to modify the selected base address of the Index and Data register pair, and the defaults
for configuration registers.
The Plug and Play soft reset has no effect on the logical devices, except for the effect of the Activate registers (index
30h) in each logical device.
The PC87317VUL can wake up with the FDC, the KBC and
the RTC either active (enabled) or inactive (disabled). The
other logical devices and the internal on-chip clock multiplier wake up inactive (disabled).
TABLE 2-1. Base Addresses
BADDR1 BADDR0
Address
Configuration Type
Index Register Data Register
0x
0279h
Write Only
Write: 0A79h
Read: RD_DATA Port
Full PnP ISA Mode
Wake up in Wait for Key state
1 0 015Ch Read/Write 015Dh Read/Write
PnP Motherboard Mode
Wake up in Config state
1 1 002Eh Read/Write 002Fh Read/Write
PnP Motherboard Mode
Wake up in Config state
Configuration
28
SOFTWARE CONFIGURATION
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2.1.3 The Strap Pins
TABLE 2-2. The Strap Pins
1. SELCS = 0 and CFG1 = 1 is an illegal strap option.
2.2 SOFTWARE CONFIGURATION
2.2.1 Accessing the Configuration Registers
Only two system I/O addresses are required to access any
of the configuration registers. The Index and Data register
pair is used to access registers for all read and write operations.
In a write operation, the target configuration register is identified, based on a value that is loaded into the Index register.
Then, the data to be written into the configuration register is
transferred via the Data register.
Similarly, for a read operation, first the source configuration
register is identified, based on a value that is loaded into the
Index register. Then, the data to be read is transferred via
the Data register.
Reading the Index register returns the last value loaded into
the Index register. Reading the Data register returns the
data in the configuration register pointed to by the Index
register.
If, during reset, the Base Address 1 (BADDR1) signal is low
(0), the Index and Data registers are not accessible immediately after reset. As a result, all configuration registers of
the PC87317VUL are also not accessible at this time. To
access these registers, you must apply the Plug and Play
(PnP) ISA protocol.
If during reset, the Base Address 1 (BADDR1) signal is high
(1), all configuration registers are accessible immediately
after reset.
It is up to the configuration software to guarantee no conflicts between the registers of the active (enabled) logical
devices, between IRQ signals and between DMA channels.
If conflicts of this type occur, the results are unpredictable.
To maintain compatibility with other SuperI/O‘s, the value of
reserved bits may not be altered. Use read-modify-write.
2.2.2 Address Decoding
In full Plug and Play mode, the addresses of the Index and
Data registers that access the configuration registers are
decoded using pins A11-0, according to the ISA Plug and
Play specification.
In Plug and Play Motherboard mode, the addresses of the
Index and Data registers that access the configuration registers are decoded using pins A15-1. Pin A0 distinguishes
between these two registers.
KBC and mouse register addresses are decoded using pins
A1,0 and A15-3. Pin A2 distinguishes between the device
registers.
RTC/APC and Power Management (PM) register addresses are decoded using pins A15-1.
FDC, UART, and GPIO register addresses are decoded using pins A15-3.
Parallel Port (PP) modes determine which pins are used for
register addresses. In SPP mode, 14 pins are used to decode Parallel Port (PP) base addresses. In ECP and EPP
modes, 13 address pins are used. TABLE 2-3 "Address
Pins Used for Parallel Port" shows which address pins are
used in each mode.
TABLE 2-3. Address Pins Used for Parallel Port
Pin Reset Configuration Affected
CFG0 0: FDC, KBC and RTC wake up inactiv e , cloc k source is 32.768 KHz
with on-chip clock multiplier disabled.
1: FDC, KBC and RTC wake up active, clock source is 48 MHz fed
via X1 pin.
Bit 0 of Activate registers (index
30h) of logical devices 0, 2 and 3
and bit 0 of PMC2 register of Power
Management (logical device 8).
CFG1
1
0: No X-Bus Data Buffer. (See XDB pins multiplexing in TABLE 1-2.)
1: X-Bus Data Buffer (XDB) enabled.
Bit 4 of SuperI/O Configuration 1
(SIOC1) register (index 21h).
BADDR1,0 00: Full PnP ISA, Wake in Wait For Key state. Index PnP ISA.
01: Full PnP ISA, Wake in Wait For Key state. Index PnP ISA.
10: PnP Motherboard, Wake in Config state. Index 015Ch.
11: PnP Motherboard, Wake in Config state. Index 002Eh.
Bits 1 and 0 of SuperI/O
Configuration 2 (SIOC2) register
(index 22h)
SELCS
a
0: CSOUT-NSC-test on pin 71.
1:
CS1 or XD0 on pin 71 (according to CFG1).
Bit 1 of SuperI/O Configuration 1
(SIOC1) register (index 21h).
PP Mode
Pins Used to
Decode Base
Address
Pins Used to
Distinguish Registers
SPP A15-2 A1,0
ECP A9-2 and A15-11 A1,0 and A10
EPP A15-3 A2-0
Configuration
THE CONFIGURATION REGISTERS
29
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TABLE 2-4. Parallel Port Address Range Allocation
1. The SuperI/O processor does not decode the Parallel Port outside this range.
2.3 THE CONFIGURATION REGISTERS
The configuration registers control the setup of the
PC87317VUL. Their major functions are to:
●
Identify the chip
●
Enable major functions (such as, the Keyboard Controller (KBC) for the keyboard and the mouse, the RealTime Clock (RTC), including Advanced Power Control
(APC), the Floppy Disc Controller (FDC), UARTs, parallel and general purpose ports, power management and
pin functionality)
●
Define the I/O addresses of these functions
●
Define the status of these functions upon reset
Section 2.3.2 "Configuration Register Summary" on page
33 summarizes information for each register of each function. In addition, the following non-standard, or card control,
registers are described in detail, in Section 2.4 "CARD
CONTROL REGISTERS" on page 37.
●
The Card Control Registers
— SID Register
— SRID Register (only in the PC97317).
— SuperI/O Configuration 1 Register (SIOC1)
— SuperI/O Configuration 2 Register (SIOC2)
— Programmable Chip Select Configuration Index
Register
— Programmable Chip Select Configuration Data Reg-
ister
●
KBC Configuration Register (Logical Device 0)
— SuperI/O KBC Configuration Register
●
FDC Configuration Registers (Logical Device 3)
— SuperI/O FDC Configuration Register
— Drive ID Register
●
Parallel Por t Configuration Register (Logical Device 4)
— SuperI/O Parallel Port Configuration Register
●
UART2 and Infrared Configuration Register (Logical
Device 5)
— SuperI/O UART2 Configuration Register
●
UART1 Configuration Register (Logical Device 6)
— SuperI/O UART1 Configuration Register
●
Programmable Chip Select Configuration Registers
—
CS0 Base Address MSB Register
—
CS0 Base Address LSB Register
—
CS0 Configuration Register
—
CS1 Base Address MSB Register
—
CS1 Base Address LSB Register
—
CS1 Configuration Register
—
CS2 Base Address MSB Register
—
CS2 Base Address LSB Register
—
CS2 Configuration Register
Parallel Port Mode
SuperI/O Parallel Port
Configuration Register Bits
7 6 5 4
Decoded Range
1
SPP 0 0 x x Three registers, from base to base + 02h
EPP (Non ECP Mode 4) 0 1 x x Eight registers, from base to base + 07h
ECP, No Mode 4,
No Inter nal Configuration
1 0 0 0
Six registers, from base to base + 02h and
from base + 400h to base + 402h
ECP with Mode 4,
No Inter nal Configuration
1 1 1 0
11 registers, from base to base + 07h and
from base + 400h to base + 402h
ECP with Mode 4,
Configuration within Parallel Port
1 0 0 1
or
1 1 1 1
16 registers, from base to base + 07h and
from base + 400h to base + 407h
Configuration
30
THE CONFIGURATION REGISTERS
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2.3.1 Standard Plug and Play (PnP) Register Definitions
TABLES 2-5 through 2-10 describe the standard Plug and
Play registers. For more detailed information on these
registers, refer the
“Plug and Play ISA Specification, Ver-
sion 1.0a, May 5, 1994”.
TABLE 2-5. Plug and Play (PnP) Standard Control Registers
Index Name Definition
00h Set RD_DATA Port Writing to this location modifies the address of the port used for reading from the
Plug and Play ISA cards. Data bits 7-0 are loaded into I/O read port address bits
9-2.
Reads from this register are ignored. Bits1 and 0 are fixed at the value 11.
01h Serial Isolation Reading this register causes a Plug and Play card in the Isolation state to compare
one bit of the ID of the board. This register is read only.
02h Config Control This register is write-only. The values are not sticky, that is, hardware automatically
clears the bits and there is no need for software to do so.
Bit 0 - Reset
Writing this bit resets all logical devices and restores the contents of
configuration registers to their power-up (default) values.
In addition, all the logical devices of the card enter their default state and the
CSN is preserved.
Bit 1 - Return to the Wait for Key state.
Writing this bit puts all cards in the Wait for Key state, with all CSNs preserved
and logical devices not affected.
Bit 2 - Reset CSN to 0.
Writing this bit causes every card to reset its CSN to zero.
03h Wake[CSN] A write to this por t causes all cards that have a CSN that matches the write data
in bits 7-0 to go from the Sleep state to either the Isolation state, if the write data
for this command is zero, or the Config state, if the write data is not zero. It also
resets the pointer to the byte-serial device.
This register is write-only.
04h Resource Data This address holds the next byte of resource information. The Status register must
be polled until bit 0 of this register is set to 1 before this register can be read.
This register is read-only.
005 Status When bit 0 of this register is set to 1, the next data byte is available for reading
from the Resource Data register.
This register is read-only.
06h Card Select
Number (CSN)
Writing to this port assigns a CSN to a card. The CSN is a value uniquely assigned
to each ISA card after the serial identification process so that each card may be
individually selected during a Wake[CSN] command.
This register is read/write.
07h Logical Device
Number
This register selects the current logical device. All reads and writes of memory, I/O,
interrupt and DMA configuration information access the registers of the logical
device written here. In addition, the I/O Range Check and Activate commands
operate only on the selected logical device.
This register is read/write. If a card has only 1 logical device, this location should
be a read-only value of 00h.
20h - 2Fh Card Level,
Vendor Defined
Vendor defined registers.
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