NSC PC97307-IBW-EB, PC97307-IBW-VUL, PC97307-ICE-EB, PC97307-ICE-VUL, PC97307-ICK-VUL Datasheet

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PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

General Description

The PC87307/PC97307 (VUL) are functionally identical parts that offer a single-chip solution to the most commonly used ISA, EISA and MicroChannel

peripherals. This fully Plug and Play (PnP) compatible chip incorporates a Floppy Disk Controller (FDC), a Keyboard and mouse Controller (KBC), a Real-Time Clock (RTC), two fast full function UARTs, Infrared (IR) support, a full IEEE 1284 parallel port, three general purpose chip select signals that can be programmed for game port control, and a separate configuration register set for each module. It also provides support for power management (including a WATCHDOG timer) and standard PC-AT address decoding for on-chip functions.

The Plug and Play (PnP) support in the device conforms to the “

Plug and Play ISA Specification

” Version 1.0a, May 5,

1994. The Infrared (IR) interface complies with the IrDA 1.0 SIR

and SHARP-IR standards, and supports all four basic protocols for Consumer-IR (TV-Remote) circuitry (RC-5, RC-5 extended, RECS80 and NEC).

Features

■ 100% compatible with Plug and Play requirements specified in the “

Plug and Play ISA Specification

”, ISA,

EISA, and MicroChannel architectures

■ Meets PC97 requirements

PRELIMINARY

March 1998

PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

Highlights

Block Diagram

Real-Time Clock

(Logical Device 2)

Floppy Disk Controller (FDC) with Digital Data Separator (DDS)

(PC8477)

High Current Driver

Keyboard

Controller (KBC)

Power Management

Logic

µP Address

Floppy Drive Interface

Data Handshake

Data

Serial

Two UARTs + IR

(16550 or 16450)

X-Bus

IEEE1284

Control

Parallel Port

Interface

Infrared

Interface

Ports

(PnP)

IRQ

Control

DMA

Channels

(Logical Devices 5 & 6)

Interrupt

(RTC and APC)

Plug and Play

(Logical Device 8)

(Logical Device 0)

Data and

Control

(Logical Device 3)

Data and

Mouse

Controller

(Logical Device 1)

General Purpose

I/O Registers

(Logical Device 7)

I/O Ports

Data and

Control

(Logical Device 4)

Control

TRI-STATE® is a registered trademark of National Semiconductor Corporation. IBM

, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.

Microsoft

and Windows® are registered trademarks of Microsoft Corporation.

Highlights

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■ A special Plug and Play (PnP) module that includes: — Flexible IRQs, DMAs and base addresses that meet

the Plug and Play requirements speciﬁed by Microsoft

in their 1995 hardware design guide for

Windows

and Plug and Play ISA Revision 1.0A

— Plug and Play ISA mode (with isolation mechanism

– Wait for Key state)

— Motherboard Plug and Play mode

■ A Floppy Disk Controller (FDC) that provides: — A modiﬁable address that is referenced by a 16-bit

programmable register

— Software compatibility with the PC8477, which con-

tains a superset of the ﬂoppy disk controller functions in the µDP8473, the NEC µPD765A and the N82077

— 13 IRQ channel options — Four 8-bit DMA channel options — 16-byte FIFO — Burst and non-burst modes — A high-performance, internal, digital data separator

that does not require any external ﬁlter components

— Support for standard 5.25" and 3.5" floppy disk

drives

— Automatic media sense support — Perpendicular recording drive support — Three-mode Floppy Disk Drive (FDD) support — Full support for the IBM Tape Drive Register (TDR)

implementation of AT and PS/2 drive types

■ A Keyboard and mouse Controller (KBC) with: — A modiﬁable address that is referenced by a 16-bit

programmable register, reported as a ﬁxed address in resource data

— 13 IRQ options for the keyboard controller — 13 IRQ options for the mouse controller — An 8-bit microcontroller — Software compatibility with the 8042AH and

PC87911 microcontrollers

— 2 KB of custom-designed program ROM — 256 bytes of RAM for data — Five programmable dedicated open drain I/O lines

for keyboard controller applications

— Asynchronous access to two data registers and one

status register during normal operation

— Support for both interrupt and polling — 93 instructions — An 8-bit timer/counter — Support for binary and BCD arithmetic — Operation at 8 MHz,12 MHz or 16 MHz (programma-

ble option)

— Can be customized using the PC87323VUL, which

includes a RAM-based KBC, as a development platform for keyboard controller code

■ A Real-Time Clock (RTC) that has: — A modiﬁable address that is referenced by a 16-bit

programmable register

— 13 IRQ options, with programmable polarity — DS1287, MC146818 and PC87911 compatibility

— 242 bytes of battery backed up CMOS RAM in two

banks

— Selective lock mechanism for the RTC RAM — Battery backed up century calendar in days, days of

the week, months and years, with automatic leapyear adjustment

— Battery backed-up time of day in seconds, minutes

and hours that allows a 12 or 24 hour format and adjustments for daylight savings time

— BCD or binary format for time keeping — Three different maskable interrupt ﬂags:

• Periodic interrupts - At intervals from 122 msec

to 500 msec

• Time-of-day alarm - At intervals from once per

second to once per day

• Updated Ended Interrupt - Once per second

upon completion of update

— Separate battery pin, 2.4 V operation that includes

an internal UL protection resistor

— 2 µA maximum power consumption during power

down

— Double-buffer time registers

■ An Advanced Power supply Control (APC) that controls the main power supply to the system, using open-drain output, as follows:

Power turned on when:

— The RTC reaches a pre-determined date and time. — A high to low transition occurs on the

RI input signals

of the UARTs.

— A ring pulse or pulse train is detected on the

RING

input signal. — A SWITCH input signal indicates a Switch On event Powered turned off when:

— A SWITCH input signal indicates a Switch Off event — A Fail-safe event occurs (power-save mode detect-

ed but the system is hung up). — Software turns power off.

■ Two UARTs that provide: — Software compatibility with the 16550A and the

16450

— A modiﬁable address that is referenced by a 16-bit

programmable register

— 13 IRQ channel options — Shadow register support for write-only bits — Four 8-bit DMA options for the UART with Infrared

support (UART2)

■ An enhanced UART and Infrared (IR) interface on the UART2 that supports:

— UART data rates up to 1.5 Mbaud — IrDA 1.0 SIR — ASK-IR option of SHARP-IR — DASK-IR option of SHARP-IR — Consumer-IR (TV-Remote) circuitry — A Plug and Play compatible external transceiver

■ A bidirectional parallel port that includes:

— A modiﬁable address that is referenced by a 16-bit

programmable register

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— Software or hardware control — 13 IRQ channel options — Four 8-bit DMA channel options — Demand mode DMA support — An Enhanced Parallel Port (EPP) that is compatible

with the new version EPP 1.9, and is IEEE1284 compliant

— An Enhanced Parallel Port (EPP) that also supports

version EPP 1.7 of the Xircom speciﬁcation.

— Support for an Enhanced Parallel Port (EPP) as

mode 4 of the Extended Capabilities Port (ECP)

— An Extended Capabilities Port (ECP) that is IEEE

1284 compliant, including level 2

— Selection of internal pull-up or pull-down resistor for

Paper End (PE) pin

— Reduction of PCI bus utilization by supporting a de-

mand DMA mode mechanism and a DMA fairness mechanism

— A protection circuit that prevents damage to the par-

allel port when a printer connected to it powers up or is operated at high voltages

— Output buffers that can sink and source14 mA

■ Three general purpose pins for three separate programmable chip select signals, as follows:

— Can be programmed for game port control — The Chip Select 0 (

CS0) signal produces open drain

output and is powered by the V

CCH

— The Chip Select 1 (CS1) and 2 (CS2) signals have

push-pull buffers and are powered by the main V

— Decoding of chip select signals depends on the ad-

dress and the Address Enable (AEN) signals, and can be qualiﬁed using the Read (

RD) and Write

(

WR) signals.

■ 16 single-bit General Purpose I/O ports (GPIO): — Modiﬁable addresses that are referenced by a 16-bit

programmable register

— Programmable direction for each signal (input or

output) with conﬁguration lock

— Programmable drive type for each output pin (open-

drain or push-pull) with conﬁguration lock

— Programmable option for internal pull-up resistor on

each input pin with conﬁguration lock

— A back-drive protection circuit

■ An X-bus data buffer that connects the 8-bit X data bus to the ISA data bus

■ Clock source options: — Source is a 32.768 KHz crystal - an internal frequen-

cy multiplier generates all the required internal frequencies.

— Source may be either a 48 MHz or 24 MHz clock in-

put signal.

■ Enhanced Power Management (PM), including:

— Special conﬁguration registers for power down — WATCHDOG timer for power-saving strategies — Reduced current leakage from pins — Low-power CMOS technology — Ability to shut off clocks to all modules

■ General features include:

— All accesses to the SuperI/O chip activate a Zero

Wait State (

ZWS) signal, except for accesses to the Enhanced Parallel Port (EPP) and to conﬁguration registers

— Access to all conﬁguration registers is through an In-

dex and a Data register, which can be relocated within the ISA I/O address space

— 160-pin Plastic Quad Flatpack (PQFP) package

Highlights

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DRATE0

Parallel

Port

Connector

Conﬁguration

Select Logic

Clock

Power

Management

EIA

Drivers

EIA

Drivers

FDC

Connector

ONCTL

ISA Bus

Basic Conﬁguration

MR AEN A15-0 D7-0 RD WR

PD7-0 SLIN/ASTRB STB/WRITE AFD/DSTRB INIT

ACK ERR SLCT PE BUSY/WAIT

BADDR1,0 CFG3-0

CCH

SWITCH RING

SIN1

SOUT1

RTS1

DTR1/BOUT1

CTS1 DSR1 DCD1

RI1

SIN2

SOUT2

RTS2

DTR2/BOUT2

CTS2 DSR2 DCD2

RI2

RDATA WDATA WGATE HDSEL DIR

STEP TRK0

INDEX DSKCHG WP MTR1,0 DR1,0 DENSEL

IOCHRDY ZWS

RTC Crystal

and Power

BAT

X1C X2C

DRQ3-0 DACK3-0

P17,16,12

P21,20

KBCLK

KBDAT

MDAT

MCLK

CS2

Keyboard I/O

Interface

General

Purpose Registers

CS1,0

MSEN1,0

GPIO27-20

GPIO17-10

IRQ1

Infrared

Interface

IRRX2,1

IRTX

PC87307/PC97307

IRQ12-3 IRQ15-14

IRSL2-0

SELCS

X-Bus

XDCS XD7-0

XDRD

WDO

POR

ID3-0

Table of Contents

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Table of Contents

Highlights.............................................................................................................................1

1.0

Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM .........................................................................................................14

1.2 SIGNAL/PIN DESCRIPTIONS ...................................................................................................15

2.0

Configuration

2.1 HARDWARE CONFIGURATION ...............................................................................................24

2.1.1 Wake Up Options ........................................................................................................24

2.1.2 The Index and Data Register Pair ...............................................................................24

2.1.3 The Strap Pins .............................................................................................................25

2.2 SOFTWARE CONFIGURATION ...............................................................................................25

2.2.1 Accessing the Configuration Registers ........................................................................25

2.2.2 Address Decoding .......................................................................................................25

2.3 THE CONFIGURATION REGISTERS .......................................................................................26

2.3.1 Standard Plug and Play (PnP) Register Definitions ....................................................27

2.3.2 Configuration Register Summary ................................................................................30

2.4 CARD CONTROL REGISTERS ................................................................................................34

2.4.1 SID Register (In PC87307) ..........................................................................................34

2.4.2 SID Register (In PC97307) ..........................................................................................34

2.4.3 SuperI/O Configuration 1 Register, Index 21h .............................................................34

2.4.4 SuperI/O Configuration 2 Register, Index 22h .............................................................35

2.4.5 Programmable Chip Select Configuration Index Register, Index 23h .........................35

2.4.6 Programmable Chip Select Configuration Data Register, Index 24h ..........................36

2.4.7 SRID Register (In PC97307 only) ................................................................................36

2.5 KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) ....................................................36

2.5.1 SuperI/O KBC Configuration Register, Index F0h .......................................................36

2.6 FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 3) ..................................................36

2.6.1 SuperI/O FDC Configuration Register, Index F0h .......................................................36

2.6.2 Drive ID Register, Index F1h .......................................................................................37

2.7 PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4) ...............................37

2.7.1 SuperI/O Parallel Port Configuration Register, Index F0h ...........................................37

2.8 UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5) ....................38

2.8.1 SuperI/O UART2 Configuration Register, Index F0h ...................................................38

2.9 UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 6) ................................................38

2.9.1 SuperI/O UART1 Configuration Register, Index F0h ...................................................38

2.10 PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS ......................................39

2.10.1 CS0 Base Address MSB, Second Level Index 00h .....................................................39

2.10.2 CS0 Base Address LSB Register, Second Level Index 01h .......................................39

2.10.3 CS0 Configuration Register, Second Level Index 02h ................................................39

2.10.4 Reserved, Second Level Index 03h .............................................................................39

2.10.5 CS1 Base Address MSB Register, Second Level Index 04h ......................................40

2.10.6 CS1 Base Address LSB Register, Second Level Index 05h .......................................40

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2.10.7 CS1 Configuration Register, Second Level Index 06h ................................................40

2.10.8 Reserved, Second Level Index 07h .............................................................................40

2.10.9 CS2 Base Address MSB Register, Second Level Index 08h ......................................40

2.10.10 CS2 Base Address LSB Register, Second Level Index 09h .......................................40

2.10.11 CS2 Configuration Register, Second Level Index 0Ah ................................................40

2.10.12 Reserved, Second Level Indexes 0Bh-0Fh .................................................................40

2.10.13 Not Accessible, Second Level Indexes 10h-FFh .........................................................40

2.11 CARD CONTROL REGISTER BITMAPS ..................................................................................41

3.0

Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)

3.1 SYSTEM ARCHITECTURE .......................................................................................................43

3.2 FUNCTIONAL OVERVIEW .......................................................................................................44

3.3 DEVICE CONFIGURATION ......................................................................................................44

3.3.1 I/O Address Space ......................................................................................................44

3.3.2 Interrupt Request Signals ............................................................................................44

3.3.3 KBC Clock ...................................................................................................................45

3.3.4 Timer or Event Counter ...............................................................................................46

3.4 EXTERNAL I/O INTERFACES ..................................................................................................46

3.4.1 Keyboard and Mouse Interface ...................................................................................46

3.4.2 General Purpose I/O Signals .......................................................................................46

3.5 INTERNAL KBC - PC87307/PC97307 INTERFACE .................................................................47

3.5.1 The KBC DBBOUT Register, Offset 60h, Read Only ..................................................47

3.5.2 The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ............47

3.5.3 The KBC STATUS Register, Offset 64h, Read Only ...................................................48

3.6 INSTRUCTION TIMING .............................................................................................................48

4.0

Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)

4.1 RTC OPERATION OVERVIEW .................................................................................................49

4.1.1 RTC Hardware and Functional Description .................................................................49

4.1.2 Timekeeping ................................................................................................................50

4.1.3 Power Supply ..............................................................................................................51

4.1.4 Interrupt Handling ........................................................................................................52

4.2 THE RTC REGISTERS .............................................................................................................52

4.2.1 RTC Control Register A (CRA), Index 0Ah ..................................................................52

4.2.2 RTC Control Register B (CRB), Index 0Bh .................................................................54

4.2.3 RTC Control Register C (CRC), Index 0Ch .................................................................54

4.2.4 RTC Control Register D (CRD), Index 0Dh .................................................................55

4.3 APC OVERVIEW .......................................................................................................................55

4.3.1 User Selectable Parameters ........................................................................................55

4.3.2 System Power States ..................................................................................................56

4.3.3 System Power Switching Logic ...................................................................................56

4.4 DETAILED FUNCTIONAL DESCRIPTION ................................................................................58

4.4.1 The ONCTL Signal ......................................................................................................58

4.4.2 Entering Power States .................................................................................................58

4.4.3 System Power-Up and Power-Off Activation Event Description ..................................59

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4.5 APC REGISTERS ......................................................................................................................60

4.5.1 APC Control Register 1 (APCR1), Index 40h ..............................................................60

4.5.2 APC Control Register 2 (APCR2), Index 41h ..............................................................61

4.5.3 APC Status Register (APSR), Index 42h .....................................................................61

4.5.4 RAM Lock Register (RLR), Index 47h .........................................................................62

4.6 RTC AND APC REGISTER BITMAPS ......................................................................................62

4.6.1 RTC Register Bitmaps .................................................................................................62

4.6.2 APC Register Bitmaps .................................................................................................63

4.7 REGISTER BANK TABLES .......................................................................................................64

5.0

The Digital Floppy Disk Controller (FDC) (Logical Device 3)

5.1 FDC FUNCTIONS .....................................................................................................................66

5.1.1 Microprocessor Interface .............................................................................................66

5.1.2 System Operation Modes ............................................................................................66

5.2 DATA TRANSFER .....................................................................................................................67

5.2.1 Data Rates ...................................................................................................................67

5.2.2 The Data Separator .....................................................................................................67

5.2.3 Perpendicular Recording Mode Support .....................................................................68

5.2.4 Data Rate Selection .....................................................................................................68

5.2.5 Write Precompensation ...............................................................................................69

5.2.6 FDC Low-Power Mode Logic .......................................................................................69

5.2.7 Reset ...........................................................................................................................69

5.3 THE REGISTERS OF THE FDC ...............................................................................................70

5.3.1 Status Register A (SRA), Offset 00h ...........................................................................70

5.3.2 Status Register B (SRB), Offset 01h ...........................................................................71

5.3.3 Digital Output Register (DOR), Offset 02h ..................................................................71

5.3.4 Tape Drive Register (TDR), Offset 03h .......................................................................73

5.3.5 Main Status Register (MSR), Offset 04h, Read Operations ........................................74

5.3.6 Data Rate Select Register (DSR), Offset 04h, Write Operations ................................75

5.3.7 Data Register (FIFO), Offset 05h ................................................................................76

5.3.8 Digital Input Register (DIR), Offset 07h, Read Operations ..........................................77

5.3.9 Configuration Control Register (CCR), Offset 07h, Write Operations .........................78

5.4 THE PHASES OF FDC COMMANDS .......................................................................................78

5.4.1 Command Phase .........................................................................................................78

5.4.2 Execution Phase ..........................................................................................................78

5.4.3 Result Phase ...............................................................................................................80

5.4.4 Idle Phase ....................................................................................................................80

5.4.5 Drive Polling Phase .....................................................................................................80

5.5 THE RESULT PHASE STATUS REGISTERS ..........................................................................81

5.5.1 Result Phase Status Register 0 (ST0) .........................................................................81

5.5.2 Result Phase Status Register 1 (ST1) .........................................................................81

5.5.3 Result Phase Status Register 2 (ST2) .........................................................................82

5.5.4 Result Phase Status Register 3 (ST3) .........................................................................83

5.6 FDC REGISTER BITMAPS .......................................................................................................84

5.6.1 FDC Standard Register Bitmaps .................................................................................84

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5.6.2 FDC Result Phase Status Register Bitmaps ...............................................................85

5.7 THE FDC COMMAND SET .......................................................................................................86

5.7.1 Abbreviations Used in FDC Commands ......................................................................87

5.7.2 The CONFIGURE Command ......................................................................................88

5.7.3 The DUMPREG Command .........................................................................................88

5.7.4 The FORMAT TRACK Command ...............................................................................89

5.7.5 The INVALID Command ..............................................................................................92

5.7.6 The LOCK Command ..................................................................................................92

5.7.7 The MODE Command .................................................................................................92

5.7.8 The NSC Command ....................................................................................................94

5.7.9 The PERPENDICULAR MODE Command .................................................................94

5.7.10 The READ DATA Command .......................................................................................96

5.7.11 The READ DELETED DATA Command ......................................................................98

5.7.12 The READ ID Command .............................................................................................99

5.7.13 The READ A TRACK Command ...............................................................................100

5.7.14 The RECALIBRATE Command .................................................................................100

5.7.15 The RELATIVE SEEK Command ..............................................................................101

5.7.16 The SCAN EQUAL, the SCAN LOW OR EQUAL and the SCAN HIGH OR EQUAL

Commands ..........................................................................................................101

5.7.17 The SEEK Command ................................................................................................102

5.7.18 The SENSE DRIVE STATUS Command ..................................................................103

5.7.19 The SENSE INTERRUPT Command ........................................................................103

5.7.20 The SET TRACK Command ......................................................................................104

5.7.21 The SPECIFY Command ..........................................................................................105

5.7.22 The VERIFY Command .............................................................................................106

5.7.23 The VERSION Command ..........................................................................................108

5.7.24 The WRITE DATA Command ....................................................................................108

5.7.25 The WRITE DELETED DATA Command ..................................................................109

5.8 EXAMPLE OF A FOUR-DRIVE CIRCUIT USING THE PC87307/PC97307 ...........................110

6.0

Parallel Port (Logical Device 4)

6.1 PARALLEL PORT CONFIGURATION ....................................................................................111

6.1.1 Parallel Port Operation Modes ..................................................................................111

6.1.2 Configuring Operation Modes ....................................................................................111

6.1.3 Output Pin Protection ................................................................................................111

6.2 STANDARD PARALLEL PORT (SPP) MODES ......................................................................111

6.2.1 Standard Parallel Port (SPP) Modes Register Set ....................................................112

6.2.2 SPP Data Register (DTR), Offset 00h .......................................................................112

6.2.3 Status Register (STR), Offset 01h .............................................................................113

6.2.4 SPP Control Register (CTR), Offset 02h ...................................................................114

6.3 ENHANCED PARALLEL PORT (EPP) MODES ......................................................................115

6.3.1 Enhanced Parallel Port (EPP) Register Set ..............................................................115

6.3.2 SPP or EPP Data Register (DTR), Offset 00h ...........................................................115

6.3.3 SPP or EPP Status Register (STR), Offset 01h ........................................................115

6.3.4 SPP or EPP Control Register (CTR), Offset 02h .......................................................116

6.3.5 EPP Address Register (ADDR), Offset 03h ...............................................................116

6.3.6 EPP Data Register 0 (DATA0), Offset 04h ................................................................116

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6.3.7 EPP Data Register 1 (DATA1), Offset 05h ................................................................116

6.3.8 EPP Data Register 2 (DATA2), Offset 06h ................................................................116

6.3.9 EPP Data Register 3 (DATA3), Offset 07h ................................................................117

6.3.10 EPP Mode Transfer Operations ................................................................................117

6.3.11 EPP 1.7 and 1.9 Zero Wait State Data Write and Read Operations .........................118

6.4 EXTENDED CAPABILITIES PARALLEL PORT (ECP) ...........................................................119

6.4.1 ECP Modes ...............................................................................................................119

6.4.2 Software Operation ....................................................................................................119

6.4.3 Hardware Operation ..................................................................................................119

6.5 ECP MODE REGISTERS ........................................................................................................120

6.5.1 Accessing the ECP Registers ....................................................................................120

6.5.2 Second Level Offsets ................................................................................................120

6.5.3 ECP Data Register (DATAR), Bits 7-5 of ECR = 000 or 001, Offset 000h ................121

6.5.4 ECP Address FIFO (AFIFO) Register, Bits 7-5 of ECR = 011, Offset 000h ..............121

6.5.5 ECP Status Register (DSR), Offset 001h ..................................................................121

6.5.6 ECP Control Register (DCR), Offset 002h ................................................................122

6.5.7 Parallel Port Data FIFO (CFIFO) Register, Bits 7-5 of ECR = 010, Offset 400h .......122

6.5.8 ECP Data FIFO (DFIFO) Register, Bits 7-5 of ECR = 011, Offset 400h ...................122

6.5.9 Test FIFO (TFIFO) Register, Bits 7-5 of ECR = 110, Offset 400h .............................123

6.5.10 Configuration Register A (CNFGA), Bits 7-5 of ECR = 111, Offset 400h ..................123

6.5.11 Configuration Register B (CNFGB), Bits 7-5 of ECR = 111, Offset 401h ..................123

6.5.12 Extended Control Register (ECR), Offset 402h .........................................................124

6.5.13 ECP Extended Index Register (EIR), Offset 403h .....................................................125

6.5.14 ECP Extended Data Register (EDR), Offset 404h ....................................................126

6.5.15 ECP Extended Auxiliary Status Register (EAR), Offset 405h ...................................126

6.5.16 Control0, Second Level Offset 00h ............................................................................126

6.5.17 Control2, Second Level Offset 02h ............................................................................126

6.5.18 Control4, Second Level Offset 04h ............................................................................127

6.5.19 PP Confg0, Second Level Offset 05h ........................................................................127

6.6 DETAILED ECP MODE DESCRIPTIONS ...............................................................................128

6.6.1 Software Controlled Data Transfer (Modes 000 and 001) .........................................128

6.6.2 Automatic Data Transfer (Modes 010 and 011) ........................................................128

6.6.3 Automatic Address and Data Transfers (Mode 100) .................................................130

6.6.4 FIFO Test Access (Mode 110) ..................................................................................130

6.6.5 Configuration Registers Access (Mode 111) .............................................................130

6.6.6 Interrupt Generation ..................................................................................................130

6.7 PARALLEL PORT REGISTER BITMAPS ...............................................................................131

6.7.1 EPP Modes Parallel Port Register Bitmaps ...............................................................131

6.7.2 ECP Modes Parallel Port Register Bitmaps ..............................................................132

6.8 PARALLEL PORT PIN/SIGNAL LIST ......................................................................................134

7.0

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

7.1 FEATURES ..............................................................................................................................135

7.2 FUNCTIONAL MODES OVERVIEW .......................................................................................135

7.2.1 UART Modes: 16450 or 16550, and Extended ..........................................................135

7.2.2 Sharp-IR, IrDA SIR Infrared Modes ...........................................................................135

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7.2.3 Consumer IR Mode ...................................................................................................135

7.3 REGISTER BANK OVERVIEW ...............................................................................................136

7.4 UART MODES – DETAILED DESCRIPTION ..........................................................................136

7.4.1 16450 or 16550 UART Mode .....................................................................................137

7.4.2 Extended UART Mode ...............................................................................................137

7.5 SHARP-IR MODE – DETAILED DESCRIPTION .....................................................................138

7.6 SIR MODE – DETAILED DESCRIPTION ................................................................................138

7.7 CONSUMER-IR MODE – DETAILED DESCRIPTION ............................................................138

7.7.1 Consumer-IR Transmission .......................................................................................138

7.7.2 Consumer-IR Reception ............................................................................................138

7.8 FIFO TIME-OUTS ....................................................................................................................139

7.8.1 UART, SIR or Sharp-IR Mode Time-Out Conditions .................................................139

7.8.2 Consumer-IR Mode Time-Out Conditions .................................................................139

7.8.3 Transmission Deferral ...............................................................................................139

7.9 AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE ..........................................140

7.10 OPTICAL TRANSCEIVER INTERFACE .................................................................................140

7.11 BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS .................................................140

7.11.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD), Bank 0, Offset 00h .141

7.11.2 Interrupt Enable Register (IER), Bank 0, Offset 01h .................................................141

7.11.3 Event Identification Register (EIR), Bank 0, Offset 02h .............................................143

7.11.4 FIFO Control Register (FCR), Bank 0, Offset 02h .....................................................145

7.11.5 Link Control Register (LCR), Bank 0, Offset 03h, and Bank Selection Register (BSR),

All Banks, Offset 03h ...........................................................................................145

7.11.6 Bank Selection Register (BSR), All Banks, Offset 03h ..............................................147

7.11.7 Modem/Mode Control Register (MCR), Bank 0, Offset 04h ......................................147

7.11.8 Link Status Register (LSR), Bank 0, Offset 05h ........................................................148

7.11.9 Modem Status Register (MSR), Bank 0, Offset 06h ..................................................149

7.11.10 Scratchpad Register (SPR), Bank 0, Offset 07h .......................................................150

7.11.11 Auxiliary Status and Control Register (ASCR), Bank 0, Offset 07h ...........................150

7.11.12 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)),

Bank 1, Offsets 00h and 01h ...............................................................................151

7.11.13 Link Control Register (LCR) and Bank Select Register (BSR), Bank 1, Offset 03h ..152

7.12 BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................152

7.12.1 Baud Generator Divisor Ports, LSB (BGD(L)) and

MSB (BGD(H)),Bank 2, Offsets 00h and 01h ......................................................152

7.12.2 Extended Control Register 1 (EXCR1), Bank 2, Offset 02h ......................................154

7.12.3 Link Control Register (LCR) and Bank Select Register (BSR), Bank 2, Offset 03h ..155

7.12.4 Extended Control and Status Register 2 (EXCR2), Bank 2, Offset 04h ....................155

7.12.5 Reserved Register, Bank 2, Offset 05h .....................................................................155

7.12.6 TX_FIFO Current Level Register (TXFLV), Bank 2, Offset 06h ................................155

7.12.7 RX_FIFO Current Level Register (RXFLV), IrDA or Consumer-IR Modes,

Bank 2, Offset 07h ..............................................................................................156

7.13 BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS ..........................................156

7.13.1 Module Revision ID Register (MRID), Bank 3, Offset 00h .........................................156

7.13.2 Shadow of Link Control Register (SH_LCR), Bank 3, Offset 01h ..............................157

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7.13.3 Shadow of FIFO Control Register (SH_FCR), Bank 3, Offset 02h ............................157

7.13.4 Link Control Register (LCR) and Bank Select Register (BSR), Bank 3, Offset 03h ..157

7.14 BANK 4 – IR MODE SETUP REGISTER ................................................................................157

7.14.1 Reserved Registers, Bank 4, Offsets 00h and 01h ...................................................157

7.14.2 Infrared Control Register 1 (IRCR1), Bank 4, Offset 02h ..........................................157

7.14.3 Link Control Register (LCR) and Bank Select Register (BSR), Bank 4, Offset 03h ..158

7.14.4 Reserved Registers, Bank 4, Offsets 04h -07h .........................................................158

7.15 BANK 5 – INFRARED CONTROL REGISTERS .....................................................................158

7.15.1 Reserved Registers, Bank 5, Offsets 00h -02h .........................................................158

7.15.2 (LCR/BSR) Register, Bank 5, Offset 03h ..................................................................158

7.15.3 Infrared Control Register 2 (IRCR2), Bank 5, Offset 04h ..........................................158

7.15.4 Reserved Registers, Bank 5, Offsets 05h -07h .........................................................158

7.16 BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS .........................159

7.16.1 Infrared Control Register 3 (IRCR3), Bank 6, Offset 00h ..........................................159

7.16.2 Reserved Register, Bank 6, Offset 01h .....................................................................159

7.16.3 SIR Pulse Width Register (SIR_PW), Bank 6, Offset 02h .........................................159

7.16.4 Link Control Register (LCR) and Bank Select Register (BSR), Bank 6, Offset 03h ..159

7.16.5 Reserved Registers, Bank 6, Offsets 04h-07h ..........................................................159

7.17 BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS 159

7.17.1 Infrared Receiver Demodulator Control Register (IRRXDC), Bank 7, Offset 0 .........160

7.17.2 Infrared Transmitter Modulator Control Register (IRTXMC), Bank 7, Offset 01h ......160

7.17.3 Consumer-IR Configuration Register (RCCFG), Bank 7, Offset 02h ........................163

7.17.4 Link Control/Bank Select Registers (LCR/BSR), Bank 7, Offset 03h ........................163

7.17.5 Infrared Interface Configuration Register 1 (IRCFG1), Bank 7, Offset 04h ...............163

7.17.6 Reserved Register, Bank 7, Offset 05h .....................................................................164

7.17.7 Infrared Interface Configuration 3 Register (IRCFG3), Bank 7, Offset 06h ...............164

7.17.8 Infrared Interface Configuration Register 4 (IRCFG4), Bank 7, Offset 07h ...............164

7.18 UART2 REGISTER WITH FAST IR REGISTER BITMAPS ....................................................165

8.0

General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip Select Output Signals

8.1 GENERAL PURPOSE INPUT AND OUTPUT (GPIO) PORTS ...............................................170

8.2 PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS .........................................................171

9.0

Power Management (Logical Device 8)

9.1 POWER MANAGEMENT OPTIONS .......................................................................................172

9.1.1 Configuration Options ................................................................................................172

9.1.2 The WATCHDOG Feature .........................................................................................172

9.2 THE POWER MANAGEMENT REGISTERS ..........................................................................172

9.2.1 Power Management Index Register, Base Address + 00h ........................................172

9.2.2 Power Management Data Register, Base Address + 01h .........................................173

9.2.3 Function Enable Register 1 (FER1), Index 00h .........................................................173

9.2.4 Function Enable Register 2 (FER2), Index 01h .........................................................173

9.2.5 Power Management Control 1 Register (PMC1), Index 02h .....................................174

9.2.6 Power Management Control 2 Register (PMC2), Index 03h .....................................174

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9.2.7 Power Management Control 3 Register (PMC3), Index 04h .....................................175

9.2.8 Watchdog Time-Out (WDTO) Register, Index 05h ....................................................175

9.2.9 WATCHDOG Configuration Register (WDCF), Index 06h ........................................175

9.2.10 WATCHDOG Status Register (WDST), Index 07h ....................................................176

9.3 POWER MANAGEMENT REGISTER BITMAPS ....................................................................177

10.0

X-Bus Data Buffer

10.1 FUNCTIONAL OVERVIEW .....................................................................................................179

10.2 MAPPING ................................................................................................................................179

11.0

The Internal Clock

11.1 THE CLOCK SOURCE ............................................................................................................180

11.2 THE INTERNAL ON-CHIP CLOCK MULTIPLIER ...................................................................180

11.3 SPECIFICATIONS ...................................................................................................................180

12.0

Interrupt and DMA Mapping

12.1 IRQ MAPPING .........................................................................................................................181

12.2 DMA MAPPING .......................................................................................................................181

13.0

Device Description

13.1 GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................182

13.1.1 Recommended Operating Conditions .......................................................................182

13.1.2 Absolute Maximum Ratings .......................................................................................182

13.1.3 Capacitance ...............................................................................................................182

13.1.4 Power Consumption Under Recommended Operating Conditions ...........................183

13.2 DC CHARACTERISTICS OF PINS, BY GROUP ....................................................................183

13.2.1 Group 1 ......................................................................................................................183

13.2.2 Group 2 ......................................................................................................................184

13.2.3 Group 3 ......................................................................................................................184

13.2.4 Group 4 ......................................................................................................................184

13.2.5 Group 5 ......................................................................................................................185

13.2.6 Group 6 ......................................................................................................................185

13.2.7 Group 7 ......................................................................................................................185

13.2.8 Group 8 ......................................................................................................................186

13.2.9 Group 9 ......................................................................................................................186

13.2.10 Group 10 ....................................................................................................................187

13.2.11 Group 11 ....................................................................................................................187

13.2.12 Group 12 ....................................................................................................................188

13.2.13 Group 13 ....................................................................................................................188

13.2.14 Group 14 ....................................................................................................................189

13.2.15 Group 15 ....................................................................................................................189

13.2.16 Group 16 ....................................................................................................................189

13.2.17 Group 17 ....................................................................................................................190

13.2.18 Group 18 ....................................................................................................................190

13.2.19 Group 19 ....................................................................................................................190

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13.2.20 Group 20 ....................................................................................................................190

13.2.21 Group 21 ....................................................................................................................190

13.2.22 Group 22 ....................................................................................................................191

13.2.23 Group 23 ....................................................................................................................191

13.3 AC ELECTRICAL CHARACTERISTICS ..................................................................................191

13.3.1 AC Test Conditions TA = 0 °C to 70 °C, VDD = 5.0 V ±10% ......................................191

13.3.2 Clock Timing ..............................................................................................................192

13.3.3 Microprocessor Interface Timing ...............................................................................193

13.3.4 Baud Output Timing ...................................................................................................195

13.3.5 Transmitter Timing .....................................................................................................196

13.3.6 Receiver Timing .........................................................................................................197

13.3.7 UART, Sharp-IR and Consumer-IR Timing ...............................................................199

13.3.8 SIR Timing .................................................................................................................200

13.3.9 IRSLn Write Timing ...................................................................................................200

13.3.10 Modem Control Timing ..............................................................................................201

13.3.11 DMA Timing ...............................................................................................................202

13.3.12 Reset Timing .............................................................................................................204

13.3.13 Write Data Timing ......................................................................................................204

13.3.14 Drive Control Timing ..................................................................................................205

13.3.15 Read Data Timing ......................................................................................................205

13.3.16 Parallel Port Timing ...................................................................................................206

13.3.17 Enhanced Parallel Port 1.7 Timing ............................................................................207

13.3.18 Enhanced Parallel Port 1.9 Timing ............................................................................208

13.3.19 Extended Capabilities Port (ECP) Timing ..................................................................209

13.3.20 GPIO Write Timing ....................................................................................................210

13.3.21 RTC Timing ...............................................................................................................210

13.3.22 APC Timing ...............................................................................................................211

13.3.23 Chip Select Timing ....................................................................................................212

Signal/Pin Connection and Description

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1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM

1 5 10 15 20 25 30

859095100

4035

PC87307/PC97307

105110115120

121

125

130

135

140

145

150

155

160

A3A4A5A6A7A8A9

A10

A11

A12

A13

IOCHRDY

ZWS

WGATE

TRK0WPRDATA

HDSEL

MTR1

DSKCHG

DIR

STEP

WDATA

MSEN1

DENSEL

INDEX

MTR0

DR1

DR0

XDRD/ID3

MSEN0

P21

P20

P17

P16

P12

GPIO10 GPIO11 GPIO12 GPIO13

CS2/XD1

STB/WRITE

SLIN/ASTRB

SLCTPEBUSY/

WAIT

ACK

INIT

CS1/XD0

D0D1D2D3D4D5D6

X2C

CCH

A15

A14

BAT

X1C

VSSVDDKBCLK

KBDAT

MDAT

MCLK

IRQ15 IRQ14 IRQ12 IRQ11

DACK3

DRATE0

DTR1/BADDR0/BOUT1

RI1

DCD1 DSR1

SIN1

RTS1/BADDR1

SOUT1/CFG0

CTS1

IRQ10

AEN

IRQ9 IRQ8 IRQ7 IRQ6

IRQ1

IRQ3

IRQ4

IRQ5

GPIO14 GPIO15 GPIO16

GPIO17/WDO

GPIO20/IRSL1/ID1

GPIO21/IRSL2/IRSL0/ID2

GPIO22/POR

DRQ1 DRQ0

DACK2 DACK1 DACK0

DRQ2

DRQ3

ERR

DTR2/CFG1/BOUT2

RI2

DCD2 DSR2

SIN2

RTS2/CFG2

SOUT2/CFG3

CTS2

AFD/DSTRB

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 V

IRTX

IRRX1 IRRX2/IRSL0/ID0 IRSL1/XD7/ID1 IRSL2/XD6/SELCS/GPIO21

GPIO27/XD5 GPIO26/XD4 GPIO25/XD3 GPIO24/XD2

CS0/CSOUT-NSC-Test ONCTL SWITCH

RING/XDCS

GPIO23/

RING

Order Number PC87307VUL/PC97307VUL

See NS Package Number VUL160A

PlasticQuad Flatpack (PQFP), EIAJ

Signal/Pin Connection and Description

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1.2 SIGNAL/PIN DESCRIPTIONS

Table 1-1 lists the signals of the part in alphabetical order and shows the pin(s) associated with each. Table 1-2 on page 23 lists the X-Bus Data Buffer (XDB) signals that are multiplexed and Table 1-3 on page 23 lists the pins that have strap functions during reset.

The Module column indicates the functional module that is associated with these pins. In this column, the System label indicates internal functions that are common to more than one module.

The I/O and Group # column describes whether the pin is an input, output, or bidirectional pin (marked as Input, Output or I/O, respectively). This column also specifies the DC characteristics group to which this pin belongs. See Section 13.2 on page 183 for details.

Refer to the glossary for an explanation of abbreviations and terms used in this table, and throughout this document. Use the Table of Contents to find more information about each register.

TABLE 1-1. Signal/Pin Description Table

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

A15-0 29-26,

23-12

ISA-Bus Input

Group 1

ISA-Bus Address – A15-0 are used for address decoding on any access except DMA accesses, on the condition that the AEN signal is low. See Address Decoding in Section 2.2.2 on page 25.

ACK 113 Parallel Port Input

Group 3

Acknowledge – This input signal is pulsed low by the printer to indicate that it has received data from the parallel port. It is pulled up by an internal nominal 25 KΩ pull-up resistor.

AFD 119 Parallel Port I/O

Group 13

Automatic Feed – When this signal is low the printer should automatically feed a line after printing each line. This pin is in TRISTATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be attached to this pin.

For Input mode see bit 5 in “Control0, Second Level Offset 00h” on page 126.

This signal is multiplexed with DSTRB. See Table 6-12 on page 134 for more information.

AEN 30 ISA-Bus Input

Group 1

DMA Address Enable – This input signal disables function selection via A15-0 when it is high. Access during DMA transfer is not affected by this signal.

ASTRB 118 Parallel Port Output

Group 1

Address Strobe (EPP) – This signal is used in EPP mode as an address strobe. It is active low.

This signal is multiplexed with

SLIN. See Table 6-12 on page 134 for

more information.

BADDR1,0 136, 134 Conﬁguration Input

Group 5

Base Address Strap Pins 0 and 1 – These pins determine the base addresses of the Index and Data registers, the value of the Plug and Play ISA Serial Identiﬁer and the conﬁguration state immediately after reset. These pins are pulled down by internal 30 KΩ resistors. External 10 KΩ pull-up resistors to V

should be employed.

BADDR1 is multiplexed with

RTS1. BADDR0 is multiplexed with DTR1 and BOUT1. See Table 2-2 on page 25 and Section 2.1 on page 24.

BOUT2,1 144, 134 UART1,

UART2

Output

Group 17

Baud Output – This multi-function pin provides the associated serial channel Baud Rate generator output signal if test mode is selected, i.e., bit 7 of the EXCR1 register is set. (See Section “Bit 7 - Baud Generator Test (BTEST)” on page 155.)

After Master Reset this pin provides the SOUT function. BOUT2 is multiplexed with

DTR2 and CFG1. BOUT1 is multiplexed

with

DTR1 and BADDR0.

BUSY 111 Parallel Port Input

Group 2

Busy – This pin is set high by the printer when it cannot accept another character. It is internally connected to a nominal 25 KΩ pulldown resistor.

This signal is multiplexed with

WAIT. See Table 6-12 on page 134 for

more information.

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CFG3-0 148, 146,

144, 138

Conﬁguration Input

Group 5

Configuration Strap Pins 3-0 – These pins determine the default configuration upon power up. These pins are pulled down by internal 30 KΩ resistors. External 10 KΩ pull-up resistors to V

should be

employed. CFG3 is multiplexed with SOUT2. CFG2 is multiplexed with

RTS2.

CFG1 is multiplexed with

DTR2 and BOUT2. CFG0 is multiplexed with SOUT1. See Table 2-2 on page 25 and Section 2.1 on page 24 for more information.

CS0 68 General

Purpose

Output

Group 21

Programmable Chip Select – CS0, CS1 and CS2 are programmable chip select and/or latch enable and/or output enable signals that have many uses, for example, as game ports or for I/O port expansion.

The decoded address and the assertion conditions are conﬁgured via the chip conﬁguration registers. See Section 2.3 on page 26.

CS0 is an open-drain pin that is in TRI-STATE unless VDD is applied. CS2 is multiplexed with XD1, CS1 is multiplexed with XD0, and CS0

is multiplexed with

CSOUT-NSC-Test.

CS2,1 72, 71 General

Purpose

I/O

Group 9

CSOUTNSC-Test

68 NSC use Output

Group 21

Chip Select Read Output, NSC-Test – National Semiconductor test output. This is an open-drain output signal.

This signal is multiplexed with

CS0.

CTS2,1 141, 131 UART1,

UART2

Input

Group 1

UART1 and UART2 Clear to Send – When low, these signals indicate that the modem or other data transfer device is ready to exchange data.

The

CTS signal is a modem status input signal whose condition the CPU can test by reading bit 4 (CTS) of the Modem Status Register (MSR) for the appropriate serial channel. Bit 4 is the complement of the CTS signal. Bit 0 (DCTS) of MSR indicates whether the CTS input signal has changed state since the previous reading of MSR.

CTS has no

effect on the transmitter. Whenever the DCTS bit of the MSR is set, an interrupt is generated

if modem status interrupts are enabled.

D7-0 10-3 ISA-Bus I/O

Group 8

ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is the LSB and D7 is the MSB. These signals have 24 mA (sink) buffered outputs.

DACK3-0 59-56 ISA-Bus Input

Group 1

DMA Acknowledge 0,1,2 and 3 – These active low input signals acknowledge a request for DMA services and enable the

IOWR and IORD input signals during a DMA transfer. These DMA signals can be mapped to the following logical devices: FDC, UART1, UART2 or parallel port.

DCD2,1 142, 132 UART1,

UART2

Input

Group 1

UART1 and UART2 Data Carrier Detected – When low, this signal indicates that the modem or other data transfer device has detected the data carrier.

The

DCD signal is a modem status input signal whose condition the CPU can test by reading bit 7 (DCD) of the Modem Status Register (MSR) for the appropriate serial channel. Bit 7 is the complement of the

DCD signal.

Bit 3 (DDCD) of the MSR indicates whether the

DCD input signal has changed state since the previous reading of MSR. Whenever the DDCD bit of the MSR is set, an interrupt is generated if modem status interrupts are enabled.

DENSEL 94 FDC Output

Group 16

Density Select (FDC) – Indicates that a high FDC density data rate (500 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is selected.

DENSELs polarity is controlled by bit 5 of the SuperI/O FDC Conﬁguration register as described in Section 2.6.1 on page 36.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

Signal/Pin Connection and Description

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DIR 90 FDC Output

Group 16

Direction (FDC) – This output signal determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in, inactive = step out) during a seek operation. During reads or writes,

DIR is

inactive.

DR1,0 88, 87 FDC Output

Group 16

Drive Select 0 and 1 (FDC) – These active low output signals are the decoded drive select output signals.

DR0 and DR1 are controlled by Digital Output Register (DOR) bits 0 and 1. They are encoded with information to control four FDDs when bit 7 of the SuperI/O FDC Conﬁguration register is 1, as described in Section 2.6.1 on page 36.

See

MTR0,1 for more information.

DRATE0 84 FDC Output

Group 20

Data Rate 0 (FDC) – This output signal reflects the value of bit 0 of the Conﬁguration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last. Output from the pin is totem-pole buffered (6 mA sink, 6 mA source).

DRQ3-0 55-52 ISA-Bus Output

Group 18

DMA Request 0, 1, 2 and 3 – These active high output signals inform the DMA controller that a data transfer is needed. These DMA signals can be mapped to the following logical devices: Floppy Disk Controller (FDC), UART1, UART2 or parallel port.

DSKCHG 99 FDC Input

Group 1

Disk Change (FDC) – This input signal indicates whether or not the drive door has been opened. The state of this pin is available from the Digital Input Register (DIR). This pin can also be conﬁgured as the RGATE data separator diagnostic input signal via the MODE command. See the MODE command in Section 5.7.7 starting on page 92.

DSR2,1 143, 133 UART1,

UART2

Input

Group 1

Data Set Ready – When low, this signal indicates that the data transfer device, e.g., modem, is ready to establish a communications link.

The

DSR signal is a modem status input signal whose condition the CPU can test by reading bit 5 (DSR) of the Modem Status Register (MSR) for the appropriate channel. Bit 5 is the complement of the DSR signal. Bit 1 (DDSR) of the MSR indicates whether the DSR input signal has changed state since the previous reading of the MSR.

Whenever the DDSR bit of the MSR is set, an interrupt is generated if modem status interrupts are enabled.

DSTRB 119 Parallel Port Output

Group 23

Data Strobe (EPP) – This signal is used in EPP mode as a data strobe. It is active low.

DSTRB is multiplexed with AFD. See Table 6-12 on page 134 for more information.

DTR2,1 144, 134 UART1,

UART2

Output

Group 17

Data Terminal Ready – When low, this output signal indicates to the modem or other data transfer device that the UART1 or UART2 is ready to establish a communications link.

The

DTR signal can be set active low by programming bit 0 (DTR) of

the Modem Control Register (MCR) to high (1). A Master Reset (MR) deactivates this signal high, and loopback

operation holds this signal inactive. DTR2 is multiplexed with CFG1 and BOUT2. DTR1 is multiplexed

with BADDR0 and BOUT1.

ERR 116 Parallel Port Input

Group 3

Error – This input signal is set active low by the printer when it has detected an error. This pin is internally connected to a nominal 25 KΩ pull-up resistor.

GPIO17-10 156-149 General

Purpose

I/O

Group 10

General Purpose I/O Signals 17-10 – General purpose I/O signals of I/O Port 1.

GPIO17 is multiplexed with

WDO.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

Signal/Pin Connection and Description

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GPIO20 GPIO21 GPIO22 GPIO23 GPIO27-24

157 77, 158 159 160 76-73

General

Purpose

I/O

Group 10

General Purpose I/O Signals 27-20 – General purpose I/O port 2 signals.

GPIO27-24 are multiplexed with XD5-2, respectively. GPIO23 is multiplexed with

RING.

GPIO22 is multiplexed with

POR.

GPIO21 is multiplexed on pin 158 with IRSL2, IRSL0 and on pin 77 with IRSL2, SELCS and XD6. See “SuperI/O Conﬁguration 2 Register, Index 22h” on page 35.

GPIO20 is multiplexed with IRSL1.

HDSEL 92 FDC Output

Group 16

Head Select – This output signal determines which side of the FDD is accessed. Active low selects side 1, inactive selects side 0.

ID0 ID1 ID2 ID3

79 78 or 157 158 70

UART2 Input

Group 1

Identiﬁcation – These ID signals identify the infrared transceiver for Plug and Play support. These pins are read after reset.

ID0 is multiplexed on pin 79 with IRRX2 and IRSL0. ID1 is multiplexed on pin 78 with IRSL1 and XD7, or on pin 157 with

GPIO20 and IRSL1. ID2 is multiplexed on pin 158 with GPIO21, IRSL2 and IRSL0. ID3 is multiplexed on pin 70 with

XDRD.

See Table 1-2 on page 23 for more information.

INDEX 97 FDC Input

Group 1

Index – This input signal indicates the beginning of an FDD track.

INIT 117 Parallel Port I/O

Group 13

Initialize – When this signal is active low, it causes the printer to be initialized. This signal is in TRI-STATE after a 1 is loaded into the corresponding control register bit.

An external 4.7 KΩ pull-up resistor should be employed.

IOCHRDY 32 ISA-Bus Output

Group 22

I/O Channel Ready – This is the I/O channel ready open drain output signal. When IOCHRDY is driven low, the EPP extends the host cycle.

IRQ1 IRQ5-3 IRQ12-6 IRQ15,14

36 39-37 47-41 49,48

ISA-Bus I/O

Group 15

Interrupt Requests 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14 and 15 – IRQ polarity and push-pull or open-drain output selection is software conﬁgurable by the logical device mapped to the IRQ line.

Keyboard Controller (KBC) or Mouse interrupts can be conﬁgured by the Interrupt Request Type Select 0 register (index 71h) as either edge or level.

The parallel port interrupt is either edge or level, according to the operation mode (default edge, conﬁgured by the SuperI/O Parallel Port Conﬁguration register at index F0h).

IRRX2,1 79, 80 UART2

(SIR)

Input

Group 1

Infrared Reception 1 and 2 – Infrared serial input data. IRRX2 is multiplexed with IRSL0 and ID0. See Table 1-2 on page 23

for more information.

IRSL0 IRSL1 IRSL2

79 or 158 78 or 157 77 or 158

UART2

(SIR)

Output

Infrared Control Signals 0, 1 and 2 – These signals control the Infrared analog front end. The pins on which these signals are driven is determined by the SuperI/O Conﬁguration 2 register (index 22h). See Section 2.4.4 on page 35. IRSL0 or ID0/IRRX2 on pin 79 is determined by UART2 bit 5 of the IRCFG4 register (See page 165).

IRSL0 is multiplexed on pin 79 with IRRX2 and ID0, or on pin 158 with GPIO21, IRSL2 and ID2.

IRSL1 is multiplexed on pin 78 with XD7 and ID1, or on pin 157 with GPIO20 and ID1.

IRSL2 is multiplexed on pin 77 with XD6, SELCS and GPIO21, or on pin 158 with GPIO21, IRSL0 and ID2.

79, 78, 77

Group 17

158, 157

Group 10

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

Signal/Pin Connection and Description

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IRTX 81 UART2

(SIR)

Output

Group 19

Infrared Transmit – Infrared serial output data.

KBCLK 102 KBC I/O

Group 11

Keyboard Clock – This I/O pin transfers the keyboard clock between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is connected internally to the internal TO signal of the KBC.

KBDAT 103 KBC I/O

Group 11

Keyboard Data – This I/O pin transfers the keyboard data between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is connected internally to KBC’s P10.

MCLK 104 KBC I/O

Group 11

Mouse Clock – This I/O pin transfers the mouse clock between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is connected internally to KBC’s T1.

MDAT 105 KBC I/O

Group 11

Mouse Data – This I/O pin transfers the mouse data between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is connected internally to KBC’s P11.

MR 51 ISA-Bus Input

Group 1

Master Reset – An active high MR input signal resets the controller to the idle state, and resets all disk interface output signals to their inactive states. MR also clears the DOR, DSR and CCR registers, and resets the MODE command, CONFIGURE command, and LOCK command parameters to their default values. MR does not affect the SPECIFY command parameters. MR sets the conﬁguration registers to their selected default values.

MSEN1,0 83, 82 FDC Input

Group 4

Media Sense – These input pins are used for media sensing when bit 6 of the SuperI/O FDC Conﬁguration register (at index F0h) is 1. See Section 2.6.1 on page 36. Each pin has a 40 KΩ internal pull-up resistor.

MTR1,0 86, 85 FDC Output

Group 16

Motor Select 1,0 – These motor enable lines for drives 0 and 1 are controlled by bits D7-4 of the Digital Output Register (DOR). They are output signals that are active when they are low. They are encoded with information to control four FDDs when bit 7 of the SuperI/O FDC Conﬁguration register is set, as described in Section 2.6.1 on page 36. See

DR1,0.

ONCTL 67 APC Output

Group 23

On/Off Control for the RTC’s Advanced Power Control (APC) –

This signal indicates to the main power supply that power should be turned on.

ONCTL is an open-drain output signal that is powered by

CCH

P17,16 P12

108, 107 106

KBC I/O

Group 12

I/O Port – KBC quasi-bidirectional port for general purpose input and output.

P21,20 110, 109 KBC I/O

Group 12

I/O Port – KBC open-drain signals for general purpose input and output. These signals are controlled by KBC ﬁrmware.

PD7-0 129-122 Parallel Port I/O

Group 14

Parallel Port Data – These bidirectional signals transfer data to and from the peripheral data bus and the appropriate parallel port data register. These signals have a high current drive capability. See “GENERAL DC ELECTRICAL CHARACTERISTICS” on page 182.

PE 115 Parallel Port Input

Group 2

Paper End – This input signal is set high by the printer when it is out of paper. This pin has an internal nominal 25 KΩ pull-up or pull-down resistor that is selected by bit 2 of the PP Confg0 register (second level offset 05h) of the parallel port.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

Signal/Pin Connection and Description

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POR 159 APC Output

Group 21

Power Off Request – This signal becomes active when an APC Switch Off event occurs, regardless of the fail-safe delay. Selection of edge or level for

POR is via the APCR1 register of the APC. Selection of an output buffer is via GPIO22 output buffer control bits (in the Port 2 Output Type and Port 2 Pull-up Control registers described in Table 8-1 on page 170). See Section 4.3 on page 55.

This signal is multiplexed with GPIO22.

RD 33 ISA-Bus Input

Group 1

I/O Read – An active low RD input signal indicates that the microprocessor has read data.

RDATA 95 FDC Input

Group 1

Read Data – This input signal holds raw serial data read from the Floppy Disk Drive (FDD).

RI2,1 145, 135 UART1, APC Input

Group 7

Ring Indicators (Modem) – When low, this signal indicates that a telephone ring signal has been received by the modem.

The CPU can test the status of the

RI modem status input signal by reading bit 6 (RI) of the Modem Status Register (MSR) for the appropriate serial channel. Bit 6 is the complement of the

RI signal.

Bit 2 (TERI) of the MSR indicates whether the

RI input signal has

changed from low to high since the previous reading of the MSR. When the TERI bit of the MSR is set, an interrupt is generated if

modem status interrupts are enabled. When enabled, a high to low transition on

RI1 or RI2 activates the ONCTL pin. The RI1 and RI2 pins each have an schmitt-trigger input buffer.

RING 69 or 160 APC Input

Group 7

Ring Indicator (APC) – Detection of an active low RING pulse or pulse train activates the

ONCTL signal. The APC’s APCR2 register

determines which pin the

RING signal uses. The pins have a schmitt-

trigger input buffer. RING is multiplexed on pin 69 with XDCS and on pin 160 with

GPIO23.

RTS2,1 146, 136 UART1,

UART2

Output

Group 17

Request to Send – When low, these output signals indicate to the modem or other data transfer device that the corresponding UART1 or UART2 is ready to exchange data.

The

RTS signal can be set active low by programming bit 1 (RTS) of the Modem Control Register (MCR) to a high level. A Master Reset (MR) sets

RTS to inactive high. Loopback operation holds it inactive.

RTS2 is multiplexed with CFG2. RTS1 is multiplexed with BADDR1.

SELCS 77 Conﬁguration Input

Group 4

Select CSOUT – During reset, this signal is sampled into bit 1 of the SuperI/O Conﬁguration 1 register (index 21h).

A 40 KΩ internal pull-up resistor (or a 10 KΩ external pull-down resistor for National Semiconductor testing) controls this pin during reset. Do not pull this signal low during reset.

This signal is multiplexed with GPIO21, IRSL2 and XD6.

SIN2,1 147, 137 UART1,

UART2

Input

Group 1

Serial Input – This input signal receives composite serial data from the communications link (peripheral device, modem or other data transfer device.)

SLCT 114 Parallel Port Input

Group 2

Select – This input signal is set active high by the printer when the printer is selected. This pin is internally connected to a nominal 25 KΩ pull-down resistor.

SLIN 118 Parallel Port I/O

Group 13

Select Input – When this signal is active low it selects the printer. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit.

An external 4.7 KΩ pull-up resistor should be used. This signal is multiplexed with

ASTRB.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

Signal/Pin Connection and Description

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SOUT2,1 148, 138 UART1,

UART2

Output

Group 17

Serial Output – This output signal sends composite serial data to the communications link (peripheral device, modem or other data transfer device).

The SOUT2,1 signals are set active high after a Master Reset (MR). SOUT2 is multiplexed with CFG3. SOUT1 is multiplexed with CFG0.

STB 112 Parallel Port I/O

Group 13

Data Strobe – This output signal indicates to the printer that valid data is available at the printer port.

This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit.

An external 4.7 KΩ pull-up resistor should be employed. This signal is multiplexed wiTH

WRITE.

STEP 91 FDC Output

Group 16

Step – This output signal issues pulses to the disk drive at a software programmable rate to move the head during a seek operation.

SWITCH 66 APC Input

Group 7

Switch On/Off – Indicates a request to the APC to switch the power on or off. When V

does not exist, a high to low transition on this

signal indicates a Switch On request. When V

exists, a high to low

transition on this pin indicates a Switch Off request. The pin has an internal pull-up of 1 MΩ (nominal), a schmitt-trigger

input buffer and debounce protection of at least 16 msec.

TC 35 ISA-Bus Input

Group 1

DMA Terminal Count – The DMA controller issues TC to indicate the termination of a DMA transfer. TC is accepted only when a

DACK

signal is active. TC is active high in PC-AT mode, and active low in PS/2 mode.

TRK0 96 FDC Input

Group 1

Track 0 – This input signal indicates to the controller that the head of the selected floppy disk drive is at track 0.

BAT

64 RTC and

APC

Input Battery Power Supply – Power signal from the battery to the Real-

Time Clock (RTC) or for Advanced Power Control (APC) when V

CCH

is less than V

BAT

(by at least 0.5 V). V

BAT

includes a UL protection

resistor.

CCH

65 RTC and

APC

Input VCC Help Power Supply – This signal provides power to the RTC or

APC when V

CCH

is higher than V

BAT

(by at least 0.5 V).

1, 24, 61, 100, 121, 140

Power

Supply

Input Main 5 V Power Supply – This signal is the 5 V supply voltage for

the digital circuitry.

2, 11, 25, 40, 60, 101, 120, 130, 139

Power

Supply

Output Ground – This signal provides the ground for the digital circuitry.

WAIT 111 Parallel Port Input

Group 2

Wait – In EPP mode, the parallel port device uses this signal to extend its access cycle.

WAIT is active low. It is internally connected

to a nominal 25 KΩ pull-down resistor. This signal is multiplexed with BUSY. See Table 6-12 on page 134 for

more information.

WDATA 89 FDC Output

Group 16

Write Data (FDC) – This output signal holds the write precompensated serial data that is written to the selected floppy disk drive. Precompensation is software selectable.

WDO 156 Power

Management

Output

Group 10

WATCHDOG Out – This output pin becomes low when a WATCHDOG time-out occurs. See “The WATCHDOG Feature” on page 172. This pin is conﬁgured by bit 6 of the SuperI/O Conﬁguration Register 2.

This signal is multiplexed with GPIO17.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

Signal/Pin Connection and Description

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WGATE 93 FDC Output

Group 16

Write Gate (FDC) – This output signal enables the write circuitry of the selected disk drive.

WGATE is designed to prevent glitches during power up and power down. This prevents writing to the disk when power is cycled.

WP 98 FDC Input

Group 1

Write Protected – This input signal indicates that the disk in the selected drive is write protected.

WR 34 ISA-Bus Input

Group 1

I/O Write – WR is an active low input signal that indicates a write operation from the microprocessor to the controller.

WRITE 112 Parallel Port Output

Group 23

Write Strobe – In EPP mode, this active low signal is a write strobe. This signal is multiplexed with

STB. See Table 6-12 on page 134 for

more information.

X1 50 Clock Input

Group 6

Clock In – A TTL or CMOS compatible 24 MHz or 48 MHz clock. See Chapter 11.

X1C 62 RTC Input Crystal 1 Slow – Input signal to the internal Real-Time Clock (RTC)

crystal oscillator ampliﬁer.

X2C 63 RTC Output Crystal 2 Slow – Output signal from the internal Real-Time Clock

(RTC) crystal oscillator ampliﬁer.

XD7,6, XD1,0

78, 77 72, 71

X-Bus I/O

Group 9

X-Bus Data – These bidirectional signals hold the data in the X Data Buffer (XDB).

XD7 is multiplexed with IRSL1 and ID1. XD6 is multiplexed with IRSL2, SELCS and GPIO21. XD5-2 are multiplexed with GPIO27-24, respectively. XD1,0 are multiplexed with

CS2,1 respectively.

See Table 1-2 on page 23.

XD5-2 76-73 X-Bus I/O

Group 10

XDCS 69 X-Bus Input

Group 7

X-Bus Data Buffer (XDB) Chip Select – This signal enables and disables the bidirectional XD7-0 data buffer signals.

This signal is multiplexed with

RING. See Table 1-2 on page 23.

XDRD 70 X-Bus Input

Group 1

X-Bus Data Buffer (XDB) Read Command – This signal controls the direction of the bidirectional XD7-0 data buffer signals.

This signal is multiplexed with ID3. See Table 1-2 on page 23.

ZWS 31 ISA-Bus Output

Group 22

Zero Wait State – When this open-drain output signal is activated (driven low), it indicates that the access time can be shortened, i.e., zero wait states.

ZWS is never activated (driven low) on access to SuperI/O chip conﬁguration registers (including during the Isolation state) or on access to the parallel port in SPP or EPP 1.9 mode.

ZWS is always activated (driven low) on access to the parallel port in ECP mode.

Assertion of

ZWS on access to a parallel port in EPP 1.7 mode is controlled by bit 3 of the Control2 register (at second level offset 02h) of the parallel port (accessed by the Index and Data registers at base+403h and base+404h). See page 127.

Bit 0 of the SuperI/O Conﬁguration 1 register (at index 21h) controls assertion of

ZWS on access to any other addresses of the part. See

page 35.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

Signal/Pin Connection and Description

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In Table 1-2, unselected (XDB or alternate function) input signals are internally blocked high.

TABLE 1-2. Multiplexed X-Bus Data Buffer (XDB) Pins

TABLE 1-3. Pins with a Strap Function During Reset

X-Bus Data Buffer (XDB)

Bit 4 of SuperI/O Conﬁguration

I/O

Alternate Function

Bit 4 of SuperI/O Conﬁguration 1

I/O

69 XDCS Input RING Input 70

XDRD Input ID3 Input

71 XD0 I/O

CS1 Output

72 XD1 I/O

CS2 Output 73 XD2 I/O GPIO24 I/O 73 XD3 I/O GPIO25 I/O 75 XD4 I/O GPIO26 I/O 76 XD5 I/O GPIO27 I/O 77 XD6/SELCS I/O IRSL2/SELCS/GPIO21 I/O 78 XD7 I/O IRSL1/ID1 I/O

Strap Pins Pin Symbols

BADDR1,0 134

DTR1/BADDR0/BOUT1

136

RTS1/BADDR1

CFG3-0 138 SOUT1/CFG0

144

DTR2/CFG1/BOUT2

146

RTS2/CFG2

148 SOUT2/CFG3

SELCS 77 IRSL2/XD6/SELCS/GPIO21

Configuration

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2.0 Conﬁguration

The part is partially configured by hardware, during reset. The configuration can also be changed by software, by changing the values of the configuration registers.

The configuration registers are accessed using an Index register and a Data register. During reset, hardware strapping options define the addresses of the configuration registers. See Section 2.1.2.

After the Index and Data register pair have determined the addresses of the conﬁguration registers, the addresses of the Index and Data registers can be changed within the ISA I/O address space, and a 16-bit programmable register controls references to their addresses and to the addresses of the other registers.

This chapter describes the hardware and software configuration processes. For each, it describes configuration of the Index and Data register pair first. See Sections 2.1 and 2.2.

Section 2.3 starting on page 26 presents an overview of the configuration registers of the part and describes each in detail.

2.1 HARDWARE CONFIGURATION

The part supports two Plug and Play (PnP) configuration modes that determine the status of register addresses upon wake up from a hardware reset, Full PnP ISA mode and PnP Motherboard mode.

2.1.1 Wake Up Options

During reset, strapping options on the BADDR0 and BADDR1 pins determine one of the following modes.

• Full Plug and Play ISA mode – System wakes up in

Wait for Key state. Index and Data register addresses are as defined by Mi-

crosoft and Intel in the

“Plug and Play ISA Specification,

Version 1.0a, May 5, 1994.”

• Plug and Play Motherboard mode – system wakes up

in Conﬁg state. The BIOS configures the part. Index and Data register

addresses are different from the addresses of the PnP Index and Data registers. Configuration registers can be accessed as if the serial isolation procedure had already been done, and the part is selected.

The BIOS may switch the addresses of the Index and Data registers to the PnP ISA addresses of the Index and Data registers, by using software to modify the base address bits of the SuperI/O Configuration 2 register (at Index 22h). See Section 2.4.4

2.1.2 The Index and Data Register Pair

During reset, a hardware strapping option on the BADDR0 and BADDR1 pins defines an address for the Index and Data Register pair. This prevents contention between the registers for I/O address space.

Table 2-1 shows the base addresses for the Index and Data registers that hardware sets for each combination of values of the Base Address strap pins (BADDR0 and BADDR1). You can access and change the content of the configuration registers at any time, as long as the base addresses of the Index and Data registers are defined.

When BADDR1 is low (0), the PnP protocol defines the addresses of the Index and Data register, and the system wakes up from reset in the Wait for Key state.

When BADDR1 is high (1), the addresses of the Index and Data register are according to Table 2-1, and the system wakes up from reset in the Config state.

This configures the part with default values, automatically, without software intervention. After reset, use software as described in Section 2.2 to modify the selected base address of the Index and Data register pair, and the defaults for configuration registers.

The Plug and Play soft reset has no effect on the logical devices, except for the effect of the Activate registers (index 30h) in each logical device.

The part can wake up with the FDC, the KBC and the RTC either active (enabled) or inactive (disabled). The clock multiplier, if configured via CFG3,2 strap pins, wakes up enabled. The other logical devices wake up inactive (disabled).

TABLE 2-1. Base Addresses

BADDR1 BADDR0

Address

Conﬁguration Type

Index Register Data Register

0279h

Write Only

Write: 0A79h

Read: RD_DATA Port

Full PnP ISA Mode

Wake up in Waitfor Key state

1 0 015Ch Read/Write 015Dh Read/Write

PnP Motherboard Mode Wake up in Conﬁg state

1 1 002Eh Read/Write 002Fh Read/Write

PnP Motherboard Mode Wake up in Conﬁg state

Configuration

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2.1.3 The Strap Pins TABLE 2-2. Strap Pins

Pin Reset Conﬁguration Affected

CFG0 0 - FDC, KBC and RTC wake up inactive.

1 - FDC, KBC and RTC wake up active.

Bit 0 of Activate registers (index 30h) of logical devices 0,2 and 3.

CFG1

0 - No X-Bus Data Buffer. (See XDB pins multiplexing in Table 1-2.) 1 - X-Bus Data Buffer (XDB) enabled.

Bit 4 of SuperI/O Conﬁguration 1 register (index 21h).

CFG3,2 00 - Clock source is 24 MHz fed via X1 pin.

01 - Reserved for

CSOUT-NSC-Test fed via X1 pin. 10 - Clock source is 48 MHz fed via X1 pin. 11 - Clock source is 32.768 KHz with on-chip clock multiplier.

Bits 2-0 of PMC2 register of Power Management (logical device 8) CFG2 affects bits 0 and 2.

CFG3 affects bit 1.

BADDR1,0 00 - Full PnP ISA, Wake in Wait For Key state. Index PnP ISA.

01 - Full PnP ISA, Wake in Wait For Key state. Index PnP ISA. 10 - PnP Motherboard, Wake in Conﬁg state. Index 015Ch. 11 - PnP Motherboard, Wake in Conﬁg state. Index 002Eh.

Bits 1 and 0 of SuperI/O Conﬁguration 2 register (index 22h)

SELCS 0 -

CSOUT-NSC-test on CS0 pin.

1 -

CS0 on CS0 pin.

Bit 1 of SuperI/O Conﬁguration 1 register (index 21h).

2.2 SOFTWARE CONFIGURATION

2.2.1 Accessing the Configuration Registers

Only two system I/O addresses are required to access any of the configuration registers. The Index and Data register pair is used to access registers for all read and write operations.

In a write operation, the target configuration register is identified, based on a value that is loaded into the Index register. Then, the data to be written into the configuration register is transferred via the Data register.

Similarly, for a read operation, first the source configuration register is identified, based on a value that is loaded into the Index register. Then, the data to be read is transferred via the Data register.

Reading the Index register returns the last value loaded into the Index register. Reading the Data register returns the data in the configuration register pointed to by the Index register.

If, during reset, the Base Address 1 (BADDR1) signal is low (0), the Index and Data registers are not accessible immediately after reset. As a result, all configuration registers of the part are also not accessible at this time. To access these registers, apply the PnP ISA protocol.

If during reset, the Base Address 1 (BADDR1) signal is high (1), all configuration registers are accessible immediately after reset.

It is up to the configuration software to guarantee no conflicts between the registers of the active (enabled) logical devices, between IRQ signals and between DMA channels. If conflicts of this type occur, the results are unpredictable.

To maintain compatibility with other SuperI/O‘s, the value of reserved bits may not be altered. Use read-modify-write.

2.2.2 Address Decoding

In full Plug and Play mode, the addresses of the Index and Data registers that access the configuration registers are decoded using pins A11-0, according to the ISA Plug and Play specification.

In Plug and Play Motherboard mode, the addresses of the Index and Data registers that access the configuration registers are decoded using pins A15-1. Pin A0 distinguishes between these two registers.

KBC and mouse register addresses are decoded using pins A1,0 and A15-3. Pin A2 distinguishes between the device registers.

RTC/APC and Power Management (PM) register addresses are decoded using pins A15-1. PM has only five registers and only responds to accesses to those registers.

FDC, UART, and GPIO register addresses are decoded using pins A15-3.

Parallel Port (PP) modes determine which pins are used for register addresses. In SPP mode, 14 pins are used to decode Parallel Port (PP) base addresses. In ECP and EPP modes, 13 address pins are used. Table 2-3 shows which address pins are used in each mode.

TABLE 2-3. Address Pins Used for Parallel Port

PP Mode

Pins Used to Decode Base

Address

Pins Used to

Distinguish Registers

SPP A15-2 A1,0

ECP A9-2 and A15-11 A1,0 and A10

EPP A15-3 A2-0

Configuration

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TABLE 2-4. Parallel Port Address Range Allocation

a. The SuperI/O processor does not decode the Parallel Port outside this range.

Parallel Port Mode

SuperI/O Parallel Port

Conﬁguration Register Bits

7 6 5 4

Decoded Range

SPP 0 0 x x Three registers, from base to base + 02h

EPP (Non ECP Mode 4) 0 1 x x Eight registers, from base to base + 07h

ECP, No Mode 4,

No Internal Conﬁguration

1 0 0 0

Six registers, from base to base + 02h and from base + 400h to base + 402h

ECP with Mode 4,

No Internal Conﬁguration

1 1 1 0

11 registers, from base to base+ 07h and from base + 400h to base + 402h

ECP with Mode 4,

Conﬁguration within Parallel Port

1 0 0 1

1 1 1 1

16 registers, from base to base + 07h and from base + 400h to base + 407h

2.3 THE CONFIGURATION REGISTERS

The configuration registers control the setup of the part. Their major functions are to:

• Identify the chip

• Enable major functions (such as, the Keyboard Control-

ler (KBC) for the keyboard and the mouse, the RealTime Clock (RTC), including Advanced Power Control (APC), the Floppy Disc Controller (FDC), UARTs, parallel and general purpose ports, power management and pin functionality)

• Define the I/O addresses of these functions

• Define the status of these functions upon reset

Section 2.3.2 summarizes information for each register of each function. In addition, the following non-standard, or card control registers are described in detail in Section 2.4, starting on page 34.

• Card Control Registers

— SuperI/O Conﬁguration 1 Register (SIOC1) — SuperI/O Conﬁguration 2 Register (SIOC2) — Programmable Chip Select Conﬁguration Index

— Programmable Chip Select Conﬁguration Data Reg-

ister

• KBC Configuration Register (Logical Device 0)

— SuperI/O KBC Conﬁguration Register

• FDC Configuration Registers (Logical Device 3)

— SuperI/O FDC Conﬁguration Register — Drive ID Register

• Parallel Port Conﬁguration Register (Logical Device 4)

— SuperI/O Parallel Port Conﬁguration Register

• UART2 and Infrared Conﬁguration Register (Logical

Device 5) — SuperI/O UART2 Conﬁguration Register

• UART1 Conﬁguration Register (Logical Device 6)

— SuperI/O UART1 Conﬁguration Register

• Programmable Chip Select Conﬁguration Registers

—

CS0 Base Address MSB Register

—

CS0 Base Address LSB Register

—

CS0 Conﬁguration Register

—

CS1 Base Address MSB Register

—

CS1 Base Address LSB Register

—

CS1 Conﬁguration Register

—

CS2 Base Address MSB Register

—

CS2 Base Address LSB Register

—

CS2 Conﬁguration Register

Configuration

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2.3.1 Standard Plug and Play (PnP) Register Definitions

Tables 2-5 through 2-10 describe the standard Plug and Play registers. For more detailed information on these registers, refer the

“Plug and Play ISA Specification, Version 1.0a, May 5, 1994.”

TABLE 2-5. PnP Standard Control Registers

Index Name Deﬁnition

00h Set RD_DATA Port Writing to this location modiﬁes the address of the port used for reading from the

Plug and Play ISA cards. Data bits 7-0 are loaded into I/O read port address bits 9-2.

Reads from this register are ignored. Bits1 and 0 are ﬁxed at the value 11.

01h Serial Isolation Reading this register causes a Plug and Play card in the Isolation state to compare

one bit of the ID of the board. This register is read only.

02h Conﬁg Control This register is write-only. The values are not sticky, that is, hardware automatically

clears the bits and there is no need for software to do so. Bit 0 - Reset

Writing this bit resets all logical devices and restores the contents of conﬁguration registers to their power-up (default) values.

In addition, all the logical devices of the card enter their default state and the CSN is preserved.

Bit 1 - Return to the Wait for Key state.

Writing this bit puts all cards in the Wait for Key state, with all CSNs preserved and logical devices not affected.

Bit 2 - Reset CSN to 0.

Writing this bit causes every card to reset its CSN to zero.

03h Wake[CSN] A write to this port causes all cards that have a CSN that matches the write data in

bits 7-0 to go from the Sleep state to either the Isolation state, if the write data for this command is zero, or the Conﬁg state, if the write data is not zero. It also resets the pointer to the byte-serial device.

This register is write-only.

04h Resource Data This address holds the next byte of resource information. The Status register must

be polled until bit 0 of this register is set to 1 before this register can be read. This register is read-only.

005 Status When bit 0 of this register is set to 1, the next data byte is available for reading

from the Resource Data register. This register is read-only.

06h Card Select

Number (CSN)

Writing to this port assigns a CSN to a card. The CSN is a value uniquely assigned to each ISA card after the serial identiﬁcation process so that each card may be individually selected during a Wake[CSN] command.

This register is read/write.

07h Logical Device

Number

This register selects the current logical device. All reads and writes of memory, I/O, interrupt and DMA conﬁguration information access the registers of the logical device written here. In addition, the I/O Range Check and Activate commands operate only on the selected logical device.

20h - 2Fh Card Level,

Vendor Deﬁned

Vendor deﬁned registers.

Configuration

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TABLE 2-6. PnP Logical Device Control Registers

TABLE 2-7. PnP I/O Space Conﬁguration Registers

Index Name Deﬁnition

0030h Activate For each logical device there is one Activate register that controls whether or not the

logical device is active on the ISA bus. This is a read/write register. Before a logical device is activated, I/O Range Check must be disabled. Bit 0 - Logical Device Activation Control

0 - Do not activate the logical device. 1 - Activate the logical device.

Bits 7-1 - Reserved

These bits are reserved and return 0 on reads.

0031h I/O Range Check This register is used to perform a conﬂict check on the I/O port range programmed

for use by a logical device. This register is read/write. Bit 0 - I/O Range Check control

0 - The logical device drives 00AAh. 1 - The logical device responds to I/O reads of the logical device's assigned I/O

range with a 0055h when I/O Range Check is enabled.

Bit 1 - Enable I/O Range Check

0 - I/O Range Check is disabled. 1 - I/O Range Check is enabled. (I/O Range Check is valid only when the logical

device is inactive).

Bits 7-2 - Reserved

These bits are reserved and return 0 on reads.

Index Name Deﬁnition

60h I/O Port Base

Address Bits (15-8)

Descriptor 0

Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O descriptor 0.

61h I/O Port Base

Address Bits (7-0)

Descriptor 0

Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O descriptor 0.

62h I/O Port Base

Address Bits (15-8)

Descriptor 1

Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O descriptor 1.

63h I/O Port Base

Address Bits (7-0)

Descriptor 1

Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O descriptor 1.

Configuration

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TABLE 2-8. PnP Interrupt Conﬁguration Registers

TABLE 2-9. PnP DMA Conﬁguration Registers

TABLE 2-10. PnP Logical Device Conﬁguration Registers

Index Name Deﬁnition

70h Interrupt Request

Level Select 0

Read/write value indicating selected interrupt level. Bits3-0 select the interrupt level used for interrupt 0. A value of 1 selects IRQL 1, a value

of 15 selects IRQL 15. IRQL 0 is not a valid interrupt selection and (represents no interrupt selection.

71h Interrupt Request

Type Select 0

Read/write value that indicates the type and level of the interrupt request level selected in the previous register.

If a card supports only one type of interrupt, this register may be read-only. Bit 0 - Type of the interrupt request selected in the previous register.

0 - Edge 1 - Level

Bit1 - Level of the interrupt request selected in the previous register. (see also “IRQ Mapping” on page 181).

0 - Low polarity (implies open-drain output with strong pull-up for a short time, followed

by weak pull-up).

1 - High polarity (implies push-pull output).

Index Name Deﬁnition

74h DMA Channel

Select 0

Read/write value indicating selected DMA channel for DMA 0. Bits 2-0 select the DMA channel for DMA 0. A value of 0 selects DMA channel 0; a

value of 7 selects DMA channel 7. Selecting DMA channel 4, the cascade channel, indicates that no DMA channel is

active.

75h DMA Channel

Select 1

Read/write value indicating selected DMA channel for DMA 1 Bits 2-0 select the DMA channel for DMA 1. A value of 0 selects DMA channel 0; a

value of 7 selects DMA channel 7. Selecting DMA channel 4, the cascade channel, indicates that no DMA channel is

active.

Index Name Deﬁnition

F0h-FEh Logical Device

Conﬁguration

Vendor Deﬁned

Vendor deﬁned.

Configuration

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2.3.2 Configuration Register Summary

The tables in this section specify the Index, type (read/write), reset value and configuration register or action that controls each register associated with each function. When the reset value is not fixed, the table indicates what controls the value or points to another section that provides this information.

Soft Reset is related to a Reset executed by utilizing the Reset Bit (Bit 0) of the Config Control Register. (See Table 2-5 on page 27.)

TABLE 2-11. Card Conﬁguration Registers

TABLE 2-12. KBC Conﬁguration Registers for Keyboard - Logical Device 0

Index Type Hard Reset Soft Reset Conﬁguration Register or Action

00h W 00h PnP ISA Set RD_DATA Port. 01h R Serial Isolation. 02h W PnP ISA PnP ISA Conﬁguration Control. 03h W 00h PnP ISA Wake[CSN]. 04h R Resource Data. 05h R Status. 06h R/W 00h PnP ISA Card Select Number (CSN). 07h R/W 00h PnP ISA Logical Device Number. 20h R

See section 2.4.1 and 2.4.2 on page 34.

SID Register.

21h R/W

See Section 2.4.3 on page 34.

No Effect SuperI/O Conﬁguration 1 Register.

22h R/W

See Section 2.4.4 on page 35.

No Effect SuperI/O Conﬁguration 2 Register.

23h R/W

See Section 2.4.5 on page 35.

No Effect Programmable Chip Select Conﬁguration Index Register.

24h R/W

See Section 2.4.6 on page 36.

No Effect Programmable Chip Select Conﬁguration Data Register.

27h R

See Section 2.4.7 on page 36.

SRID Register (in pc97307 only).

Index R/W Hard Reset Soft Reset Conﬁguration Register or Action

30h R/W 00h or 01h

See CFG0, Section 2.1.3.

00h or 01h

See CFG0,Section

2.1.3.

Activate. See also FER1 of power management device

(logical device 8). 31h R/W 00h 00h I/O Range Check. 60h R/W 00h 00h Data Base Address MSB Register. 61h R/W 60h 60h Data Base Address LSB Register.

Bit 2 (for A2) is read only, 0. 62h R/W 00h 00h Command Base Address MSB Register. 63h R/W 64 64h Command Base Address LSB.

Bit 2 (for A2) is read only,1. 70h R/W 01h 01h KBC Interrupt (KBC IRQ1 pin) Select. 71h RW 02h 02h KBC Interrupt Type.

Bits 1,0 are read/write; other bits, read only. 74h R 04h 04h Report no DMA assignment. 75h R 04h 04h Report no DMA assignment.

F0h R/W

See Section 2.5.1 on page 36.

No Effect SuperI/O KBC Conﬁguration Register.

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