NSC PC87570-ICC-VPC Datasheet

1

- January 1998

Highlights

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©

1998 National Semiconductor Corporation

PRELIMINARY

April 1998

PC87570 Keyboard and Power Management Controller

Highlights

General Description

The PC87570 is a highly integrated embedded RISC-based
controller optimized for power management (PM), keyboard
and mouse (KBC) and system control in portable Personal
Computer (PC) applications.

The PC87570 incorporates National’s CompactRISC
CR16A core, a high performance 16-bit RISC processor
core, a Bus Interface Unit (BIU) that directly interfaces with
memory and I/O devices, on-chip memory and system sup­port functions. Among these are legacy functions, handled
by the Host Bus Interface (HBI), that include the Real-Time
Clock and Advanced Power Control (RTC and APC), and
peripherals, including: frequency-multiplier-based High Fre­quency Clock Generator (HFCG), Power Mode Control
(PMC), Interrupt Control Unit (ICU), Multi-Input Wake-Up
(MIWU), General Purpose I/O Ports (GPIO) with internal
keyboard matrix scanning, PS/2

®

Interface, ACCESS.bus

®

(ACB) Interface, two Multi-Function 16-Bit Timers (MFT16),
periodic interrupt timer and WATCHDOG (TWD), ADC
and DAC.

The PC87570 highly efficient architecture and its on-chip
peripherals, supporting functions and low power consump­tion, provide a highly integrated solution for portable note­book PCs, sub-notebook PCs and other portable devices.

Outstanding Features

●

Shared BIOS memory

●

Fully ACPI-compliant embedded controller

●

Proprietary PS/2 shift mechanism

●

Extremely low current consumption in Idle mode

●

Support for a variety of off-chip wake-up sources

●

Scalable design for growth without controller upgrade

Block Diagram

Core Bus

Peripheral Bus

Bus

KBC + PM

Host I/F

RTC +

Processing

Unit

HBI

Host Bus

APC

Host

Config

RAM

Memory

External

BIU

CR16A Core

32.768

ICU

HFCG

PMC

ADC

KBSCAN

ACB

GPIO

WDG

Peripherals

Legacy

ROM

MIWU

IBM®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.

CompactRISC

TM

, WATCHDOGTM and TRI-STATE® are trademarks of National Semiconductor Corporation.

ACCESS.bus® is a registered trademark of Digital Equipment Corporation.

I

2C®

is a registered trademark of Philips.

Memory

(ISA Compatible)

MFT16

Timer +

KHz

Adapter

PS/2

I/F

I/F

CLK

DAC

+ I/O

(X2)

2

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Features

• CR16A Core

— 16-bit embedded RISC processor core

• Bus Interface Unit (BIU)

— Three address zones for static devices (SRAM,

ROM FLASH, I/O)

— Configurable wait states and fast read bus cycles

• Internal Memory

— 2048 bytes of on-chip ROM
— 1024 bytes of on-chip RAM
— All memories can hold both code and data

• External Memory

— Supports BIOS memory (Flash) sharing with PC host
— Up to 56 Kbyte for code and data
— Field upgradable with Flash or SRAM devices
— Supports host controlled code download and update

• Host Bus Interface (HBI)

— Three host interface channels, typically used for the

KBC, PM and RTC devices

— Motherboard Plug and Play (PnP) configuration

o With Enable and Lock bits for each device
o Relocatable address for each device

— Host power supply indicator input pin
— 8042 KBC standard Interface (60h, 64h)
— Intel 80C51SL compatible
— IRQ1 and IRQ12 support
— Fast Gate A20 and Fast host Reset, via firmware
— PM interface port (62h, 66h)
— PM port IRQ11

• Real-Time Clock (RTC) and Advanced Power Control

(APC)
— RTC

o DS1287, MC146818 and PC87911 compatible
o 242 bytes battery backed-up CMOS RAM
o Calendar including century and automatic leap-

year adjustment

o Optional daylight saving adjustment
o BCD or binary format for timekeeping
o Three individually maskable interrupt event

flags: periodic rates from 122 µs to 500 ms; time­of-day alarm, once per second to once per day

o Separate backup battery pin
o Double buffer time registers
o The CMOS RAM and the RTC registers can be

accessed by the CR16A firmware

— APC

o Alarm wake-up
o Hardware wake-up events
o Software off events

• HFCG

— On-chip frequency multiplier
— Single 32.786KHz crystal
— Software controlled frequency generation

• PMC

— 3.3 and 5V operation with mixed voltage system

support

— Reduced power consumption capability
— Back-drive protection
— Three power modes, switched by software or hard-

ware:

o Active mode operating frequency 4-10MHz
o Idle (20 µA)
o Power Off - RTC only (0.9 µA typical) from back-

up battery

— Automatic wake-up on system events

• ICU

— 16 maskable interrupt sources
— Four general purpose external interrupt inputs
— Programmable trigger mode (level: high or low,

edge: falling or rising)

— Enable and pending indication for each interrupt
— Non-maskable interrupt input

• MIWU

— Supports up to 24 wake-up or interrupt inputs
— Generates wake-up to PMC
— Generates interrupts to ICU
— Provides user-selectable trigger conditions

• GPIO

— 76 ports
— I/O pins individually configured as input or output
— Configurable internal pull-up resistors
— Special ports for internal keyboard matrix scanning

o 16 open-collector outputs
o 8 Schmidt inputs with internal pull-up

— Special input for system On/Off switch
— Supports very low-cost implementation of additional

off-chip I/O ports

• PS/2 Interface

— Supports three independent devices (external KBC,

mouse and additional pointing device)

— Supports byte lev el handling via hardware accelerator

• ACB Interface

— Intel SMBus and Philips I

2C®

compatible

— ACCESS.bus master and slave
— Supports polling and interrupt controlled operation
— Generates a wake-up signal on detection of a Start

Condition, while in power-down mode

— Optional internal pull-up on SDA and SCL pins

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• MFT16

— Two 16-bit timers
— Each timer supports Pulse Width Modulator (PWM),

Capture and Counter capabilities

• TWD

— 16-bit periodic interrupt timer with 30-µs resolution

and 5-bit prescaler, for system tick and periodic
wake-up tasks

— 8-bit WATCHDOG timer

• ADC

— Eight channels, 8-bit resolution

— 10 µs conversion/channel
— Internal or external voltage reference

• DAC

— Four channels, 8-bit resolution
— 1 µs conversion time for 50 pF load
— Full output range from AGND to AVCC

• Supports Microsoft Advanced Power Management

(APM) specifications revision 1.2, February 1996
— Generates the System Management Interrupt (SMI)

• 160-pin PQFP and 176-pin TQFP packages

Basic Configuration

or

Clock

External
Memory

PC87570

Host System Bus (ISA Compatible)

32KX1/32KCLKIN
32KX2

HMR

HA18-0

HD7-0

HIOR
HIOW

IRQ1

IRQ11
IRQ12

RD

WR1-0

SEL0

A18-16, A15-0

D15-8

AD7-0

DA3-0

PA6-0
PB7-0
PC7-0
PD7-0

HIOCHRDY

RTC

Battery

V

BAT

IRQ8

PSCLK1

PSDAT1

Crystal

32.768 KHz

External Keyboard

Internal

Keyboard

KBSOUT15-0

KBSIN7-0

SRAM or

Flash

ENV0

GA20

AVCC
AGND

VCC

GND

Power
Supply

SCL

D7-0

HMEMRD
HMEMWR

PSCLK2

PSDAT2

PSCLK3

PSDAT3

PG4-0

PE1-0

PF7-0

PH5-0

HMEMCS

HAEN

EXINT0,10,11,15

PFAIL

RING

SHBM
HRMS

Configuration

Inputs

I/O

Expansion

TA

HDEN
TRIS

HPWRON

PC0

External Mouse

Auxiliary PS/2

Interface

Interface

Interface

HRSTO

SELIO

(Matrix)

SDA

TB

SWIN

Analog

Reset

Control

(power-up reset)

GPIO

Interrupt

ACCESS.bus

System

Timers

ENV1

NC
NC

SEL1

NC

(Application)

V

REF

ADC
DAC

4

Table of Contents

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Table of Contents

Highlights.......................................................................................................................................................1

1.0 Introduction

1.1 INTERNAL ARCHITECTURE ....................................................................................................14

1.1.1 Processing Unit ...........................................................................................................14

1.1.2 BIU ...............................................................................................................................14

1.1.3 Memory ........................................................................................................................14

1.1.4 HBI ...............................................................................................................................14

1.1.5 Peripherals ..................................................................................................................14

1.2 EXPANSION OPTIONS .............................................................................................................15

1.3 OPERATING ENVIRONMENTS ................................................................................................15

1.3.1 IRE Environment .........................................................................................................16

1.3.2 IRD Environment .........................................................................................................17

1.3.3 DEV Environment ........................................................................................................18

2.0 Signal/Pin Connection and Description

2.1 CONNECTION DIAGRAMS ......................................................................................................19

2.2 SIGNAL/PIN DESCRIPTIONS ...................................................................................................21

2.3 RESET SOURCES AND TYPES ...............................................................................................26

2.3.1 Power-Up Reset ..........................................................................................................26

2.3.2 Warm Reset .................................................................................................................26

2.3.3 WATCHDOG Reset .....................................................................................................26

2.3.4 Triggering Reset ..........................................................................................................26

2.4 STRAP PINS ............................................................................................................................26

2.4.1 Setting the Environment ..............................................................................................26

2.4.2 Other Strap Pin Settings ..............................................................................................26

2.4.3 System Load on Strap Pins .........................................................................................27

2.4.4 Strap Inputs During Idle Mode .....................................................................................27

2.4.5 Strap Pin Status Register (STRPST) ...........................................................................27

2.5 ALTERNATE FUNCTIONS ........................................................................................................27

2.6 SYSTEM CONFIGURATION REGISTERS ...............................................................................29

2.6.1 Module Configuration Register (MCFG) ......................................................................29

2.6.2 PAGE Register ............................................................................................................30

2.7 SHARED MEMORY CONFIGURATION ...................................................................................30

2.8 MEMORY MAP ..........................................................................................................................30

2.8.1 Accessing Base Memory .............................................................................................31

2.8.2 Accessing External Memory ........................................................................................32

2.8.3 Accessing I/O Expansion Space .................................................................................33

3.0 Bus Interface Unit (BIU)

3.1 FEATURES ................................................................................................................................34

3.2 FUNCTIONAL DESCRIPTION ..................................................................................................34

3.2.1 Interfacing ....................................................................................................................34

3.2.2 Static Memory and I/O Support ...................................................................................34

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3.2.3 Byte Accessing ............................................................................................................34

3.3 CLOCK AND BUS CYCLES ......................................................................................................34

3.3.1 Clock Cycles ................................................................................................................34

3.3.2 Control Signals ............................................................................................................35

3.3.3 Early Write Bus Cycle ..................................................................................................36

3.3.4 Late Write Bus Cycle ...................................................................................................38

3.3.5 Normal Read Bus Cycle ..............................................................................................40

3.3.6 Fast Read Bus Cycle ...................................................................................................42

3.3.7 I/O Expansion Bus Cycles ...........................................................................................43

3.3.8 I/O Expansion Example ...............................................................................................44

3.4 DEVELOPMENT SUPPORT .....................................................................................................44

3.4.1 Bus Status Signals ......................................................................................................44

3.4.2 Core Bus Monitoring ....................................................................................................44

3.5 BIU REGISTERS .......................................................................................................................45

3.5.1 BIU Configuration Register (BCFG) ............................................................................45

3.5.2 I/O Zone Configuration Register (IOCFG) ...................................................................45

3.5.3 Static Zone Configuration Register (SZCFGn) ............................................................45

3.6 USAGE HINTS ..........................................................................................................................46

4.0 On-Chip Memory

4.1 INTERNAL RAM ........................................................................................................................47

4.2 INTERNAL ROM ........................................................................................................................47

4.2.1 Access Times ..............................................................................................................47

4.2.2 ROM Shadow ..............................................................................................................47

5.0 Host Bus Interface (HBI)

5.1 FEATURES ................................................................................................................................48

5.2 HOST ACCESS TO SHARED MEMORY DEVICE ...................................................................49

5.2.1 Enabling Shared Memory Mode ..................................................................................49

5.2.2 Memory Device Interface .............................................................................................49

5.2.3 Host Access to Shared Memory ..................................................................................49

5.3 CORE ACCESS TO RTC/APC ..................................................................................................49

5.3.1 Host and CR16A Arbitration over RTC/APC ...............................................................49

5.4 USAGE HINTS ..........................................................................................................................49

5.4.1 Shared Memory ...........................................................................................................49

5.4.2 Wake-Up from Host .....................................................................................................50

5.4.3 Host Power-on Indication ............................................................................................50

5.5 HOST ACCESS TO PC87570 RESIDENT I/O DEVICES .........................................................50

5.5.1 Host Access to Configuration Registers ......................................................................50

5.5.2 Host Access to Resident I/O Devices ..........................................................................50

5.5.3 Host Bus I/O Cycles ....................................................................................................50

5.6 KBC CHANNEL .........................................................................................................................50

5.6.1 Status Register ............................................................................................................50

5.6.2 DBBOUT Register .......................................................................................................51

5.6.3 DBBIN Register ...........................................................................................................51

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5.7 PM CHANNEL ...........................................................................................................................52

5.8 RTC/APC CHANNEL .................................................................................................................52

5.9 CR16A INTERRUPTS ...............................................................................................................52

5.10 HOST INTERRUPTS .................................................................................................................52

5.10.1 IRQ1, IRQ12 and IRQ11 and IRQ8 Buffers .................................................................53

5.11 SYSTEM CONSIDERATIONS ...................................................................................................53

5.11.1 Reset Configuration .....................................................................................................53

5.11.2 Host Power-On (HPWRON) Indication Input ...............................................................53

5.11.3 Host Master Reset (HMR) Input ..................................................................................53

5.11.4 Host Reset Output (HRSTO) from PC87570 ...............................................................53

5.11.5 HDEN Strap .................................................................................................................54

5.11.6 GA20 Pin Functionality ................................................................................................54

5.11.7 Host Driven Wake-Up ..................................................................................................54

5.11.8 APC-ON and APC-OFF Events ...................................................................................54

5.12 HBI REGISTERS ACCESSED BY CR16A ................................................................................54

5.12.1 Control and Status Register 1 (CST1) .........................................................................55

5.12.2 Control and Status Register 2 (CST2) .........................................................................55

5.12.3 RTC Core Address Register (RTCCA) ........................................................................55

5.12.4 RTC Core Data Register (RTCCD) .............................................................................56

5.12.5 Host PnP Initial Configuration Base Address Low and High Registers (HCFGBAL/H) 56

5.12.6 Host Interface Control Register (HICTRL) ...................................................................56

5.12.7 Host Interface IRQ Control Register (HIIRQC) ............................................................56

5.12.8 Host Interface KBC Status Register (HIKMST) ...........................................................57

5.12.9 Host Interface Keyboard Data Out Buffer Register (HIKDO) .......................................57

5.12.10 Host Interface Mouse Data Out Buffer Register (HIMDO) ...........................................58

5.12.11 Host Interface KBC Data In Buffer Register (HIKMDI) ................................................58

5.12.12 Host Interface PM Port Status Register (HIPMST) ......................................................58

5.12.13 Host Interface PM Data Out Buffer Register (HIPMDO) ..............................................58

5.12.14 Host Interface PM Data In Buffer Register (HIPMDI) ..................................................58

5.13 HOST CHANNEL CONFIGURATION .......................................................................................58

5.13.1 Chip Base Address Initial Setting ................................................................................58

5.13.2 Operation Guidelines ...................................................................................................60

5.14 HBI REGISTERS ACCESSED BY HOST .................................................................................61

5.14.1 Identification Register (SID) .........................................................................................61

5.14.2 Identification Type Register (SIDT) .............................................................................61

5.14.3 Identification Revision Register (SIDR) .......................................................................61

5.14.4 Base Address High Register (SBAH) ..........................................................................61

5.14.5 Base Address Low Register (SBAL) ............................................................................61

5.14.6 RTC Chip Select Address High Register (RTCCSAH) ................................................61

5.14.7 RTC Chip Select Address Low Register (RTCCSAL) .................................................61

5.14.8 KBC Chip Select Address High Register (KBCCSAH) ................................................62

5.14.9 KBC Chip Select Address Low Register (KBCCSAL) .................................................62

5.14.10 PM Chip Select Address High Register (PMCSAH) ....................................................62

5.14.11 PM Chip Select Address Low Register (PMCSAL) .....................................................62

5.14.12 Function Enable Register (FER) ..................................................................................62

5.14.13 Function Lock Register (FLR) ......................................................................................63

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5.14.14 IRQ Enable Register (IRQE) .......................................................................................63

6.0 Real-Time Clock (RTC) and Advanced Power Control (APC)

6.1 FEATURES ................................................................................................................................64

6.2 RTC FUNCTIONAL DESCRIPTION ..........................................................................................64

6.2.1 Host Bus Interface .......................................................................................................64

6.2.2 Core Bus Interface .......................................................................................................64

6.2.3 Bank Description .........................................................................................................64

6.2.4 Bank Accessing ...........................................................................................................64

6.2.5 RTC Clock Generation ................................................................................................64

6.2.6 Internal Oscillator .........................................................................................................65

6.2.7 External Oscillator .......................................................................................................65

6.2.8 Timing Generation .......................................................................................................65

6.2.9 Timekeeping ................................................................................................................66

6.2.10 Updating ......................................................................................................................66

6.2.11 Alarms .........................................................................................................................67

6.2.12 Power Supply ..............................................................................................................67

6.2.13 System Bus Lockout ....................................................................................................68

6.2.14 Power-Up Detection ....................................................................................................68

6.2.15 Oscillator Activity .........................................................................................................68

6.2.16 Interrupt Handling ........................................................................................................68

6.2.17 Battery-Backed Register Banks and RAM ...................................................................68

6.3 RTC REGISTERS ......................................................................................................................69

6.3.1 RTC Control Register A (CRA) ....................................................................................69

6.3.2 RTC Control Register B (CRB) ....................................................................................70

6.3.3 RTC Control Register C (CRC) ...................................................................................70

6.3.4 RTC Control Register D (CRD) ...................................................................................71

6.4 USAGE HINTS ..........................................................................................................................71

6.5 APC FUNCTIONAL DESCRIPTION ..........................................................................................71

6.5.1 Operation .....................................................................................................................71

6.5.2 User Selectable Parameters ........................................................................................71

6.5.3 System Power States ..................................................................................................71

6.5.4 System Power Switching Logic ...................................................................................72

6.5.5 APC-ON/APC-OFF Interrupt Signals ...........................................................................72

6.5.6 Entering Power States .................................................................................................72

6.5.7 Predetermined Wake-Up .............................................................................................72

6.5.8 Ring Signal Event ........................................................................................................72

6.6 APC REGISTERS ......................................................................................................................72

6.6.1 APC Control Register 1 (APCR1) ................................................................................73

6.6.2 APC Control Register 2 (APCR2) ................................................................................73

6.6.3 APC Status Register (APSR) ......................................................................................73

6.6.4 RAM Lock Register (RLR) ...........................................................................................73

6.7 REGISTER BANKS ...................................................................................................................74

7.0 High Frequency Clock Generator (HFCG)

7.1 FEATURES ................................................................................................................................76

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7.2 FUNCTIONAL DESCRIPTION ..................................................................................................76

7.2.1 Setting Clock Frequency .............................................................................................76

7.2.2 Fast Clock Setting .......................................................................................................77

7.3 HFCG REGISTERS ...................................................................................................................77

7.3.1 HFCG Control Register (HFCGCTRL) ........................................................................77

7.3.2 HFCGM Low Value Register (HFCGML) .....................................................................77

7.3.3 HFCGM High Value Register (HFCGMH) ...................................................................77

7.3.4 HFCGN Value Register (HFCGN) ...............................................................................77

7.3.5 HFCGI Low Value Register (HFCGIL) .........................................................................78

7.3.6 HFCGI High Value Register (HFCGIH) .......................................................................78

8.0 Power Mode Control (PMC)

8.1 FEATURES ................................................................................................................................79

8.2 THE POWER MODES ...............................................................................................................79

8.3 SWITCHING BETWEEN POWER MODES ...............................................................................79

8.3.1 Decreasing Power Consumption .................................................................................79

8.3.2 Increasing Performance ..............................................................................................79

8.4 POWER MODE CONTROL REGISTER (PMCR) .....................................................................80

8.5 USAGE HINTS ..........................................................................................................................80

9.0 Interrupt Control Unit (ICU)

9.1 FEATURES ................................................................................................................................81

9.2 FUNCTIONAL DESCRIPTION ..................................................................................................81

9.2.1 NMI ..............................................................................................................................81

9.2.2 Maskable Interrupts .....................................................................................................81

9.2.3 Edge/Level and Polarity Selection ...............................................................................81

9.2.4 Pending Interrupts .......................................................................................................81

9.2.5 External Interrupt Inputs ..............................................................................................81

9.2.6 Interrupt Assignment ...................................................................................................81

9.3 ICU REGISTERS .......................................................................................................................82

9.3.1 NMI Status Register (NMISTAT) .................................................................................82

9.3.2 Power Fail Control Register (PFAIL) ...........................................................................82

9.3.3 Interrupt Vector Register (IVCT) ..................................................................................83

9.3.4 Interrupt Enable and Mask Register (IENAM) .............................................................83

9.3.5 Interrupt Pending Register (IPEND) ............................................................................83

9.3.6 Edge Interrupt Clear Register (IECLR) ........................................................................83

9.3.7 Edge/Level Trigger Configuration Register (IELTG) ....................................................83

9.3.8 Trigger Polarity Configuration Register (ITRPL) ..........................................................83

9.4 USAGE HINTS ..........................................................................................................................83

9.4.1 Initializing .....................................................................................................................83

9.4.2 Clearing .......................................................................................................................83

9.4.3 Nesting ........................................................................................................................83

10.0 Multi-Input Wake-Up (MIWU)

10.1 FEATURES ................................................................................................................................84

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10.2 FUNCTIONAL DESCRIPTION ..................................................................................................84

10.2.1 Trigger Conditions .......................................................................................................86

10.2.2 Pending Flags ..............................................................................................................86

10.2.3 Input Enable ................................................................................................................86

10.2.4 Interrupts .....................................................................................................................86

10.2.5 Input Assignments .......................................................................................................86

10.3 MIWU REGISTERS ...................................................................................................................86

10.3.1 Edge Detection Register 1(WKEDG1) .........................................................................86

10.3.2 Edge Detection Register 2 (WKEDG2) ........................................................................86

10.3.3 Edge Detection Register 3 (WKEDG3) ........................................................................86

10.3.4 Pending Register 1 (WKPND1) ...................................................................................86

10.3.5 Pending Register 2 (WKPND2) ...................................................................................86

10.3.6 Pending Register 3 (WKPND3) ...................................................................................87

10.3.7 Wake-Up Enable Register 1 (WKEN1) ........................................................................87

10.3.8 Wake-Up Enable Register 2 (WKEN2) ........................................................................87

10.3.9 Wake-Up Enable Register 3 (WKEN3) ........................................................................87

10.3.10 Pending Clear Register 1 (WKPCL1) ..........................................................................87

10.3.11 Pending Clear Register 2 (WKPCL2) ..........................................................................87

10.3.12 Pending Clear Register 3 (WKPCL3) ..........................................................................87

10.4 USAGE HINTS ..........................................................................................................................87

11.0 General Purpose I/O (GPIO) Ports

11.1 FEATURES ................................................................................................................................88

11.2 FUNCTIONAL DESCRIPTION ..................................................................................................88

11.2.1 Output Buffer ...............................................................................................................88

11.2.2 Input Buffer ..................................................................................................................88

11.2.3 Open Drain ..................................................................................................................88

11.2.4 Weak Pull-Up ...............................................................................................................88

11.3 GPIO PORT REGISTERS .........................................................................................................89

11.3.1 Port Alternate Function Register (PxALT) ...................................................................89

11.3.2 Port Direction Register (PxDIR) ...................................................................................89

11.3.3 Port Data Out Register (PxDOUT) ..............................................................................89

11.3.4 Port Data In Register (PxDIN) .....................................................................................89

11.3.5 Port Weak Pull-up Register (PxWPU) .........................................................................89

12.0 PS/2 Interface

12.1 FEATURES ................................................................................................................................90

12.2 FUNCTIONAL DESCRIPTION ..................................................................................................90

12.2.1 Configuration ...............................................................................................................90

12.2.2 Shift Mechanism ..........................................................................................................90

12.2.3 Quasi-Bidirectional Drivers ..........................................................................................90

12.2.4 Interrupt Signals ..........................................................................................................91

12.2.5 Power Modes ...............................................................................................................91

12.3 SHIFT MECHANISM ENABLED ................................................................................................91

12.3.1 Reset ...........................................................................................................................91

12.3.2 Enable .........................................................................................................................91

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12.3.3 General PS/2 Interface Operation ...............................................................................91

12.3.4 Transmit Mode .............................................................................................................93

12.4 SHIFT MECHANISM DISABLED ...............................................................................................94

12.4.1 Clock Signal Control ....................................................................................................94

12.4.2 Data Signal Control .....................................................................................................94

12.4.3 Interrupt Generation ....................................................................................................94

12.5 PS/2 INTERFACE REGISTERS ................................................................................................95

12.5.1 PS/2 Data Register (PSDAT) ......................................................................................95

12.5.2 PS/2 Status Register (PSTAT) ....................................................................................95

12.5.3 PS/2 Control Register (PSCON) ..................................................................................95

12.5.4 PS/2 Output Signal Register (PSOSIG) ......................................................................96

12.5.5 PS/2 Input Signal Register (PSISIG) ...........................................................................96

12.5.6 PS/2 Interrupt Enable Register (PSIEN) ......................................................................96

13.0 ACCESS.bus (ACB) Interface

13.1 FEATURES ................................................................................................................................98

13.2 ACB PROTOCOL OVERVIEW ..................................................................................................98

13.2.1 ACB Interface ..............................................................................................................98

13.2.2 Data Transactions .......................................................................................................98

13.2.3 Start and Stop ..............................................................................................................98

13.2.4 Acknowledge Cycle .....................................................................................................98

13.2.5 “Acknowledge after every byte” Rule ...........................................................................99

13.2.6 Addressing Transfer Formats ....................................................................................100

13.2.7 Arbitration on the Bus ................................................................................................100

13.3 FUNCTIONAL DESCRIPTION ................................................................................................100

13.3.1 Master Mode ..............................................................................................................100

13.3.2 Slave Mode ................................................................................................................101

13.3.3 Power-Down ..............................................................................................................102

13.3.4 SDA and SCL Pin Configuration ................................................................................102

13.3.5 ACB Clock Frequency Configuration .........................................................................102

13.4 ACB REGISTERS ....................................................................................................................102

13.4.1 ACB Serial Data Register (ACBSDA) ........................................................................102

13.4.2 ACB Status Register (ACBST) ..................................................................................102

13.4.3 ACB Control Status Register (ACBCST) ...................................................................103

13.4.4 ACB Control Register 1 (ACBCTL) ............................................................................104

13.4.5 ACB Own Address Register (ACBADDR) .................................................................104

13.4.6 ACB Control Register 2 (ACBCTL2) ..........................................................................104

13.5 USAGE HINTS ........................................................................................................................105

14.0 Multi-Function 16-Bit Timer (MFT16)

14.1 FEATURES ..............................................................................................................................106

14.2 FUNCTIONAL DESCRIPTION ................................................................................................106

14.3 CLOCK SOURCE UNIT ...........................................................................................................107

14.3.1 Prescaler ...................................................................................................................107

14.3.2 External Event Clock .................................................................................................107

14.3.3 Pulse Accumulate Mode ............................................................................................107

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14.3.4 Slow Speed Clock .....................................................................................................107

14.3.5 Counter Clock Source Select ....................................................................................108

14.4 TIMER/COUNTER AND ACTION UNIT ..................................................................................108

14.4.1 Operation Modes .......................................................................................................108

14.4.2 Timer Interrupts .........................................................................................................113

14.4.3 Timer I/O Functions ...................................................................................................113

14.5 MFT16 REGISTERS ................................................................................................................114

14.5.1 Clock Prescaler Register (TPRSC) ...........................................................................114

14.5.2 Clock Unit Control Register (TCKC) ..........................................................................114

14.5.3 Timer/Counter Register 1 (TCNT1) ...........................................................................114

14.5.4 Timer/Counter Register 2 (TCNT2) ...........................................................................114

14.5.5 Reload/Capture Register A(TCRA) ...........................................................................114

14.5.6 Reload/Capture Register B (TCRB) ..........................................................................114

14.5.7 Timer Mode Control Register (TCTRL) .....................................................................114

14.5.8 Timer Interrupt Control Register (TICTL) ...................................................................115

14.5.9 Timer Interrupt Clear Register (TICLR) .....................................................................115

15.0 Timer and WATCHDOG (TWD)

15.1 FEATURES ..............................................................................................................................116

15.2 FUNCTIONAL DESCRIPTION ................................................................................................116

15.2.1 Input Clock .................................................................................................................116

15.2.2 Pre-Scale ...................................................................................................................116

15.2.3 TWD Timer 0 .............................................................................................................116

15.3 WATCHDOG OPERATION ....................................................................................................117

15.4 TWD CONTROL AND CONFIGURATION ..............................................................................117

15.5 OPERATION IN IDLE MODE ..................................................................................................117

15.6 TWD REGISTERS ...................................................................................................................117

15.6.1 Timer and WATCHDOG Configuration Registers (TWCFG) .....................................117

15.6.2 Timer and Watchdog Clock Pre-Scaler Register (TWCP) .........................................117

15.6.3 TWD Timer 0 Register (TWDT0) ...............................................................................118

15.6.4 TWDT0 Control and Status Register (T0CSR) ..........................................................118

15.6.5 WATCHDOG Count Register (WDCNT) ...................................................................118

15.6.6 WATCHDOG Service Data Match Register (WDSDM) .............................................118

15.7 USAGE HINTS ........................................................................................................................118

16.0 Analog to Digital Converter (ADC)

16.1 FEATURES ..............................................................................................................................119

16.2 FUNCTIONAL DESCRIPTION ................................................................................................119

16.2.1 Reset .........................................................................................................................120

16.2.2 Reference Voltage .....................................................................................................120

16.2.3 Input Signal Range ....................................................................................................120

16.2.4 ADC Clock .................................................................................................................120

16.2.5 Initializing and Enabling the ADC ..............................................................................120

16.2.6 ADC Operation ..........................................................................................................121

16.2.7 Disabling the ADC to Save Power .............................................................................121

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16.2.8 Sampling Time ...........................................................................................................121

16.2.9 Polling Driven Operation ............................................................................................121

16.2.10 Interrupt Driven Operation .........................................................................................121

16.2.11 Overflow ....................................................................................................................121

16.3 OPERATION MODES .............................................................................................................122

16.4 ADC REGISTERS ...................................................................................................................123

16.4.1 ADC Status Register (ADCST) ..................................................................................123

16.4.2 ADC Control Register 1 (ADCCNT1) .........................................................................123

16.4.3 ADC Control Register 2 (ADCCNT2) .........................................................................123

16.4.4 ADC Control Register 3 (ADCCNT3) .........................................................................124

16.4.5 ADC Data Registers ..................................................................................................125

16.5 USAGE HINTS ........................................................................................................................125

16.5.1 Power Supply and Layout Guidelines ........................................................................125

16.5.2 Power Consumption ..................................................................................................125

16.5.3 Filtering the Noise on Input Signals ...........................................................................126

16.5.4 AD0-7 Multiplexing with PD0-7 Port ..........................................................................126

16.5.5 Calculating the Sampling Time ..................................................................................126

17.0 Digital to Analog Converter (DAC)

17.1 FEATURES ..............................................................................................................................127

17.2 FUNCTIONAL DESCRIPTION ................................................................................................127

17.2.1 DAC Reset .................................................................................................................127

17.2.2 Reference Voltage .....................................................................................................127

17.2.3 Output Signal Range .................................................................................................127

17.2.4 Initializing and Enabling the DAC ..............................................................................128

17.2.5 Disabling the DAC .....................................................................................................128

17.2.6 Conversion Start ........................................................................................................128

17.3 DAC REGISTERS ...................................................................................................................128

17.3.1 DAC Control Register (DACCTRL) ............................................................................128

17.3.2 DAC Data Registers ..................................................................................................128

17.4 USAGE HINTS ........................................................................................................................128

17.4.1 Power Supply and Layout Guidelines ........................................................................128

17.4.2 Output Settling Time ..................................................................................................129

17.4.3 Output Voltage Accuracy ...........................................................................................129

17.4.4 Filtering Noise on Output Signals ..............................................................................129

17.4.5 Current Consumption ................................................................................................129

17.4.6 Entering Idle Mode ....................................................................................................129

18.0 Development System Support

18.1 ISE INTERRUPT .....................................................................................................................130

18.2 TRIS STRAP INPUT PIN .........................................................................................................130

18.3 FREEZING EVENTS ...............................................................................................................130

18.3.1 Disabling Maskable Interrupts ...................................................................................130

18.3.2 Freezing the WATCHDOG Counter ..........................................................................130

18.3.3 Disabling Additional Modules ....................................................................................130

18.3.4 Disabling Destructive Reads .....................................................................................130

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18.4 MONITORING ACTIVITY DURING DEVELOPMENT .............................................................130

18.4.1 The Bus Status Signals .............................................................................................130

18.4.2 Transaction Effects on the External Bus ...................................................................130

18.4.3 Pipe Status Signals ...................................................................................................131

18.5 DEVELOPMENT SYSTEM REGISTERS ................................................................................131

18.5.1 Debug Configuration Register (DBGCFG) ................................................................131

18.5.2 Debug Freeze Enable Register (DBGFRZEN) ..........................................................131

19.0 Device Specifications

19.1 POWER AND GROUNDING ...................................................................................................132

19.2 GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................132

19.2.1 Recommended Operating Conditions .......................................................................132

19.2.2 Absolute Maximum Ratings .......................................................................................133

19.2.3 Power Supply Current under Recommended Operating Conditions .........................133

19.3 DC ELECTRICAL CHARACTERISTICS .................................................................................134

19.3.1 Analog .......................................................................................................................134

19.3.2 Digital .........................................................................................................................135

19.4 AC ELECTRICAL CHARACTERISTICS ..................................................................................137

19.4.1 Definitions ..................................................................................................................137

19.4.2 Timing Tables ............................................................................................................138

19.5 TIMING DIAGRAMS ................................................................................................................144

19.5.1 General ......................................................................................................................144

19.5.2 BIU .............................................................................................................................146

19.5.3 GPIO Ports ................................................................................................................149

19.5.4 Host Interface ............................................................................................................150

19.5.5 MFT16 .......................................................................................................................151

19.5.6 ACCESS Bus Interface ..............................................................................................152

19.5.7 Dev Environment Support .........................................................................................153

19.5.8 Interrupts and Wake-up .............................................................................................153

19.5.9 Reset .........................................................................................................................154

19.5.10 Host Power-on ...........................................................................................................154

19.5.11 PS/2 Interface ............................................................................................................155

A. CR16A Register Map
B. Bootloader Description

B.1 OVERVIEW .............................................................................................................................164

B.2 CONFIGURATION BLOCKS ...................................................................................................164

B.2.1 System Configuration Block ......................................................................................164

B.2.2 KBC Header ..............................................................................................................164

B.3 SYSTEM RESOURCES USED BY BOOTLOADER ...............................................................164

B.3.1 GPIO Pins ..................................................................................................................164

B.3.2 On-Chip RAM ............................................................................................................165

B.4 BOOTLOADER PROGRAM OPERATION ..............................................................................165

Introduction

14

1.0 Introduction

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1.0 Introduction

1.1 INTERNAL ARCHITECTURE

The following descriptions are based on the block diagram
in Highlights on page 1.

1.1.1 Processing Unit

The CompactRISC CR16A core is an advanced, general­purpose, 16-bit microprocessor core with a RISC architec­ture. The core is responsible for arithmetic and logic opera­tions and program control. For more details about the core
structure and instruction set, see

CR16A Core Architecture

Specification, Revision 1.1, January 1996.

1.1.2 BIU

The BIU controls access to:

●

on-chip Base Memory (boot-code, ZONE1, mask­ROM)

●

off-chip devices:

— Base Memory (boot-code, ZONE1, Flash or ROM)
— External Memory (application code, ZONE0, Flash

or SRAM)

— I/O Expansion

Each of these memories is associated with a ZONE in the
BIU. The zone configuration registers control access to de­vices connected to it. See Section 3.2 on page 34 for more
details on BIU.

1.1.3 Memory
ROM The on-chip ROM holds the CR16A boot program which

is run by the PC87570 upon reset (internal power-up reset, or
pulse on HMR pin). The 2048 byte on-chip ROM is used for
boot and External Memory update programs.

The boot program verifies that the External Memory exists
and holds a valid code; then, it jumps to execute this code.
If the External Memory does not hold a valid code (for ex­ample, the Flash is wrongly programmed), the boot pro­gram enables the host to download the code via the host
interface channel, and re-program the Flash.

The External Memory holds most of the PC87570 application
programs and constant data. The external memory can be any
kind of memory device since the PC87570 can directly inter­face with Flash, ROM or SRAM devices. This allows upgrad­ing of the PC87570 firmware (keyboard controller code) in the
field.

RAM The 1024 byte on-chip RAM is mostly used for the
storage of program variables and stack. It can store short
programs used upon returning from Idle mode to Active
mode, and is preserved as long as VCC power is applied to
the PC87570. The PC87570 hardware arbitrates Flash us­age by the CR16A firmware and the host processor BIOS
program, when the "shared-memory" configuration is used.
To reduce resource contention when this shared BIOS
Flash scheme is used, the host processor should copy the
Flash contents to the host’s main memory (DRAM) upon
system boot. Flash sharing is based on “cycle stealing” so
both the host processor and the CR16A can execute in par­allel code from the same memory device.

1.1.4 HBI

The Host Bus Interface (HBI) bridges and arbitrates be­tween host and CR16A accesses to shared resources. The
HBI allows the host and CR16A to share Flash memory.
See Section 5.2 on page 49 for more details on the shared
memory system.

The HBI enables host access to the KBD/MOUSE and the PM
interface ports, and to the RTC/APC. It also enables the
CR16A to access the RTC/APC and its CMOS RAM.

The host interface uses an ISA compatible bus protocol.
The PC87570 decodes the 16 ISA address lines to identify
the on-chip I/O device address as defined in the host con­figuration. Shared BIOS memory accesses to the device
are indicated by a memory chip select input from the host
(

HMEMCS signal), and three additional address lines (A16,

A17 and A18).
The Host Interface Configuration allows the host pro-

cessor to configure the interface to the PC87570 I/O devic­es (KBD, PM and RTC/APC host interface channels). The
Host Interface Configuration includes a motherboard Plug­and-Play protocol that allows settings, such as the address
of each device, to be enabled and disabled. It also includes
a locking scheme to allow the BIOS program to protect the
configuration from tampering.

The Host Interface has three channels as follows:

●

Keyboard and Mouse (host addresses 60h, 64h).

●

Power Management (host address 62h, 66h)

●

RTC/APC (host address 70h, 71h).

The Host Interface supports the four legacy (ISA) inter­rupts.The PC87570 can generate interrupt requests to the
host processor via IRQ1, IRQ12, IRQ11 and

IRQ8 for the
Keyboard, Mouse, PM and RTC/APC handlers, respective­ly. This allows the PC87570 to be used with polling or inter­rupt driven schemes.

The PC87570 communicates with a host processor over an
ISA compatible, host interface bus. The KBD, PM and the
RTC/APC are interfaced as I/O devices over the I/O ad­dress space of the host.

In addition, the PC87570 generates the gate A20 control
signal (GA20 pin) and a soft reset signal (

HRSTO pin) to the

host. Optionally, this

HRSTO reset signal can be used to
prevent the host from accessing the shared Flash when the
PC87570 cannot perform the shared memory access dur­ing the PC87570’s boot-up time.

1.1.5 Peripherals
The RTC/APC has a low-power clock that provides time-of-

day, a calendar with century counter and alarm features. It
can work from either V

CC

or a backup battery using an in­ternal switch. Other features include three maskable inter­rupt sources and 242 bytes of general-purpose RAM. An
external battery source maintains valid RAM and time dur­ing V

CC

failure. The RTC is software compatible with the

DS1287 and MC146818.
The APC hardware, with APM 1.2 compatible power con-

trol, features such as alarm wake-up, ring detection and
host control off commands. The APC controls the PC power
supply via the CR16A firmware. This allows maximum flex­ibility in designing an ACPI system based on the PC87570.

Introduction

EXPANSION OPTIONS

15

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The HFCG (High Frequency Clock Generator) provides
clocks for the various on-chip modules. These clocks are
generated directly from a 32.768 KHz crystal or from the on­chip HFCG. The HFCG generates the high-frequency clock
using the RTC’s 32.768 KHz clock signal as a reference.
The PC87570 operation frequency is set by programming
the HFCG registers. The PMC enables and disables high
frequency clock generation, according to the required pow­er mode.

The PMC (Power Mode Control) reduces the PC87570's
power consumption to the required activity level. Power
consumption is adjusted by controlling the clock frequency
and selective enabling/disabling of three power modes: Ac­tive, Idle and Power Off. Activity can be resumed by a peri­odic wake-up or via external events.

The ICU (Interrupt Control Unit) is a sixteen-channel mod­ule that interfaces between the interrupt requests (from dif­ferent on-chip modules and external sources), and the
CR16A core. Both maskable and non-maskable interrupts
are generated.

For maskable interrupts, the ICU controls the masking of
the various sources and prioritizes the different requests. It
generates an interrupt to the core and indicates which of the
sources requested service. For non-maskable interrupts, it
combines the various sources into one and indicates which
is the requested service.

MIWU The Multi-Input Wake-Up module allows the device
to return from Idle mode. The CR16A can enable or disable
the various wake-up conditions. The PC87570 has a total of
23 wake-up signals, some of which are grouped to generate
a single interrupt signal.

GPIO Ports consist of up to 76 GPIO signals that provide
interface and control for the PC system. Some of these I/O
port signals share their pins with an alternate function (see
Table 2-5 on page 27), and may be mutually exclusive.
Some of these signals, when configured as inputs, can in­terrupt the CR16A when an event is detected even if the de­vice is in Idle Mode. An example is the SWIN input, which is
dedicated for the PC’s On/Off switch.

One of the I/O pin can be used as an SMI output to the host
processor. The SMI is generated based on various events
identified by the CR16A. This includes an OFFcommand in­dication from the APC.

Internal keyboard scanning is supported by 16 open-drain
output port signals, and 8 input port signals with Schmidt
trigger input buffer and internal pull-up resistors. For power
efficiency, the inputs include an interrupt and a wake-up ca­pability, so that pressing/releasing keys may be identified
without scanning the keyboard matrix in either Active or Idle
modes. The keyboard interrupt is controlled by the MIWU.

The PS/2 Interface, is an industry-standard, with PS/2­compatible keyboard support, is implemented through a
two-wire, bidirectional TTL interface. Several vendors also
supply PS/2 mouse products and other pointing devices
with the same type of interface.

The PC87570 supports three PS/2 channels. Each channel
has two quasi-bidirectional signals which may be interfaced di­rectly to an external keyboard, mouse or any other PS/2 com­patible pointing device. Since the three channels are identical,
the connector ports are interchangeable.

The PC87570 includes a hardware accelerator that allows
the PS/2 channels to be controlled with minimal software
overhead. It also eliminates the sensitivity to interrupt laten­cy that characterized traditional solutions.

The ACB Interface is a two-wire serial interface compati­ble with the ACCESS.bus physical layer. It is also compati­ble with Intel’s SMBus and Philips’ I

2

C. This module can
serve as a bus master or slave, and performs both transmit
or receive operations.

The MFT16 contains two 16-bit timers with a range of op­eration modes. These timers can operate from several
clock sources in PWM, Capture or Counter mode to satisfy
a wide range of application requirements.

The TWD has a 16-bit periodic interrupt timer that can be
programmed to generate interrupts at pre-defined intervals.
An 8-bit WATCHDOG timer can reset the PC87570 when­ever the software loses control of the processor.

The ADC contains eight analog input channels. Each ADC
channel has a 10 µsec minimum conversion period. Either
an internal or external voltage source may be used as a ref­erence for the A/D conversion.

The DAC has four channels of voltage output. Each of the
four DAC channels has an 8-bit resolution with a full output
range from AGND to AV

CC

. Conversion time is about 1 µsec

on a 50 pF load.

1.2 EXPANSION OPTIONS

The PC87570 system can be expanded cost effectively, as
follows:

●

I/O Expansion permits adding I/O port pins, in addition
to those available on-chip, using low-cost standard
74HC devices.

●

The External Memory may be configured to 8-bit width
to interface with 8-bit Flash/SRAM devices, or it may
be configured to 16-bit width when additional perfor­mance is required.

●

The PC87570 may be configured to interface with 32
Kbyte or 56 Kbyte of External Memory (application).

1.3 OPERATING ENVIRONMENTS

Upon power-up reset, the ENV1-0 pins select one the fol­lowing operating environments:

●

Internal ROM Enabled (IRE)

●

Internal ROM Disabled (IRD)

●

Development (DEV)

See Section 2.4 on page 26 for more information about
these pins and controlling the loads connected to them.

Code written for IRE environment is executable in all environ­ments, since it is binary compatible. The execution time of
code in on-chip Base Memory (the IRE environment) is identi­cal to that in off-chip Base Memory (IRD and DEV environ­ments); i.e., the operation is cycle-by-cycle compatible.

PC87570 devices are tested to ensure that they operate in
either IRE or IRD environment. Only selected parts are test­ed for operation in DEV environment.

Introduction

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OPERATING ENVIRONMENTS

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1.3.1 IRE Environment

In this environment, after reset, (internal power-on reset cir­cuit or an external pulse on HMR pin), the PC87570 starts
running the code written in the internal mask-ROM. This
ROM contains the PC87570’s boot program which is read­only. The boot-code size can be up to 2 Kbytes. After com­pletion of the boot program, the process is handed over to
the External Memory. In the External Memory resides the
user-defined application.

The boot program performs several basic task needed to
start the system in a safe and ordered way. It checks if the
External Memory holds valid code. In case the code is in­valid, it allows the host processor to re-program the Flash
device. See also Section B.1 on page 164.

To maximize on-chip ROM performance, configure the BIU
as described in Section 3.6 on page 46.

The majority of applications use the PC87570 in IRE envi­ronment, which provides up to 10 on-chip I/O ports with a to­tal of 76 GPIO signals. The ports are: PA6-0, PB7-0, PC7­0, PD7-0, PE1-0, PF7-0, PG4-0, PH5-0, KBSIN7-0 and
KBSOUT15-0.

In addition, the PC87570 provides an interface to External
Memory and a variety of system functions, including ADC
and DAC, Timers, Interrupts, PM, ACCESS.bus/SMBus, and
other features (some features are mutually exclusive).

See Figure 1-1 for a system example in IRE environment.
In this environment, the ENV0 and ENV1 strap pins do not
need any external pull-up resistors.

or

Clock

External
Memory

PC87570

Host System Bus (ISA Compatible)

32KX1/32KCLKIN
32KX2

HMR

HA18-0

HD7-0

HIOR
HIOW

IRQ1

IRQ11
IRQ12

RD

WR1-0

SEL0

A18-16, A15-0

D15-8

AD7-0

DA3-0

PA6-0
PB7-0
PC7-0
PD7-0

HIOCHRDY

RTC

Battery

V

BAT

IRQ8

PSCLK1

PSDAT1

Crystal

32.768 KHz

External Keyboard

Internal

Keyboard

KBSOUT15-0

KBSIN7-0

SRAM or

Flash

ENV0

GA20

AVCC

AGND

VCC

GND

Power
Supply

SCL

D7-0

HMEMRD
HMEMWR

PSCLK2

PSDAT2

PSCLK3

PSDAT3

PG4-0

PE1-0

PF7-0

PH5-0

HMEMCS

HAEN

EXINT0,10,11,15

PFAIL

RING

SHBM
HRMS

Configuration

Inputs

I/O

Expansion

TA

HDEN
TRIS

HPWRON

PC0

External Mouse

Auxiliary PS/2

Interface

Interface

Interface

HRSTO

SELIO

(Matrix)

SDA

TB

SWIN

Analog

Reset

Control

(power-up reset)

GPIO

Interrupt

ACCESS.bus

System

Timers

ENV1

NC
NC

Figure 1-1. IRE Environment

SEL1

NC

(Application)

V

REF

ADC
DAC

Introduction

OPERATING ENVIRONMENTS

17

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1.3.2 IRD Environment

IRD environment is used mostly for prototypes and low-vol­ume manufacturing. In this environment, the on-chip Base
Memory (containing the up to 2 KByte boot code), is re­placed by up to 64 Kbytes of off-chip memory, called off­chip Base Memory, which may be ROM or Flash memory.

You can control the number of wait states used to access the
Base Memory to allow interfacing with devices that have a
wide range of access times. Configure this number according
to the operation frequency and voltage, and the device ac­cess time. Since the time required to access off-chip Base

Memory devices affects the performance of the CR16A core,
use the same number of wait states in all environments to
maintain cycle-by-cycle compatibility.

In this environment, the pins of ports PF and PG are allocat­ed for the interface to the Base Memory. The system may
restore these ports using the I/O Expansion protocol and
off-chip logic, while maintaining cycle-by-cycle and binary
compatibility with the IRE environment. All features of IRE
environment can be implemented either directly or by using
additional external logic.

Figure 1-2 illustrates a system in IRD environment.

or

Clock

External
Memory

PC87570

Host System Bus (ISA Compatible)

32KX1/32KCLKIN
32KX2

HMR

HA18-0

HD7-0

HIOR
HIOW

IRQ1

IRQ11
IRQ12

RD

WR1-0

SEL0

A18-16, A15-0

D15-8

AD7-0

DA3-0

PA6-0
PB7-0
PC7-0
PD7-0

HIOCHRDY

RTC

Battery

V

BAT

IRQ8

PSCLK1

PSDAT1

Crystal

32.768 KHz

External Keyboard

Internal

Keyboard

KBSOUT15-0

KBSIN7-0

SRAM or

Flash

ENV0

GA20

AVCC
AGND

VCC

GND

Power
Supply

SCL

D7-0

HMEMRD
HMEMWR

PSCLK2

PSDAT2

PSCLK3

PSDAT3

PG4-0

PE1-0

PF7-0

PH5-0

HMEMCS

HAEN

EXINT0,10,11,15

PFAIL

RING

SHBM
HRMS

Configuration

Inputs

I/O

Expansion

TA

HDEN
TRIS

HPWRON

PC0

External Mouse

Auxiliary PS/2

Interface

Interface

Interface

HRSTO

SELIO

(Matrix)

SDA

TB

SWIN

Analog

Reset

Control

(power-up reset)

GPIO

Interrupt

ACCESS.bus

System

Timers

ENV1

NC

Figure 1-2. IRD Environment

SEL1

(Application)

V

REF

ADC
DAC

Off-chip

Base

(Boot code

ROM)

Memory

16

16

*

Restored

Ports

*

Optional 8/16 data bus

V

CC

R

1

PF
PG

Introduction

18

OPERATING ENVIRONMENTS

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1.3.3 DEV Environment

DEV environment is most commonly used to develop soft­ware on Application Development Boards (ADBs) and In­System Emulators (ISEs). In this environment, the develop­ment tools can load code and data of up to 64 Kbytes to off­chip RAM. This can replace the Base Memory used in
IRE/IRD environment (on-chip/off-chip boot-code). The de­velopment tool can also load code and data of up to 56
Kbytes to off-chip RAM (application).

In this environment, the pins of ports PF, PG and PH are al­located for the interface to the Base Memory, for ISE inter­rupt and for CR16A core status indication. The system may
re-gain these ports using the I/O Expansion protocol and
off-chip logic, while maintaining cycle-by-cycle and binary
compatibility with the IRE environment. Using the same soft­ware, this environment is binary and cycle-by-cycle compati­ble with IRD and IRE environments. All features of IRE
environment can be implemented either directly or by using
additional external logic. Figure 1-3 shows a system in DEV
environment.

or

Clock

External
Memory

PC87570

Host System Bus (ISA Compatible)

32KX1/32KCLKIN
32KX2

HMR

HA18-0

HD7-0

HIOR
HIOW

IRQ1

IRQ11
IRQ12

RD

WR1-0

SEL0

A18-16, A15-0

D15-8

AD7-0

DA3-0

PA6-0
PB7-0
PC7-0
PD7-0

HIOCHRDY

RTC

Battery

V

BAT

IRQ8

PSCLK1

PSDAT1

Crystal

32.768 KHz

External Keyboard

Internal

Keyboard

KBSOUT15-0

KBSIN7-0

SRAM or

Flash

ENV0

GA20

AVCC

AGND

VCC

GND

Power
Supply

SCL

D7-0

HMEMRD
HMEMWR

PSCLK2

PSDAT2

PSCLK3

PSDAT3

PG4-0

PE1-0

PF7-0

PH5-0

HMEMCS

HAEN

EXINT0,10,11,15

PFAIL

RING

SHBM
HRMS

Configuration

Inputs

I/O

Expansion

TA

HDEN
TRIS

HPWRON

PC0

External Mouse

Auxiliary PS/2

Interface

Interface

Interface

HRSTO

SELIO

(Matrix)

SDA

TB

SWIN

Analog

Reset

Control

(power-up reset)

GPIO

Interrupt

ACCESS.bus

System

Timers

ENV1

NC

Figure 1-3. DEV Environment

SEL1

(Application)

V

REF

ADC
DAC

Off-chip

Base

(Boot code

SRAM)

Memory

16

16

*

Restored

Ports

*

Optional 8/16 data bus

V

CC

R

1

PF
PG
PH

CLK

ISE
BST2-0

PFS
PLI

Development

Support

BE1,0
CBRD

Signal/Pin Connection and Description

19

2.0 Signal/Pin Connection and Description

www.national.com

2.0 Signal/Pin Connection and Description

2.1 CONNECTION DIAGRAMS

80

75

70

65

60

55

50

1 5 10 15 20 25 30

859095100

4035

PC87570

105110115120

45

41

81

121

125

130

135

140

145

150

155

160

HD0

HD1

GND

HD2

HD3

HD4

HD5

HD6

HD7

GND

V

BAT

KBSIN7

KBSIN2

KBSIN1

KBSIN3

PH1/BST1/ENV1

PG3/

SEL1

V

CC

SEL0/HRMS

PH2/BST2/TRIS

HIOCHRDY

DA1

GND

PH4/PLI

PH3/PFS

PH5/

ISE

PD6/AD6

PH0/BST0/ENV0

PG2/CLK

DA0

DA3

DA2

PB5(GA20)

AGND

HA9

A6A5A4A3A2

PA2/HMEMWR

HMR

HPWRON

HA0

PB7/SWIN

A8

IRQ12
IRQ11

A14/BE1

A10

A11A7A9

PA6/A17

A13/BE0

PE0/HA18

HRSTO(PB6)

KBSOUT0

HA10

HA11

HA12

HA13

HA14

HA15

PA3/HA16

PA4/HA17

PSDAT1

PC7/PSDAT3

PB0/RING

KBSIN5

KBSIN6

PC6/PSCLK3

PC5/EXINT15

RD/HDEN

PG0/

SELIO

WR0

PG4/WR1

A1

A0

KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4

PC4/EXINT11

PD7/AD7

PF3/D11
PF4/D12

PF1/D9
PF2/D10

PF6/D14

PF5/D13

PF7/D15

PF0/D8

KBSOUT5

KBSIN4

KBSIN0

KBSOUT15

KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9

KBSOUT14

KBSOUT13

KBSOUT12

KBSOUT11

HA1
HA2
HA3
HA4
HA5
HA6
HA7

GND

V

CC

PSDAT2
PSCLK1

PC3/EXINT0
PC2
PC1

PSCLK2

PC0

A12

32KX2

KBSOUT10

PA5/A16

HIOR

HIOW

IRQ1

PA0/HMEMCS

V

CC

GND

PA1/HMEMRD

IRQ8

PG1/A15/CBRD

PE1/A18/SHBM

D0
D1
D2
D3
D4
D5
D6
D7

AV

CC

PD5/AD5
PD4/AD4
PD3/AD3
PD2/AD2
PD1/AD1
PD0/AD0
V

REF

PFAIL

PB3/TA
PB2/SDA
PB1/SCL

PB4/TB/EXINT10

HA8

V

CC

160-pin PQFP

32KX1/32CLKIN

160-pin PQFP Package
Order Number PC87570-ICC/VUL
NS Package Number VUL160

HAEN

Signal/Pin Connection and Description

20

CONNECTION DIAGRAMS

www.national.com

32KX1/32CLKIN

85

80

75

70

65

60

55

5 101520253035

95100105110

40

PC87570

115120125130

50

90

135

140

145

150

155

160

165

170

175

HD0

HD1

HAEN

GND

HD2

HD3

HD4

HD5

HD6

HD7

GND

V

BAT

KBSIN7

KBSIN2

KBSIN1

KBSIN3

PH1/BST1/ENV1

PG3/SEL1

V

CC

SEL0/HRMS

PH2/BST2/TRIS

HIOCHRDY

DA1

GND

PH4/PLI

PH3/PFS

PH5/

ISE

PD6/AD6

PH0/BST0/ENV0

PG2/CLK

DA0

DA3

DA2

PB5(GA20)

AGND

HA9

A6A5A4A3A2

PA2/HMEMWR

HMR

HPWRON

HA0

PB7/SWIN

A8

IRQ12
IRQ11

A14/BE1

A10

A11A7A9

PA6/A17

A13/BE0

PE0/HA18

HRSTO(PB6)

KBSOUT0

HA10

HA11

HA12

HA13

HA14

HA15

PA3/HA16

PA4/HA17

PSDAT1

PC7/PSDAT3

PB0/RING

KBSIN5

KBSIN6

PC6/PSCLK3
PC5/EXINT15

RD/HDEN

PG0/SELIO

WR0

PG4/

WR1

A1

A0

KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4

PC4/EXINT11

PD7/AD7

PF3/D11
PF4/D12

PF1/D9

PF2/D10

PF6/D14

PF5/D13
PF7/D15

PF0/D8

KBSOUT5

KBSIN4

KBSIN0

KBSOUT15

KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9

KBSOUT14

KBSOUT13

KBSOUT12

KBSOUT11

HA1
HA2
HA3
HA4
HA5
HA6
HA7

GND

V

CC

PSDAT2
PSCLK1

PC3/EXINT0
PC2
PC1

PSCLK2

PC0

A12

32KX2

KBSOUT10

PA5/A16

HIOR

HIOW

IRQ1

PA0/

HMEMCS

V

CC

GND

PA1/HMEMRD

IRQ8

PG1/A15/CBRD

PE1/A18/SHBM

D0
D1
D2
D3
D4
D5
D6
D7

AV

CC

PD5/AD5
PD4/AD4
PD3/AD3
PD2/AD2
PD1/AD1
PD0/AD0
V

REF

PFAIL

PB3/TA
PB2/SDA
PB1/SCL

PB4/TB/EXINT10

HA8

V

CC

176-pin TQFP

1

176-pin Thin Quad Flatpack (TQFP)
Order Number PC87570-ICC/VPC
NS Package Number VPC176

NC

NC

NC
NC

NC
NC

NC

NC

NC

NC

NC
NC

NC
NC

NC

NC

45

Signal/Pin Connection and Description

SIGNAL/PIN DESCRIPTIONS

21

www.national.com

2.2 SIGNAL/PIN DESCRIPTIONS

Refer to Table 2-2 for an alphabetical listing of all PC87570 signals and pins, as well as brief descriptions. The following
abbreviations are used in the Type column in this table.

Table 2-1. Type Symbols

Table 2-2. PC87570 Signals

Symbol Description DC Characteristics

TTL Input, TTL compatible See Table 19-7 on page 135.
CMOSS Input, CMOS with Schmidt Trigger See Table 19-7 on page 135.
STRAP Input with Schmidt characteristics and an internal

pull-down resistor, typically used for strap signals

See Table 19-7 on page 135.

CM Output, CMOS buffer See Table 19-7 on page 135.
CMHD1 Output, CMOS buffer with high drive type 1 See Table 19-7 on page 135.
CMHD2 Output, CMOS buffer with high drive type 2 See Table 19-7 on page 135.
OD Output, Open-Drain See Table 19-7 on page 135.
OD2 Output, Open-Drain with high drive type 2 See Table 19-7 on page 135.
PU Weak pull-up capability (on input or output pin) See Table 19-7 on page 135.
OSCIN Oscillator input [not characterized]
OSCOUT Oscillator output [not characterized]
ANIN Analog input signal See Table 19-5 on page 134.
ANOUT Analog output signal See Table 19-6 on page 134.

Signal

Pin Number Buffer Type

Function

160-pin 176-pin Input Output

32KCLKIN 23 25 TTL - 32.768 KHz Oscillator Clock Input..
32KX1 23 25 OSCIN 32.768 KHz Crystal Interface, input to oscillator.
32KX2 25 27 - OSCOUT 32.768 KHz Crystal Oscillator Interface output

to crystal. See Figure 6-1 on page 65.

A18-0 122-104 136, 135,

130-114

- CM Address A18 through A0. CR16A address to
external memory. A16-A17 should not be pulled
up during power-up since include special test
features.

AD7-0 84, 83,

80-75

95, 94,

86-81

ANIN - Analog Inputs of the A/D converter

AGND 82 92 N/A N/A Analog Ground, for ADC and DAC.
AV

CC

81 91 N/A N/A Analog 5V or 3.3V power supply.
BE1,0 118, 117 128, 127 - CM Byte Enable bits 1 and 0 on monitor bus cycles.
BST2-0 92-94 102-104 - CM Bus Status bits 2-0 on monitor bus cycles.

When in DEV environment, these pins allows
monitoring of the external bus cycles. When
BCFG.OBR is also set, the internal bus cycles
are also visible outside. See also Table 2-5 on
page 27.

CBRD 119 129 - CM Core Bus Read Status on monitor bus cycles.

Available in all modes. See Table 2-5 on
page 27.

Signal/Pin Connection and Description

22

SIGNAL/PIN DESCRIPTIONS

www.national.com

CLK 97 107 - CM PC87570 internal clock (On-chip Clock Multi-

plier output). Available in all environments. For
IRE environment, set MCFG.CLKOE=1. See

Table 2-5 on page 27.
D15-0 138-123 152-137 TTL CM CR16A Memory Data bus bits 15 through 0.
DA3-0 88-85 98-95 - ANOUT Digital to Analog Converter Output.
ENV1,0 93, 94 103, 104 STRAP - Environment select strap pins.These pins define

if the device environment, IRE, IRD or DEV.

They are sampled on power-up reset. See Sec-

tion 2.4 on page 26.
EXINT0

EXINT10
EXINT11
EXINT15

58
69
59
62

64
75
65
68

TTL - External Interrupt Inputs 0, 10, 11, 15. Interr upt

signals for general purpose use. These interrupt

signals are asynchronous. See Table 9-2 on

page 82.
GA20 70 76 - CM Gate A20 output. See Section 5.11.6 on page

54.

GND 22, 24,

60, 99,

146

24, 26,

66, 109,

160

N/A N/A Ground for both on-chip logic, output drivers

and back-up battery circuit. See Figure 19-1 on

page 132 for details on connections with

AGND. See also Figure 16-4 on page 125 and

Figure 17-2 on page 129.
HA18-0 10-1,

160-152

12-3,

174-166

TTL - Host Address lines inputs to address registers

in the KBC, PM, RTC/APC and the configura-

tion registers. See Section 5.5.2 on page 50

and Section 5.4.3 on page 50. See also

“HPWRON” pin description below.
HAEN 11 13 TTL - Host Address Enable should be low during

HIORD and HIOWR bus transactions, otherwise

the bus transaction is ignored. Refer to Section

19.5.4 on page 150.

HD7-0 20-13 22-15 TTL CMHD2 Host Data. Bi-directional data bus used to inter-

face the PC87570 to the peripheral data bus of

the host. Refer to Section 19.5.4 on page 150.
HDEN 101 111 STRAP - Host Device Enable, strap pin.

When pulled high during power-up reset, con-

figures the Host device (host interface and

RTC) to be enabled as default after each reset.

When low during power-up reset, the mother-

board PnP protocol must be used to enable the

host access to these devices after each reset.

See Section 2.4.2 on page 26 and Section

5.11.5 on page 54.

HIOCHRDY 12 14 - OD2 Host I/O Channel Ready. An open drain output

that enables extending the host access. This is

used for handling the dual ported access to the

CMOS RAM and to share memory with the

host. See “HRMS” and “HPWRON” pins

description below.
HIOR 144 158 TTL - Host I/O Read. Active-low input that signals an

I/O data read by the host processor.

Signal

Pin Number Buffer Type

Function

160-pin 176-pin Input Output

Signal/Pin Connection and Description

SIGNAL/PIN DESCRIPTIONS

23

www.national.com

HIOW 145 159 TTL - Host I/O Write. Active-low input that signals an

I/O data write by the host processor.
HMEMCS 143 157 TTL - Host BIOS Memory Chip Select. This signal is

in use when the shared memory configuration is

enabled (

SHBM=0). See pin “SHBM” below .

See also Table 2-5 on page 27.
HMEMRD 148 162 TTL - Host Memory Read. Active-low input that sig-

nals a memory data read by the host processor.

This signal is in use when the shared memory

configuration is enabled (

SHBM=0). See pin

“SHBM” below . See also Table 2-5 on page 27.
HMEMWR 149 163 TTL - Host Memory Write. Active-low input that sig-

nals a memory data write by the host processor.

This signal is in use when the shared memory

configuration is enabled (

SHBM=0). See pin
“SHBM” below . See also Table 2-5 on page 27.
For AC parameters, refer to Section 19.5.4 on
page 150.

HMR 150 164 CMOSS - Master Reset. A rising edge that resets the

PC87570. See details at Section 2.3.4 on page

26.

HPWRON 151 165 CMOSS - Host Power On. Indicates that the host power

supply is on, and the host bus interface signals
are valid. While HPWRON is low, the host
inputs are ignored, and all outputs are either
floating or driven low. See Section 5.11.2 on
page 53.

HRMS 95 105 STRAP - Host Reset Mode Select, strap pin. When pulled

high during power-up reset, enables sending
reset event to the Host processor when the
shared BIOS is accessed while the PC87570 is
not in Active mode, or the MCFG.SHOFF or
MCFG.SHMEN are 0. When low, the host
access is extended until the PC87570 com­pletes its execution.

HRSTO 71 77 - CM Host Reset Output
IRQ1 142 156 TTL CMHD2

OD2

Interrupt 1. Active-high output to signal a key­board interrupt. This bit is set when the KBC
port output buffer is full with data to the key­board driver.

IRQ8 141 155 - OD2 Interrupt 8. Active-low output that Indicates an

RTC interrupt.

IRQ11 140 154 TTL CMHD2

OD2

Interrupt 11. Active-high output that indicates an
output buffer full in the Power Management port
of the Host I/F.

IRQ12 139 153 TTL CMHD2

OD2

Interrupt 12. Active-high output that indicates a
mouse interrupt. This bit is set when the KBC
port output buffer is full with data for the mouse
driver.

ISE 89 99 TTL - ISE Interrupt. Reser ved for use by the develop-

ment system.

Signal

Pin Number Buffer Type

Function

160-pin 176-pin Input Output

Signal/Pin Connection and Description

24

SIGNAL/PIN DESCRIPTIONS

www.national.com

KBSIN7-0 27-34 29-36 CMOSS-PU - Internal Keyboard Input scan lines
KBSOUT15-0 35-50 37-42,

47-56

- OD Internal Keyboard Output scan lines

PA6-0 121, 120,

9, 8,

149, 148,

143,

135, 130,

11, 10,

163, 162,

157

TTL-PU CM-PU Port A, bits 0 through 6

PB7-0 72-65 78-71 TTL-PU CM-PU Port B, bits 0 through 7
PC2-0 57-55 63-61 TTL-PU CMHD1-PU Port C, bits 0 through 2 high drive output buff ers
PC7-3 64-62, 59, 58 70-68, 65, 64 TTL-PU CM-PU Port C, bits 3 through 7
PD7-0 84, 83, 80-75 94, 93, 86-81 TTL - Port D, bits 0 through 7, input port only
PE1,0 122, 10 136, 12 TTL-PU CM-PU Port E, bits 0 through 1
PF7-0 138-131 152-145 TTL CM Port F, bits 0 through 7
PFAIL 73 79 CMOSS - Power Fail. Non-maskable interrupt input

detected

PFS 91 101 - CM Pipe Flow Status signal
PG4-0 103, 96,

97, 119,

100

113, 106,
107, 129,

110

TTL CM Port G, bits 0 through 4

PH5-0 89-94 99-104 TTL CM Port H, bits 0 through 5
PLI 90 100 - CM Pipe Long Instruction signal
PSCLK1

1

52 58 TTL-PU

CMHD1-PU

1

PS/2 Channel 1 Clock signal

PSCLK2

1

54 60 TTL-PU

CMHD1-PU

1

PS/2 Channel 2 Clock signal

PSCLK3

1

64 70 TTL-PU

CMHD1-PU

1

PS/2 Channel 3 Clock signal

PSDAT1

1

51 57 TTL-PU

CMHD1-PU

1

PS/2 Channel 1 Data signal

PSDAT2

1

53 59 TTL-PU

CMHD1-PU

1

PS/2 Channel 2 Data signal

PSDAT3

1

63 69 TTL-PU

CMHD1-PU

1

PS/2 Channel 2 Data signal

RD 101 111 - CMHD Read control signal. May be used as Output

Enable.

RING 65 71 CMOSS - Advanced P ower Control Ring detect and wake-

up input

SCL 66 72 CMOSS-PU OD-PU ACCESS.bus Serial Clock signal
SDA 67 73 CMOSS-PU OD-PU ACCESS.bus Serial Data signal
SEL0 95 105 - CM Zone Select 0. Chip-select signal for the Exter-

nal Memory.

SEL1 96 106 - CM Zone Select 1. Used to select the off-chip Base

Memory.

SELIO 100 110 - CM I/O Expansion chip-select signal
SHBM 122 136 STRAP - Shared host BIOS Memory. Enable when 0
SWIN 72 78 STRAP - On switch to the MIWU and ICU
TA 68 74 TTL CM Timer pin A

Signal

Pin Number Buffer Type

Function

160-pin 176-pin Input Output

Signal/Pin Connection and Description

SIGNAL/PIN DESCRIPTIONS

25

www.national.com

1. This is a quasi-bidirectional output. It has drive low capability. It is pulsing high for a short period; steady state:
pull high using a weak pull-up. See also Section 12.2.3 on page 90

TB 69 75 TTL - Timer pin B
TRIS 92 102 STRAP - TRI-STATE strap option. When high, during

power-up reset, causes the PC87570 to float all
its output and I/O signals.

V

BAT

26 28 IN

ULR

- Battery supply. This is the 2.4 - 5.5V battery
voltage for the RTC circuitry.

V

CC

21, 61,

98, 147

23, 67,

108, 161

N/A N/A Digital 5V or 3.3V power supply

V

REF

74 80 ANIN ANOUT Reference voltage for the on-chip A/D circuits.

With the internal V

REF

enabled a capacitor is

connected between V

REF

and GND. When the

internal V

REF

is disabled, an External Refer-

ence voltage should be connected to this input.

WR1,0 103, 102 113, 112 - CM Write control for bytes 0 and 1

Signal

Pin Number Buffer Type

Function

160-pin 176-pin Input Output

Signal/Pin Connection and Description

26

RESET SOURCES AND TYPES

www.national.com

2.3 RESET SOURCES AND TYPES

2.3.1 Power-Up Reset

The PC87570 includes an internal power-up reset circuit
This circuit generates the power-up reset signal which

During power-up reset, the PC87570 responds as follows:

●

Carries out all the warm reset actions

●

Enables the 32K crystal, if it is disabled

●

Resets the HFCG Register to its default frequency

●

Loads preset values to all register.

●

Puts pins with strap options into TRI-STATE, and en­ables the internal pull-downs on the strap pins

●

Samples the values of the strap pins.

2.3.2 Warm Reset

During a warm reset, the PC87570 responds as follows:

●

Ter minates instructions being executed

●

Discards results not yet written to memory

●

Traps and eliminates pending interrupts

●

Clears the internal latch for the edge-sensitive external
interrupt

●

Deactivates the external bus control signals WR(0-1),
SEL(0-1), SELIO, RD and BST(0-2)

●

Puts the address A(0-15) and data D(0-15) buses in
TRI-STATE

●

Switches to Active mode

●

Loads preset values into registers

●

Sets the motherboard PnP mechanism to its reset
state.

Certain registers, such as the HFCG and Port PC Registers,
are affected only by power-up and/or WATCHDOG reset.
During warm reset, the strap pins are not sampled and the
configuration determined at power-up is unaffected by sub­sequent warm resets.

2.3.3 WATCHDOG Reset

During a WATCHDOG reset, the PC87570 performs the
power-up reset actions with one exception: it does not sam­ple the value of the strap pins. Instead, it maintains the con­figuration determined by the strap pins at power-up reset.

2.3.4 Triggering Reset

The PC87570 is reset by an internal reset signal generated
on the ramp-up of the V

CC

power supply (cold reset). The
chip is also reset on the rising edge of the HMR pin (warm
reset).

Power-Up Reset The PC87570 performs a power-up reset
when power is applied to it. This reset is completed t

IRST

af­ter the internal clock has stabilized. See Figure 19-25 on
page 154.

If the RTC clock was disabled before power-up, external de­vices should wait at least t

32KW

(see before accessing the
PC87570. If HRMS=0, any access by the host processor is
stalled, by de-asserting (0) HIOCHRDY, until after the reset
process is completed and the bus request can be per­formed.

Warm Reset A rising edge of the HMR input initiates a
warm reset. The rising edge is identified only when power
(V

CC

) is applied to the PC87570 completed the internal
power-up reset cycle. The reset continues for a period of
about 16 clock cycles after the HMR rising edge. See details
at Figure 19-26 on page 154.

The PC87570 can operate when HMR is still active (high).
In this case, the host bus I/F is inactive.

Note: In all PC87570 revisions, before C3, the HMR (for­merly HMR) input pin is ignored when HPWRON is 0, dis­abling reset execution.

WATCHDOG Reset

The PC87570 generates a WATCHDOG reset on request
from the TWD (WATCHDOG signal is asserted). The reset
period is identical to the power-up reset period.

2.4 STRAP PINS

During power-up reset, the ENV(0-1), TRIS, HRMS, HDEN
and

SHBM strap input signals are sampled. Internal pull­down resistors set these signals to 0. You can use an exter­nal 10 KΩ resistor connected to V

CC

to set them to 1.

2.4.1 Setting the Environment

ENV0 and ENV1 determine the operating environment. Ta­ble 2-3 shows the settings allowed. Pulling both ENV0 and
ENV1 to 1 at the same time produces unpredictable results.

Table 2-3. Environment Pin Settings

Figures 1-1 on page 16, 1-2 on page 17, and 1-3 on page
18 demonstrate how to use the ENV(0-1) signals to config­ure the PC87570 for IRE, IRD, and Dev environment, re­spectively.

2.4.2 Other Strap Pin Settings

Table 2-4 provides brief descriptions of other strap inputs.
For details on

SHBM, HRMS, HDEN and TRIS, see sec­tions 5.2 on page 49, 5.11.4 on page 53, 5.11.5 on page 54
and 18.2 on page 130, respectively.

Table 2-4. Other Strap Pin Settings

Environment ENV0 ENV1

IRE 0 0

IRD 0 1

Dev 1 0

Strap

Pin

Internal Pull-Down (0) External Pull-Up (1)

SHBM Enables shared memory

with host BIOS

Disables shared
memory with host BIOS

HRMS Extends host access

until the PC87570
completes its execution

Enables a reset event to
be sent to the host
when the shared BIOS
is accessed while the
PC87570 is not in
Active mode, or SHOFF
or SHMEM bit is cleared
in MCFG Register

Signal/Pin Connection and Description

ALTERNATE FUNCTIONS

27

www.national.com

2.4.3 System Load on Strap Pins

The loads connected to the strap pins should prevent the
voltage on them from dropping below V

STRh

when the pins

should be high (1), or rising above V

STRl

when they should

be low (0). See Table 19-7 on page 135.
If the load caused by the system on the strap pins exceeds

10 µA when V

CC

= 5.0V or 5 µA when VCC= 3.3V, use ei­ther an external pull-up resistor or a smaller pull-down resis­tor to keep the pin at 1 or 0, respectively.

2.4.4 Strap Inputs During Idle Mode

When the PC87570 is in Idle mode and shared memory with
host BIOS is enabled, the A(16-18) signals are forced to the
value sampled on the strap input that shares the pin. This is
done to reduce leakage currents on external resistors con­nected to that pin.

Note: A(16-17) are reserved strap inputs that should not

be pulled to 1.

2.4.5 Strap Pin Status Register (STRPST)

The STRPST Register is a byte-wide, read-only register. It
enables the software to read the value set to strap pins dur­ing power-up reset. STRPST bits provide the value of their
respective strap input. See Table 2-5 for bit details.

2.5 ALTERNATE FUNCTIONS

The PC87570 uses the GPIO port pins to multiplex func­tions and thereby maximize the device’s flexibility, as
shown in Table 2-5. You select alternate pin functions
through the configuration registers and strap options, as fol­lows:

●

The SHBM strap pin (see Table 2-4) controls the PA
pins. When

SHBM = 1, the pins function as GPIO port

signals. When

SHBM=0, they function as described in

Section 5.2.1 on page 49.

●

The ports’ Alternate Function Control Register controls
the PB, PC, PD and PE pins. Each of the ports’ pins
may be used as a GPIO port or in its alternate function.

●

The environment setting and MCFG bits control port
PF and PG pins.

●

The environment setting controls port PH pins. When
in Dev environment, the pins perform their alternate
functions. In IRE or IRD environments, they function
as GPIO ports.

When a pin is used as GPIO and not in its alternate function,
disable the alternate function in the module’s register to pre­vent wired effects.

Table 2-5 lists the I/O pins and their alternate functions.
When you use a pin as GPIO, you should disable the alter­nate function in the module register to prevent wired effects.

Table 2-5. Alternate Function Mapping

HDEN Disables host interface;

must be enabled using
the motherboard PnP
protocol after each reset

Enables host interface
to its default settings
(legacy address of KBC,
RTC and PMC)

TRIS Normal operation Causes PC87570 to

float all its output and
I/O signals for ISE use

Strap

Pin

Internal Pull-Down (0) External Pull-Up (1)

7 3 2 1 0

Reserved HDEN HRMS SHBM

Pin Name

Port Signal

Alternate
Function

Select

(Alternate Function)

Name Type

PA0/

HMEMCS PA0

I/O

HMEMCS

SHBM=0

PA1/

HMEMRD PA1 HMEMRD

PA2/

HMEMWR PA2 HMEMWR
PA3/HA16 PA3 HA16
PA4/HA17 PA4 HA17

PA5/A16 PA5 A16
PA6/A17 PA6 A17

Signal/Pin Connection and Description

28

ALTERNATE FUNCTIONS

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PB0/RING PB0

I/O

RING PBALT.0

PB1/SCL PB1 SCL PBALT.1

PB2/SDA PB2 SDA PBALT.2

PB3/TA PB3 TA PBALT.3

PB4/TB/EXINT10 PB4 TB/EXINT10 PBALT.4

PB5/GA20 PB5

1

GA20 0 always

PB6/

HRSTO PB6

2

HRSTO 1 always

PB7/SWIN PB7 SWIN PBALT.7

PC0 PC0

I/O

- PCALT.0
PC1 PC1 - PCALT.1
PC2 PC2 - PCALT.2

PC3/EXINT0 PC3 EXINT0 PCALT.3
PC4/EXINT11 PC4 EXINT11 PCALT.4
PC5/EXINT15 PC5 EXINT15 PCALT.5

PC6/PSCLK3 PC6 PSCLK3 PCALT.6
PC7/PSDAT3 PC7 PSDAT3 PCALT.7

PD0/AD0 PD0

Input

AD0 PDALT.0
PD1/AD1 PD1 AD1 PDALT.1
PD2/AD2 PD2 AD2 PDALT.2
PD3/AD3 PD3 AD3 PDALT.3
PD4/AD4 PD4 AD4 PDALT.4
PD5/AD5 PD5 AD5 PDALT.5
PD6/AD6 PD6 AD6 PDALT.6
PD7/AD7 PD7 AD7 PDALT.7

PE0/HA18 PE0

I/O

HA18 PEALT.0

PE1/A18 PE1 A18 PEALT.1

PF0/D8 PF0

I/O

D8

Dev or IRD Env;

IRE Env when

MCFG.EXM16=1

PF1/D9 PF1 D9
PF2/D10 PF2 D10
PF3/D11 PF3 D11
PF4/D12 PF4 D12
PF5/D13 PF5 D13
PF6/D14 PF6 D14
PF7/D15 PF7 D15

Pin Name

Port Signal

Alternate
Function

Select

(Alternate Function)

Name Type

Signal/Pin Connection and Description

SYSTEM CONFIGURATION REGISTERS

29

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1. PB5 is initialized upon reset as an output port with data set to 1. This allows the
PC87570 firmware to use it as GA20.

2. PB6 is always configured as output and with its alternate function enabled. See
Section 5.11.4 on page 53.

2.6 SYSTEM CONFIGURATION REGISTERS

2.6.1 Module Configuration Register (MCFG)

The MCFG Register is a read/write, byte-wide register. It is
used for global system configuration and setup.

Write operations to the MCFG Register should write zeros
to all reserved bits. Upon reset, non-reserved bits of MCFG
are cleared to 0. MCFG can be written in Active mode only.
Its contents is preserved in Idle mode.

In IRE environment, all fields of MCFG should be used to
designate associated pins as GPIO ports or for their alter­nate functions. In IRD and Dev environments, the pins are
always allocated for IRD or Dev use. The I/O ports function­ality can be implemented using off-chip logic.

To guarantee binary and cycle-by-cycle compatibility
among the different environments, define the MCFG fields
as required for IRE even when in IRD or Dev environments,
and use the I/O Expansion protocol to build an off-chip im­plementation of the I/O ports when they are used by the ap­plication.

ADBs or ISE systems may use the MCFG Shadow (MCFG­SH) Register to select the functionality of the signal that
reaches the user’s application.

Bit 0 - Base Memory Shadow Off (SHOFF)

While cleared, the Base Memory can be accessed start­ing from address 10000h and the External Memory can­not be accessed. When set, this signal turns off the
Base Memory shadow (i.e., the copy that starts at ad­dress 00000h) and enables access to the External
Memory. Once SHOFF is set, the firmware should not
clear it.

Bit 1 - Shared Memory Access Enable (SHMEM)

The host processor is enabled to access the shared
memory only when SHMEM and SHOFF are set. Addi­tional conditions to the host access are described in
Sections 2.7 on page 30 and 5.2 on page 49. When
SHMEM is cleared the host access to the shared mem­ory is disabled. Once SHMEN is set, the firmware
should not clear it.

Bit 2 - External Memory 16-Bit (EXM16)

While cleared, it defines the External Memory as 8 bits
wide. When set it enables the use of a 16-bit wide Exter­nal Memory. The bus width as indicated in this register
and the bus width as defined in zone0 of the BIU
(SZCFG0) should be the same.

When a 16-bit wide External Memory is used, ports
PF0-7 and PG4 serve as part of the memory interface.

PG0/

SELIO PG0

I/O

SELIO Dev or IRD Env;

IRE Env when

MCFG.EXIOE=1

PG1/A15/CBRD PG1 A15/CBRD Dev or IRD Env;

IRE Env when

MCFG.A15E=1

PG2/CLK PG2 CLK Dev or IRD Env;

IRE Env when

MCFG.CLKOE=1

PG3/

SEL1 PG3 SEL1 Dev or IRD Env;

IRE Env when

MCFG.EXM16=1

PG4/

WR1 PG4 WR1

PH0/BST0/ENV0 PH0

I/O

BST0

Dev Env

PH1/BST1/ENV1 PH1 BST1

PH2/BST2 PH2 BST2

PH3/PFS PH3 PFS

PH4/PLI PH4 PLI
PH5/

ISE PH5 ISE

Pin Name

Port Signal

Alternate
Function

Select

(Alternate Function)

Name Type

7 6 5 4 3 2 1 0

Res CLKOE EXIOE A15E EXM16 SHMEM SHOFF

Signal/Pin Connection and Description

30

SHARED MEMORY CONFIGURATION

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Bit 3 - Address A15 Enable (A15E)

When cleared (0), the PG1/A15 pin is used as a PG1
GPIO port. When it is set (1), the pin is used to output
address line A15. This allows interface to up to 56 Kbyte
of External Memory. It is set when shared BIOS memory
mode is detected.

Bit 4 - Expansion I/O Enable (EXIOE)

When cleared (0), the PG0/

SELIO pin is used as a
GPIO port signal (PG0). When set (1), the pin is used to
output

SELIO signal. SELIO allows the use of the I/O
Expansion protocol to implement I/O ports off-chip, in
addition to the I/O ports implemented on-chip.

BIt 5 - Clock Output Enable (CLKOE)

When cleared (0), the PG2/CLK pin is used as a gener­al-purpose port signal (PG2). When set (1), the port out­puts the clock signal.

Bit 6 - Test Hook Set Flag (TEST)

This bit is set only when the test hook is enabled. The
Base Memory should jump to the test hook routine when
this bit is identified as high. Any device used in the IRE
environment must hold this code. This is a read only bit.
When modifying the MCFG Register, always write 0 to
this bit.

2.6.2 PAGE Register

The PAGE Register is a read/write, byte wide register.
When shared memory is used, this register defines the most
significant bits of the address used when the CR16A core
access the External Memory (zone 0). This defines which
part of the shared memory the PC87570 firmware uses.
During host processor access to the shared memory, the
address lines are taken from the host address bus and not
from the Page Register.

See “External Memory Mapping into Shared BIOS Memory”
on page 32 for an explanation of how the bits below are
used to map the External Memory.

2.7 SHARED MEMORY CONFIGURATION

The PC87570 can share the use of the same memory de­vice with the host processor. Either Flash EPROM or ROM
devices may be used. The memory can be up to 512 KByte.

The PC87570 is mapped into a block of 56 KByte in the
memory device. It may use all the block or part of it.

The host can access any of the bytes in the Flash device.
The BIOS program may be stored at any location not used
by the PC87570 firmware, even within the block assigned to
it.

To share the BIOS memory, hold the

SHBM strap input low
during power-up reset. The firmware should perform the fol­lowing initialization steps after reset:

1. Set MCFG.A15E to 1 and MCFG.EXM16 according to

the value of PH[3].

2. Set MCFG.SHOFF to enable access to the External

Memory.

3. Load the Page Register with the firmware’s base ad­dress of the Shared BIOS block that needs to be ac­cessed.

4. Configure the memory (zone0) access parameters (i.e.,
bus width, write cycle type, number of wait and hold cy­cles) using the Page and SZCFG0 Registers. The mem­ory device may be either 8 or 16 bits wide; the host
interface is 8-bits wide and the PC87570 takes care of
the bus width translation.

5. If the memory device is 512 KByte (i.e., above 256
KByte), set the PEALT.0 and PEALT.1 bits, configuring
PE0 and PE1 to be used in their alternate functions.
HA18 is used as a BIOS page select.

The External Memory may be read or written by the core,
as necessary, during steps 3 through 5, but the shared
memory cannot be accessed by the host processor.

6. Set MCFG.SHMEN only after the above configurations
are completed.

Figure 2-1 describes the hardware scheme used when a
512K Byte, 8-bit wide, Flash memory is connected to the
PC87570 in the shared BIOS memory configuration.

See Section 5.2 on page 49 for more details about the
shared memory interface and the bus protocols in use.

2.8 MEMORY MAP

The memory and I/O devices are directly mapped into the
256-Kbyte address space of the CR16A. The CR16A allows
the first 128 Kbytes (00000h-1FFFFh) of its address space
to include both code and data.

The boot section code and constant data of a PC87570­based system is stored in the Base Memory. This memory is:

●

On-chip ROM in IRE environment

●

Off-chip memories (ROM, Flash or SRAM memory) in
IRD or Dev environment.

Most of the code and constant data of the PC87570 is
stored in the External Memory. This memory can be either
a ROM, Flash or RAM device interfaced directly with the
PC87570. A power-up configuration pin allows memory
sharing with the host processor.

Only byte-wide transactions may access byte-wide regis­ters, and only word-wide transactions may access word­wide registers. Attempts to read a write-only register or write
to a read-only register cause unpredictable results.

Zeros must be written to reserved bits. Reading reserved
bits returns an undefined value. When modifying a register
with reserved bits, the data read from reserved bits can be
written back to it.

Table 2-6 shows how the PC87570’s memory and I/O de­vices are mapped in the CR16A address space. Appendix
A on page 156 shows the address map of the registers for
the other modules.

Addresses not included in Table 2-6 or in Chapter A on
page 156 are reserved. Attempts to access unlisted ad­dresses produce unpredictable result

s.

7 3 2 1 0

Reserved PAGE18 PAGE17 PAGE16