NSC PC87351-ICK-VLA Datasheet

PC87351 PC98 and ACPI Compliant SuperI/O with System Wake-Up Control

www.national.com

PRELIMINARY

May 1998

PC87351 PC98 and ACPI Compliant SuperI/O with System Wake-Up Control

Highlights

General Description

The PC87351, a member of National Semiconductor’s SuperI/O family of integrated PC peripherals, is a 128-pin, PC98 and ACPI compliant SuperI/O that offers a single-chip solution to the most commonly used ISA peripherals.

The PC87351 incorporates: a Floppy Disk Controller (FDC) which is available also on the Parallel Port pins as a multiplexed option (PPM), two enhanced Serial Ports, Infrared Comunication Port (HP-SIR, Sharp-IR, and Consumer Electronics-IR), a full IEEE 1284 Parallel Port, a Keyboard and Mouse Controller (KBC), System Wake-Up Control (SWC), General-Purpose Input/Output (GPIO) Ports with assert interrupt capability, and Fan Speed Control (FSC).

Outstanding Features

• Fan Speed Control for two fans

• 11 General-Purpose I/O Ports, bi-directional, with in-

terrupt assertion capability

• System Wake-Up Control powered by V

, generates

power-up request in response to preprogrammed keyboard or mouse sequence, modem, telephone ring, and two general-purpose events without an external clock

• Serial or parallel IRQ support

• Programmable write protect for Floppy Disk Controller

• Power-fail recovery support

Block Diagram

Controller

System Wake-Up

IEEE 1284

Wake-Up

Parallel Port

Ports

Keyboard and Mouse

Interface

Floppy Disk

Controller

Keyboard and Mouse

Control

Events

Host Interface

ISA

Interface

SERIRQ

I/O Ports

General-Purpose

I/O

PWUREQ

Serial Port 2

Serial Infrared

Interface Interface

Serial Port 1

Serial

Interface

BAT

FANOUT0 FANOUT1

Fan Speed Control

with IR

Floppy Drive

Interface

Parallel Port/ Floppy Drive

PPM

IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation. Microsoft

and Windows® are registered trademarks of Microsoft Corporation.

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

Highlights (Continued)

www.national.com

Features

• PC98 and ACPI Compliant

— PnP Conﬁguration Register structure — Flexible resource allocation for all logical devices

❏ Relocatable base address ❏ 9 Parallel IRQ or 15 Serial IRQ routing options ❏ 3 optional 8-bit DMA channels (where applica-

ble)

• Floppy Disk Controller (FDC)

— Software compatible with the PC8477, which con-

tains a superset of the FDC functions in the µDP8473, the NEC µPD765A and the N82077

— 16-byte FIFO — Burst and non-burst modes — High-performance, digital data separator that does

not require any external ﬁlter components

— Standard 5.25" and 3.5" Floppy Disk Drive (FDD)

support

— Perpendicular recording drive support — Three-mode FDD support — Full support for IBM Tape Drive Register (TDR) im-

plementation of AT and PS/2 drive types

— Programmable write protect

• Parallel Port

— Software or hardware control — Enhanced Parallel Port (EPP) compatible with new

version EPP 1.9 and IEEE 1284 compliant

— EPP support for version EPP 1.7 of the Xircom spec-

iﬁcation

— EPP support as mode 4 of the Extended Capabilities

Port (ECP)

— IEEE 1284 compliant ECP, including level 2 — Selection of internal pull-up or pull-down resistor for

Paper End (PE) pin

— PCI bus utilization reduction by supporting a de-

mand DMA mode mechanism and a DMA fairness mechanism

— Protection circuit that pre vents damage to the paral-

lel port when a printer connected to it powers up or is operated at high voltages, even if the device is in power-down

— Output buffers that can sink and source 14 mA

• Parallel Port Multiplexer (PPM)

— Additional set of FDC signals multiple x ed on P arallel

Port pins

— Optional connection of additional, external FDD on

Parallel Port connector

• Serial Port 1

— Software compatib le with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — UART data rates up to 1.5 Mbaud

• Serial Port 2 with Infrared

— Software compatib le with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — UART data rates up to 1.5 Mbaud — HP-SIR — ASK-IR option of SHARP-IR — DASK-IR option of SHARP-IR — Consumer Remote Control supports RC-5, RC-6,

NEC, RCA and RECS 80

— Non-standard DMA support − 1 or 2 channels

• Keyboard and Mouse Controller (KBC)

— 8-bit microcontroller — Software compatib le with the 8042AH and PC87911

microcontrollers

— 2 KB custom-designed program ROM — 256 bytes RAM for data — Four programmable dedicated open-drain I/O lines — Asynchronous access to two data registers and one

status register during normal operation

— Support for both interrupt and polling — 93 instructions — 8-bit timer/counter — Support for binary and BCD arithmetic — Operation at 8 MHz,12 MHz or 16 MHz (prog ramma-

ble option)

— Can be customized b y using the PC87323, which in-

cludes a RAM-based KBC as a development platform for KBC code

• 11 General-Purpose Bi-Directional I/O (GPIO) Ports

— 11 GPIO pins with interrupt assertion capability — Progr ammable drive type for each output pin(open-

drain, push-pull or output disable)

— Programmable option for internal pull-up resistor on

each input pin

— Output lock option — Back-drive protection circuit

• System Wake-Up Control (SWC)

— Power-up request upon detection of Keyboard,

Mouse,

RI1,RI2,RING, PME1 and PME2 activity, as

follows:

❏ Preprogrammed Keyboard or Mouse sequence ❏ External modem ring on serial ports ❏ Ring pulse or pulse train on the

RING input

❏ General purpose events, PME1 and PME2

— Optional routing of power-up request on IRQ line — Powered by V

— Battery-backed wake-up setup — Power-fail recovery support

Highlights (Continued)

www.national.com

• Fan Speed Control

— Supports different fan types — Two speed control lines with Pulse Width Modulation

(PWM)

❏ Output signal in the range of 6 Hz to 93.75 KHz ❏ Duty cycle resolution of 1/256

• Clock Sources

— 48 MHz clock input — On-chip low frequency clock generator for wake-up — 33 MHz PCI clock input for Serial IRQ

www.national.com

Datasheet Revision Record

Revision Date Status Comments

January 1998 Advanced Information First pass with pin assignment March 1998 Preliminary Implemented:

Item 1, Important Notice, pin reassignment

May 1998 Preliminary Implemented:

Items 2-31 below Paginated Datasheet Revision Record in datasheet body

Item Topic Change/Correction Location

2 Pin description Table describing KBCLK, KBDAT, MCLK and MDAT

signals enhanced to identify pin drivers

Section 1.4.7

3 PPM power save mode All references deleted Chapter 2 4 Device architecture 9 logical devices Section 2.1 5 Index 74h, 75h

DMA Channel Select 0, 1

Modiﬁed Section 2.2.3,

Table 2-7 6 VSB Power-Up Reset Hardware reset explanation modiﬁed Section 2.2.5 7 New section added REGISTER TYPE ABBREVIATIONS added before

the existing section; all subsequent numbering changed

Section 2.3

8 SuperI/O Conﬁguration 1 Register

Bit 3

Reserved Section 2.4.3

9 SuperI/O Conﬁguration 2 Register Bits

6 5 Function

0 0 GPIO17 0 1 KBRST (default) 1 0 P12 1 1 PNF (PPM mode enabled)

Bits 2 1 0 Function

0 0 X GPIO14 (default) 0 1 1 GPIO14 0 1 0 IRQ9 1 0 X IRRX2/IRSL0 1 1 X P17

Section 2.4.4

10 SuperI/O Revision ID Register Location and Type added Section 2.4.7 11 Keyboard and Mouse Controller All references to TEST0 and TEST1 changed to T0

and T1, respectively.

Section 2.11.1

12 Implementation Ports 1 and 2 description deleted Section 2.12.2 13 GPIO Conﬁguration Registers’ Access Drawing modiﬁed Figure 2-6 14 GPIO Pin Conﬁguration Select Register

Bits 5-4

01, 10: Binary value of the port number, 1-2 respectively 11: Reserved

Section 2.12.4

15 Fan Speed Control General Description modiﬁed; nomenclature of Fan

Control Duty Cycle and Fan Control Pre-Scale registers changed; references to Fan Speed Monitor deleted; conﬁguration parameters (Reset and Type) modiﬁed

Section 2.13

16 System events Number of events changed to seven Section 3.2

Datasheet Revision Record (Continued)

www.national.com

17 Keyboard Data Shift Register Description modiﬁed Section 3.4.6 18 Mouse Data Shift Register Description modiﬁed Section 3.4.7 19 Ports with fewer than 8 bits Implementation description Chapter 4 20 Interrupt Assertion and Handling Bit nomenclature modiﬁed Section 4.3 21 GPIO Pin Conﬁguration Access Register Bit nomenclature and descriptions changed Section 4.4.1 22 GPIO Data Out Register Bitmap and Reset values added Section 4.4.3 23 GPIO Data In Register Bitmap and Reset values added Section 4.4.4 24 GPIO Interrupt Enable Register Bitmap and Reset values added Section 4.4.5 25 GPIO Status Register Bitmap and Reset values added Section 4.4.6 26 Functional Description Corrected and enhanced Section 5.2 27 Fan Control Duty Cycle Register

Bits 7-0

00h: PWM output is continuously low 01h-FEh: PWM output is high for [Duty Cycle Value] clock

cycles and low for [256-Duty Cycle Value] clock cycles FFh: PWM output is continuously high

Section 5.3.3

28 Device Speciﬁcations Timing diagrams drawn more precisely Chapter 11 29 V

BAT

Battery Supply Current Conditions and Max modiﬁed Section 11.1.4

30 Host Interface I/O Cycle Timing t

RDYA

, t

RDYl

and t

RWl

added to table; footnote 2 added

to table; IOCHRDY timing diagram added

Section 11.2.3

31 Serial IRQ Timing Output timing diagram modiﬁed Section 11.2.6

Item Topic Change/Correction Location

www.national.com

Contents at a Glance

This datasheet is organized to reflect two major topics: device specific issues (Highlights through Chapter 2), and proprietary functional blocks (Chapters 3 through 10). Chapter 11 summarizes the AC/DC device characteristics.

Highlights ................................................................................................................................................1

This chapter provides a description and block diagram of the PC87351 major functional blocks, the features that make this device outstanding as compared with comparable devices, and the features of each functional block.

Datasheet Revision Record...................................................................................................................4

This chapter serves two functions: it provides a record of the datasheet revisions; it documents the major changes of this revision as compared with the previous one. Each change is cross-referenced and linked to the change location within the datasheet.

1 Signal/Pin Connection and Description............................................................................................. 11

This chapter includes four major sections: a connection diagram that shows all pins and their related signals; an alphabetical directory of all signals/pins linked to a table where more detailed information is provided; a summary of all multiplexed signals and how to configure them for default and alternate settings, and functionally grouped tables that describe each signal/pin in detail.

2 Device Architecture and Configuration.............................................................................................. 24

This chapter presents all PC87351 device specific information on the relevant functional blocks, as well as hardware and software configuration procedures and the related configuration registers.

3 System Wake-Up Control (SWC)......................................................................................................... 51

This chapter describes the system wake-up capabilities of the PC87351, designed to maximize device functionality while minimizing power consumption.

4 General-Purpose Input/Output (GPIO) Port ....................................................................................... 57

This chapter describes a single 8-bit GPIO port, whose operation is associated with two register sets. Refer to the Device Architecture and Configuration chapter for the specific implementation in this device.

5 Fan Speed Control................................................................................................................................ 64

This chapter describes the Fan Speed Control, a programmable Pulse Width Modulation (PWM) generator whose output is used to control the fan’s power voltage. Refer to the

Device Architecture and Configuration

chapter for the specific imple-

mentation in this device.

6-10 Legacy Functional Blocks

Please refer to the PC87307, PC87309 or PC87317 Datasheet for information on the Keyboard and Mouse Controller (KBC), Serial Port 1, Serial Port 2 with IR, Parallel Port and Floppy Disk Controller (FDC).

11 Device Characteristics.......................................................................................................................................72

This chapter provides DC electrical characteristics, both general and of all device pins, as well as AC electrical characteristics.

www.national.com

Table of Contents

Highlights.......................................................................................................................................................1

Datasheet Revision Record....................................................................................................................4

1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM .........................................................................................................11

1.2 SIGNAL/PIN DIRECTORY ........................................................................................................12

1.3 PIN MULTIPLEXING .................................................................................................................16

1.4 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................17

1.4.1 Clock ............................................................................................................................17

1.4.2 Fan Speed Control ......................................................................................................17

1.4.3 FDC (Including PPM) ...................................................................................................17

1.4.4 General-Purpose Input/Output (GPIO) Ports ...............................................................19

1.4.5 Host Interface ..............................................................................................................20

1.4.6 Infrared (IR) .................................................................................................................20

1.4.7 Keyboard and Mouse Controller (KBC) .......................................................................21

1.4.8 Parallel Port .................................................................................................................22

1.4.9 Power and Ground ......................................................................................................22

1.4.10 Serial Ports 1 and 2 .....................................................................................................23

1.4.11 Strapping .....................................................................................................................23

1.4.12 System Wake-Up Control ............................................................................................23

2.0 Device Architecture and Configuration

2.1 OVERVIEW ...............................................................................................................................24

2.2 CONFIGURATION STRUCTURE AND ACCESS .....................................................................25

2.2.1 The Index-Data Register Pair ......................................................................................25

2.2.2 Banked Logical Device Registers ................................................................................25

2.2.3 Standard PnP Register Definitions ..............................................................................26

2.2.4 Overview of PnP Standard Registers ..........................................................................28

2.2.5 Default Configuration Setup ........................................................................................29

2.2.6 Address Decoding .......................................................................................................29

2.2.7 The Internal Clocks ......................................................................................................29

2.3 REGISTER TYPE ABBREVIATIONS ........................................................................................30

2.4 SUPERI/O CONFIGURATION AND CONTROL REGISTERS .................................................30

2.4.1 SuperI/O Register Map ................................................................................................30

2.4.2 SuperI/O ID Register (SID) ..........................................................................................30

2.4.3 SuperI/O Configuration 1 Register (SIOCF1) ..............................................................31

2.4.4 SuperI/O Configuration 2 Register (SIOCF2) ..............................................................32

2.4.5 SuperI/O Configuration 3 Register (SIOCF3) ..............................................................33

2.4.6 SuperI/O Configuration 4 Register (SIOCF4) ..............................................................34

2.4.7 SuperI/O Revision ID Register (SRID) ........................................................................34

2.5 PARALLEL PORT MULTIPLEXER (PPM) ................................................................................35

2.5.1 PPM Mode ...................................................................................................................35

2.5.2 TRI-STATE Control of Parallel Port Pins .....................................................................36

2.6 FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0 ...................................................37

Table of Contents (Continued)

www.national.com

2.6.1 General Description .....................................................................................................37

2.6.2 Configuration ...............................................................................................................37

2.6.3 FDC Configuration Register ........................................................................................38

2.6.4 Drive ID Register .........................................................................................................38

2.7 PARALLEL PORT - LOGICAL DEVICE 1 .................................................................................39

2.7.1 General Description .....................................................................................................39

2.7.2 Configuration ...............................................................................................................39

2.7.3 Parallel Port Configuration Register ............................................................................40

2.8 SERIAL PORT 2 - LOGICAL DEVICE 2 ....................................................................................41

2.8.1 General Description .....................................................................................................41

2.8.2 Configuration ...............................................................................................................41

2.8.3 Serial Port 2 Configuration Register ............................................................................41

2.9 SERIAL PORT 1 - LOGICAL DEVICE 3 ....................................................................................42

2.9.1 Configuration ...............................................................................................................42

2.9.2 Serial Port 1 Configuration Register ............................................................................42

2.10 SYSTEM WAKE-UP CONTROL (SWC) - LOGICAL DEVICE 4 ................................................43

2.10.1 Configuration ...............................................................................................................43

2.11 KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6 ..................44

2.11.1 General Description .....................................................................................................44

2.11.2 Configuration ...............................................................................................................45

2.11.3 KBC Configuration Register ........................................................................................45

2.12 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7 .....................46

2.12.1 General Description .....................................................................................................46

2.12.2 Implementation ............................................................................................................46

2.12.3 Configuration ...............................................................................................................46

2.12.4 GPIO Pin Configuration Select Register ......................................................................47

2.12.5 GPIO Pin Configuration Access Register ....................................................................48

2.13 FAN SPEED CONTROL - LOGICAL DEVICE 8 ........................................................................49

2.13.1 General Description .....................................................................................................49

2.13.2 Configuration ...............................................................................................................49

2.13.3 Fan Speed Control Configuration Register ..................................................................50

3.0 System Wake-Up Control (SWC)

3.1 OVERVIEW ...............................................................................................................................51

3.2 FUNCTIONAL DESCRIPTION ..................................................................................................51

3.3 EVENT DETECTION .................................................................................................................51

3.3.1 Modem Ring ................................................................................................................51

3.3.2 Telephone Ring ...........................................................................................................51

3.3.3 Keyboard and Mouse Activity ......................................................................................51

3.3.4 General-Purpose Events .............................................................................................51

3.4 SWC REGISTERS .....................................................................................................................52

3.4.1 SWC Register Map ......................................................................................................52

3.4.2 Wake-Up Events Control Register (WKCR) ................................................................52

3.4.3 Wake-Up Events Status Register (WKSR) ..................................................................53

Table of Contents (Continued)

www.national.com

3.4.4 Wake-Up Configuration Register (WKCFG) ................................................................54

3.4.5 PS/2 Protocol Control Register (PS2CTL) ...................................................................54

3.4.6 Keyboard Data Shift Register (KDSR) .........................................................................55

3.4.7 Mouse Data Shift Register (MDSR) .............................................................................55

3.4.8 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) ......................................56

3.5 SWC REGISTER BITMAP .........................................................................................................56

4.0 General-Purpose Input/Output (GPIO) Port

4.1 OVERVIEW ...............................................................................................................................57

4.2 BASIC FUNCTIONALITY ..........................................................................................................58

4.2.1 Configuration Options ..................................................................................................58

4.2.2 Operation .....................................................................................................................58

4.3 INTERRUPT ASSERTION AND HANDLING ............................................................................59

4.3.1 Interrupt Configuration .................................................................................................59

4.3.2 Interrupt Assertion .......................................................................................................59

4.4 GPIO PORT REGISTERS .........................................................................................................60

4.4.1 GPIO Pin Configuration Access Register ....................................................................60

4.4.2 GPIO Port Runtime Register Map ...............................................................................61

4.4.3 GPIO Data Out Register (GPDO) ................................................................................62

4.4.4 GPIO Data In Register (GPDI) ....................................................................................62

4.4.5 GPIO Interrupt Enable Register (GPIEN) ....................................................................63

4.4.6 GPIO Status Register (GPST) .....................................................................................63

5.0 Fan Speed Control

5.1 OVERVIEW ...............................................................................................................................64

5.2 FUNCTIONAL DESCRIPTION ..................................................................................................64

5.3 FAN SPEED CONTROL REGISTERS ......................................................................................65

5.3.1 Fan Speed Control Register Map ................................................................................65

5.3.2 Fan Control Pre-Scale Register (FCPSR) ...................................................................65

5.3.3 Fan Control Duty Cycle Register (FCDCR) .................................................................65

5.4 FAN SPEED CONTROL BITMAP .............................................................................................66

6.0 Floppy Disk Controller (FDC)

Refer to PC87307, PC87309 or PC87317 datasheet.

7.0 Parallel Port

Refer to PC87307, PC87309 or PC87317 datasheet.

8.0 Serial Port 2 with IR

Refer to PC87307, PC87309 or PC87317 datasheet.

9.0 Serial Port 1

Refer to PC87307, PC87309 or PC87317 datasheet.

10.0 Keyboard and Mouse Controller (KBC)

Refer to PC87307, PC87309 or PC87317 datasheet.

Table of Contents (Continued)

www.national.com

11.0 Device Characteristics

11.1 DC ELECTRICAL CHARACTERISTICS ...................................................................................72

11.1.1 Recommended Operating Conditions .........................................................................72

11.1.2 Absolute Maximum Ratings .........................................................................................72

11.1.3 Capacitance .................................................................................................................72

11.1.4 Power Consumption under Recommended Operating Conditions ..............................73

11.1.5 Input, PCI 5V ...............................................................................................................73

11.1.6 Strap Pin ......................................................................................................................73

11.1.7 Input, TTL Compatible .................................................................................................73

11.1.8 Input with TTL Schmitt Trigger ....................................................................................74

11.1.9 Output, Totem-Pole Buffer ...........................................................................................74

11.1.10 Output, Open-Drain Buffer ...........................................................................................74

11.2 AC ELECTRICAL CHARACTERISTICS ....................................................................................75

11.2.1 AC Test Conditions ......................................................................................................75

11.2.2 Clock Timing ................................................................................................................75

11.2.3 Host Interface I/O Cycle Timing ...................................................................................76

11.2.4 Host Interface DMA Cycle Timing ...............................................................................78

11.2.5 PCICLK Timing Specifications .....................................................................................79

11.2.6 Serial IRQ Timing ........................................................................................................80

11.2.7 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing .............................81

11.2.8 Modem Control Timing ................................................................................................82

11.2.9 FDC Write Data Timing ...............................................................................................82

11.2.10 FDC Drive Control Timing ...........................................................................................83

11.2.11 FDC - Read Data Timing .............................................................................................83

11.2.12 Standard Parallel Port Timing ......................................................................................84

11.2.13 Enhanced Parallel Port Timing ....................................................................................84

11.2.14 Extended Capabilities Port (ECP) Timing ....................................................................85

1.0 Signal/Pin Connection and Description

www.national.com

1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM

Order Number PC87351-xxx/VLA

See NS Package Number VLA128A

Plastic Quad Flatpack (PQFP), JEDEC

xxx = Three character identiﬁer for National data, and keyboard ROM and/or customer identiﬁcation code

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

59585756555453525150494847464544424140

PC87351-xxx/VLA

GA20/GPIO20

VSS

KBCLK

KBDAT

MCLK

VDD

KBRST/GPIO17/P12/PNF

CLKIN

VSS

DR1

DR0

WDATA

MTR1

MTR0

DRATE0

DSKCHG

DIR

INDEX

TRK0

RDATA

DENSEL

WGATE

HDSEL

STEP

PD2/

PD3/

RDATA

PD0/

INDEX

PD4/

DSKCHG

PD5/MSEN0

PD6/DRATE0

PD7/MSEN1

PD1/

TRK0

BUSY/

WAIT/MTR1

AFD/DSTRB/DENSEL

STB/WRITE

ACK/DR1

SLCT/

WGATE

PE/

WDATA

ERR/HDSEL

INIT/DIR

SLIN/ASTRB/STEP

636261

65 66 67

68 69 70

71 72

73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101 102

103

104

105

106

107

108

A10

GPIO11/IRQ5

A15

AEN

IOCHRDY

IORD

IOWR

SERIRQ/IRQ3 PCICLK/IRQ1

DACK2

DACK3

DACK1

DRQ3

DRQ2

DRQ1

VSS

VDD

GPIO14/IRQ9/IRRX2/P17

GPIO15/IRQ11/P12/P17

GPIO16/IRQ12

GPIO12/IRQ6

GPIO13/IRQ7

A11

A12

A13

IRTX

IRRX1

NC NC

GPIO10/IRQ4

A14

GPIO13/RTS2

GPIO14/SOUT2

GPIO12/SIN2

GPIO15/

CTS2

GPIO16/DTR2/BOUT2

MDAT

DCD1

GPIO11/

DSR2

DSR1

SIN1

RTS1

SOUT1

CTS1

BADDR/

DTR1/BOUT1

RI1

GPIO10/

DCD2

VSB

PWUREQ

RI2

VSS

GPIO22/FANOUT1/IRRX2/P17

SUSP/PME2

VBAT

RING/PME1

GPIO21/FANOUT0/P12/PNF

1.0 Signal/Pin Connection and Description (Continued)

www.national.com

SIGNAL/PIN DIRECTORY

1.2 SIGNAL/PIN DIRECTORY

See Table 1-2 for an alphabetical listing of all signals, cross-referenced to additional information for detailed functional descriptions, electrical DC characteristics, and pin multiplexing. The DC characteristics are denoted by a buffer type symbol, described briefly in Table 1-1 and in detail in Sections 11.1.6 to 11.1.10. The pin multiplexing information refers to three different types of multiplexing:

• MUX - Multiplexed functions. Pins are shared between two different functions. Each function is associated with different

board connectivity, and normally, the function selection is determined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the BIOS upon power-up, in order to comply with the board implementation.

• MM - Multiple Mode. Pins have two or more modes of operation within the same function. These modes are associated

with the same external (board) connectivity. Mode selection may be controlled by the device driver, through the registers of the functional block, and do not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O configuration perspective. The mode selection method (registers and bits) as well as the signal specification in each mode, are described within the functional description of the relevant functional blocks.

• PPM - Parallel Port MUX. This special multiplexing of the FDC signals on the Parallel Port pins allows connection of the

external FDC through the Parallel Port connector. This multiplexing is dynamic, controlled by hardware, and does not require any special BIOS setup except for enabling the PPM function. The PPM functionality and a listing of the pins that are multiplexed are described in Section 2.5.

Table 1-1. Buffer Types

Name Description Section

GND Ground pin N/A IN

PCI

Input, PCI 5V 11.1.5

STRP

Input, Strap pin (min VIH is 0.6VDD) with weak pull-down during strap time 11.1.6

Input, TTL compatible 11.1.7

Input, TTL compatible with Schmitt trigger 11.1.8

ULR

Input, with serial UL Resistor N/A

p/n

Output, Totem-Pole buffer that is capable of sourcingpmA and sinkingn mA 11.1.9

Output, Open-Drain output buffer that is capable of sinkingn mA 11.1.10

PWR Power pin N/A

Table 1-2. Signal/Pin Directory

Signal Pin/s

Functional Group DC Characteristics

Multiplexed

Name Section Buffer Type Section

A15-0

28-19, 16-11

Host Interface

1.4.5

11.1.7

ACK

Parallel Por t

1.4.8

11.1.7

PPM

AEN

Host Interface

1.4.5

11.1.7

AFD/DSTRB

Parallel Por t

1.4.8

OD14, O

14/14

11.1.10, 11.1.9

MM/PPM

ASTRB See SLIN/ASTRB BADDR

110

Strapping

1.4.11

STRP

11.1.6

MUX

BOUT1 See

DTR1/BOUT1

BOUT2 See

DTR2/BOUT2

BUSY/

WAIT

Parallel Por t

1.4.8

11.1.7

MM/PPM

CLKIN

Clock

1.4.1

11.1.7

1.0 Signal/Pin Connection and Description (Continued)

SIGNAL/PIN DIRECTORY

www.national.com

CTS1

109

Serial Port 1

1.4.10

11.1.8

CTS2

118

Serial Port 2

1.4.10

11.1.8

MUX

D7-0 10-3 Host Interface 1.4.5

15/24

11.1.7

11.1.9

DACK1-3

50, 52-53

Host Interface

1.4.5

11.1.7

DCD1

104

Serial Port 1

1.4.10

11.1.8

DCD2

112

Serial Port 2

1.4.10

11.1.8

MUX

DENSEL

FDC 1.4.3

, O

4/24

11.1.10, 11.1.9

94 PPM

DIR

FDC 1.4.3

, O

4/24

11.1.10, 11.1.9

90 PPM

DR0

FDC

1.4.3

OD24, O

4/24

11.1.10, 11.1.9

DR1

FDC 1.4.3

, O

4/24

11.1.10, 11.1.9

80 PPM

DRATE0

FDC 1.4.3

6/12

11.1.9

82 PPM

DRQ1-3

47-49

Host Interface

1.4.5

15/24

11.1.9

DSKCHG

FDC 1.4.3

11.1.7

84 PPM

DSR1

105

Serial Port 1

1.4.10

11.1.8

DSR2

113

Serial Port 2

1.4.10

11.1.8

MUX

DSTRB See AFD/DSTRB DTR1/BOUT1

110

Serial Port 1

1.4.10

6/12

11.1.9

DTR2/BOUT2

119

Serial Port 2

1.4.10

6/12

11.1.9

MM/MUX

ERR

Parallel Por t

1.4.8

11.1.7

PPM

FANOUT0

127

Fan Speed Control

1.4.2

2/20

11.1.9

MUX

FANOUT1

128

Fan Speed Control

1.4.2

2/20

11.1.9

MUX

GPIO17-10

98, 37-43 or 112-5, 117-9

GPIO Port 1 1.4.4

OD12, O

6/12

11.1.8

11.1.10, 11.1.9

MUX

GPIO22-20 127-128, 99 GPIO Por t 2 1.4.4

OD12, O

6/12

11.1.8

11.1.10, 11.1.9

MUX

HDSEL

FDC 1.4.3

, O

4/24

11.1.10, 11.1.9

92 PPM

INDEX

FDC 1.4.3

11.1.7

93 PPM

Table 1-2. Signal/Pin Directory (Continued)

Signal Pin/s

Functional Group DC Characteristics

Multiplexed

Name Section Buffer Type Section

1.0 Signal/Pin Connection and Description (Continued)

www.national.com

SIGNAL/PIN DIRECTORY

GA20 99 KBC 1.4.7

11.1.10

MUX

INIT 90 Parallel Port

1.4.8

OD14, O

14/14

11.1.10, 11.1.9

PPM

IOCHRDY

Host Interface

1.4.5

11.1.10

IORD

Host Interface

1.4.5

11.1.7

IOWR

Host Interface

1.4.5

11.1.7

IRQ1, 3-7, 9, 11-12

34, 35, 37-43 Host Interface 1.4.5

OD24, O

15/24

11.1.7

11.1.10, 11.1.9

MUX

IRRX1

Infrared

1.4.5

11.1.7

IRRX2/IRSL0 41, 128 Infrared 1.4.5

6/12

11.1.7

11.1.9

MM/MUX

IRRX2 See IRRX2/IRSL0 IRSL0 See IRRX2/IRSL0 IRTX

Infrared

1.4.5

6/12

11.1.9

KBCLK 100

Wake-Up KBC

1.4.12

1.4.7

11.1.7

11.1.10

KBDAT 101

Wake-Up KBC

1.4.12

1.4.7

11.1.7

11.1.10

KBRST 98 KBC 1.4.7

11.1.10

MUX

MCLK 102

Wake-Up KBC

1.4.12

1.4.7

11.1.7

11.1.10

MDAT 103

Wake-Up KBC

1.4.12

1.4.7

11.1.7

11.1.10

Host Interface

1.4.5

11.1.8

MSEN0

FDC

1.4.3

11.1.7

PPM

MSEN1

FDC

1.4.3

11.1.7

PPM

MTR0

FDC

1.4.3

OD24, O

4/24

11.1.10, 11.1.9

MTR1

FDC 1.4.3

, O

4/24

11.1.10, 11.1.9

79 PPM

P12 42, 98, 127 KBC 1.4.7

11.1.10

MUX

P17 41, 42, 128 KBC 1.4.7

11.1.10

MUX

PCICLK

Host Interface

1.4.5

11.1.7

MUX

PD7-0

81-84, 87, 89, 91, 93

Parallel Por t 1.4.8

OD14, O

14/14

11.1.7

11.1.10, 11.1.9

PPM

Parallel Por t

1.4.8

11.1.7

PPM

PME1

125

Wake-Up

1.4.12

11.1.8

MUX

PME2

126

Wake-Up

1.4.12

11.1.8

MUX

Table 1-2. Signal/Pin Directory (Continued)

Signal Pin/s

Functional Group DC Characteristics

Multiplexed

Name Section Buffer Type Section

1.0 Signal/Pin Connection and Description (Continued)

SIGNAL/PIN DIRECTORY

www.national.com

PNF

98, 127

Parallel Por t

1.4.8

11.1.7

MUX

PWUREQ

124

Wake-Up

1.4.12

11.1.10

RDATA

FDC 1.4.3

11.1.7

87 PPM

RI1 111

Wake-Up Serial Port 1

1.4.12

1.4.10

11.1.8

RI2 120

Wake-Up Serial Port 2

1.4.12

1.4.10

11.1.8

RING

125

Wake-Up

1.4.12

11.1.8

MUX

RTS1

107

Serial Port 1

1.4.10

6/12

11.1.9

RTS2

115

Serial Port 2

1.4.10

6/12

11.1.9

MUX

SERIRQ 35 Host Interface 1.4.5

15/24

11.1.8

11.1.9

MUX

SIN1

106

Serial Port 1

1.4.10

11.1.8

SIN2

114

Serial Port 2

1.4.10

11.1.8

MUX

SLCT

Parallel Por t

1.4.8

11.1.7

PPM

SLIN/ASTRB

Parallel Por t

1.4.8

OD14, O

14/14

11.1.10, 11.1.9

MM/PPM

SOUT1

108

Serial Port 1

1.4.10

6/12

11.1.9

SOUT2

117

Serial Port 2

1.4.10

6/12

11.1.9

MUX

STEP

FDC 1.4.3

, O

4/24

11.1.10, 11.1.9

88 PPM

STB/WRITE

Parallel Por t

1.4.8

OD14, O

14/14

11.1.10, 11.1.9

SUSP

126

Wake-Up

1.4.12

11.1.8

MUX

Host Interface

1.4.5

11.1.7

TRK0

FDC 1.4.3

11.1.7

91 PPM

BAT

122

Power and Ground

1.4.11

ULR

N/A

17, 86

Power and Ground

1.4.9 PWR N/A

123

Power and Ground

1.4.12 PWR N/A

18, 51, 85, 116

Power and Ground 1.4.12 GND N/A

WAIT See BUSY/WAIT

WDATA

FDC 1.4.3

, O

4/24

11.1.10, 11.1.9

78 PPM

Table 1-2. Signal/Pin Directory (Continued)

Signal Pin/s

Functional Group DC Characteristics

Multiplexed

Name Section Buffer Type Section

1.0 Signal/Pin Connection and Description (Continued)

www.national.com

PIN MULTIPLEXING

1.3 PIN MULTIPLEXING

There are three categories of pins with multiple names: Multiplexed (MUX), Multiple Mode (MM) and Parallel Port MUX (PPM). See Section 1.2 for descriptions of these categories. All the multiplexing options in the MUX category and their associated setup configuration are described in Table 1-3. A multiplexing option may be chosen on one pin only per group.

WGATE

64 FDC

1.4.3

, O

4/24

11.1.10, 11.1.9

77 PPM

FDC 1.4.3

11.1.7

89 PPM

WRITE See STB/WRITE

Table 1-3. Pin Multiplexing Conﬁguration

Default Alternate

Signal I/O Conﬁguration Signal I/O Conﬁguration

34 PCICLK I SIOCF2, Bit 0 = 0 IRQ1 I/O SIOCF2, Bit 0 = 1 35 SERIRQ I/O SIOCF2, Bit 0 = 0 IRQ3 I/O SIOCF2, Bit 0 = 1 37 GPIO10

I/O SIOCF2, Bit 0 = 0

IRQ4

I/O SIOCF2, Bit 0 = 1

38 GPIO11 IRQ5 39 GPIO12 IRQ6 40 GPIO13 IRQ7 43 GPIO16 IRQ12 41 GPIO14

I/O

SIOCF2, Bits 2-1 = 00 or Bits 2-0 = 011

IRQ9 I/O SIOCF2, Bits 2-0 = 010 IRRX2/IRSL0 I/O SIOCF2, Bits 2-1 = 10 P17 I/O SIOCF2, Bits 2-1 = 11

42 GPIO15

I/O

SIOCF2, Bits 4-3 = 00 or Bits 4-3, 0 = 011

IRQ11 O SIOCF2, Bits 4-3, 0 = 010 P12 I/O SIOCF2, Bits 4-3 = 10 P17 I/O SIOCF2, Bits 4-3 = 11

98 KBRST

I/O SIOCF2, Bits 6-5 = 01

GPIO17 I/O SIOCF2, Bits 6-5 = 00 P12 I/O SIOCF2, Bits 6-5 = 10 PNF I/O SIOCF2, Bits 6-5 = 11

99 GA20 I/O SIOCF2, Bit 7 = 1 GPIO20 I/O SIOCF2, Bit 7 = 0

Table 1-2. Signal/Pin Directory (Continued)

Signal Pin/s

Functional Group DC Characteristics

Multiplexed

Name Section Buffer Type Section

1.0 Signal/Pin Connection and Description (Continued)

DETAILED SIGNAL/PIN DESCRIPTIONS

www.national.com

1.4 DETAILED SIGNAL/PIN DESCRIPTIONS

1.4.1 Clock

1.4.2 Fan Speed Control

1.4.3 FDC (Including PPM)

The Parallel-Port/FDC MUX (PPM) provides a means to connect an external FDD on the Parallel Por t connector, in addition to the internal FDD on the FDC header. This is done by physically connecting internally each FDC pin to a corresponding Parallel Por t pin while isolating it from the Parallel Port logic. The Parallel Port becomes an additional connecting point to the FDC interface as long as the PPM is in active mode. The functional descriptions in this table apply to both the FDC pin and to the corresponding PPM pin. For a detailed description of PPM functionality, see Section 2.5.

112 GPIO10

I/O SIOCF3, Bit 0 = 0

DCD2 I

SIOCF3, Bit 0 = 1

113 GPIO11

DSR2 I 114 GPIO12 SIN2 I 115 GPIO13

RTS2 O 117 GPIO14 SOUT2 O 118 GPIO15

CTS2 I 119 GPIO16

DTR2/BOUT2 O 125

RING I SIOCF4, Bit 0 = 0 PME1 I SIOCF4, Bit 0 = 1

126

SUSP I SIOCF4, Bit 2 = 0 PME2 I SIOCF4, Bit 2 = 1

127 GPIO21

I/O SIOCF3, Bits 2-1 = 00

FANOUT0 I/O SIOCF3, Bits 2-1 = 01

P12 I/O SIOCF3, Bits 2-1 = 10

PNF I/O SIOCF3, Bits 2-1 = 11 128 GPIO22

I/O SIOCF3, Bits 4-3 = 00

FANOUT1 I/O SIOCF3, Bits 4-3 = 01

IRRX2/IRSL0 I/O SIOCF3, Bits 4-3 = 10

P17 I/O SIOCF3, Bits 4-3 = 11

Signal Pin/s I/O Buffer Type Description

CLKIN 45 I IN

Clock In. A 48MHz clock input.

Signal Pin/s I/O Buffer Type Description

FANOUT0 FANOUT1

127, 128

2/20

Fan Output 0, 1. Pulse Width Modulation (PWM) signals, that are used to control the speed of cooling fans by controlling the voltage supplied to the fan’s motor.

Table 1-3. Pin Multiplexing Conﬁguration (Continued)

Default Alternate

Signal I/O Conﬁguration Signal I/O Conﬁguration

1.0 Signal/Pin Connection and Description (Continued)

www.national.com

DETAILED SIGNAL/PIN DESCRIPTIONS

Signal Pin/s I/O Buffer Type Description

DENSEL 74 O O

4/24

Density Select. Indicates that a high FDC density data rate (500 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is selected. DENSEL polarity is controlled by bit 5 of the FDC Conﬁguration Register.

94 This pin provides an additional density select signal in PPM mode when

PNF = 0.

DIR 67 O OD24-O

4/24

Direction. Determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in, inactive = step out) during a seek operation. During reads or writes,

DIR is inactive.

90 This pin provides an additional direction signal in PPM mode when

PNF = 0.

DR0 69 O OD24-O

4/24

Drive Select 0. Decoded drive select output signal. DR0 is controlled by Digital Output Register (DOR) bit 0.

DR1 70 O OD24-O

4/24

Drive Select 1. Decoded drive select output signal. DR1 is controlled by Digital Output Register (DOR) bit 1.

80 This pin provides an additional drive select 1 signal in PPM mode when

PNF = 0.

DRATE0 73 O O

6/12

Data Rate 0. Reflects the value of bit 0 of the Conﬁguration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last. Output from the pin is totem-pole buffered.

82 This pin provides an additional FDC data rate signal in PPM mode, when

PNF = 0.

DSKCHG 59 I IN

Disk Change. Indicates if the drive door has been opened. The state of this pin is stored in the Digital Input Register (DIR). This pin can also be conﬁgured as the RGATE data separator diagnostic input signal via the MODE command.

84 This pin provides an additional FDC Disk Change signal in PPM Mode

when PNF = 0.

HDSEL 60 O OD24, O

4/24

Head Select. Determines which side of the FDD is accessed. Active low selects side 1, inactive selects side 0.

92 This pin provides an additional head select signal in PPM mode when

PNF = 0.

INDEX 72 I IN

Index. Indicates the beginning of an FDD track.

93 This pin provides an additional index signal in PPM mode when PNF = 0.

MSEN0, MSEN1

82, 80

IIN

Media Sense Signals 0 and 1. Provide media sense signals only in PPM mode when PNF = 0.

MTR0 71 O OD24, O

4/24

Motor Select 0. Active low, motor enable line for drive 0, controlled by bits D7-4 of the Digital Output Register (DOR).

This signal is not available on the PPM, assuming that the exter nal FDD is either drive 1 or 3.

MTR1 68 O OD24, O

4/24

Motor Select 1. Active low, motor enable line for drive 1, controlled by bits D7-4 of the Digital Output Register (DOR).

79 This pin provides an additional motor select 1 signal in PPM mode when

PNF = 0. This pin is the motor enable line for drive 1 or drive 0, according to the TDR Register.

RDATA61 I IN

Read Data. Raw serial input data stream read from the FDD.

87 This pin provides an additional read data signal in PPM mode when PNF = 0.

1.0 Signal/Pin Connection and Description (Continued)

DETAILED SIGNAL/PIN DESCRIPTIONS

www.national.com

1.4.4 General-Purpose Input/Output (GPIO) Ports

STEP 66 O OD24, O

4/24

Step. Issues pulses to the disk drive at a software programmable rate to move the head during a seek operation.

88 This pin provides an additional step signal in PPM mode when PNF = 0.

TRK0 63 I IN

Track 0. Indicates to the controller that the head of the selected floppy disk drive is at track 0.

91 This pin provides an additional Track 0 signal in PPM Mode when PNF = 0.

WDATA65 OOD24, O

4/24

Write Data. Carries out the write pre-compensated serial data that is written to the selected floppy disk drive. Pre-compensation is software selectable.

78 This pin provides an additional

WDATA signal in PPM mode when PNF = 0.

WGATE 64 O OD24, O

4/24

Write Gate. Enables the write circuitry of the selected disk drive. WGATE is designed to prevent glitches during power up and power down. This prevents writing to the disk when power is cycled.

77 This pin provides an additional

WGATE signal in PPM mode when PNF = 0.

WP 62 I IN

Write Protected. Indicates that the disk in the selected drive is write protected. A software programmable conﬁguration bit (FDC conﬁguration at Index F0h, Logical Device 0) can force an active write-protect indication to the FDC regardless of the status of this pin.

89 This pin provides an additional

WP signal in PPM mode when PNF = 0.

Signal Pin/s I/O Buffer Type Description

GPIO17 GPIO16-109843-37

I/O IN

, O

6/12

General-Purpose I/O Port 1, bits 0-7. Each pin is configured independently as input or I/O, with or without static pull-up, and with either open-drain or totem-pole output type. The port support interrupt assertion and each pin can be enabled or masked as interrupt source.

GPIO 16-10 119-117,

115-112

These pins provide alternate GPIO location options.

GPIO22-20 128,

127, 99

I/O IN

12, O6/12

General-Purpose I/O Port 2, bits 0-2. Same as Port 1.

Signal Pin/s I/O Buffer Type Description

1.0 Signal/Pin Connection and Description (Continued)

www.national.com

DETAILED SIGNAL/PIN DESCRIPTIONS

1.4.5 Host Interface

1.4.6 Infrared (IR)

Signal Pin/s I/O Buffer Type Description

A15-A0 11-16,

19-28

IIN

Address. These address lines of the ISA bus determine which internal register is accessed. A15-A0 are don’t cares during DMA transfer.

AEN 29 I IN

Address Enable. This input disables function selection via A15-A0 when it is high. Access during DMA transfer is NOT affected by this pin.

D7-D0 45 I/O INT/O

15/24

Data. Bi-directional data lines of the ISA bus. D7 is the MSB and D0 is the LSB.

DACK1-3 50, 52,53IIN

DMA Acknowledge 1, 2 and 3. These active low signals acknowledge a request for DMA services and enable the

IORD and the IOWR input

signals during DMA transfer.

DRQ1-3 47-49 O O

15/24

DMA Request 1, 2, and 3. These active high output signals inform the DMA controller that a data transfer is needed.

IOCHRDY 30 O OD

I/O Channel Ready. This is the I/O channel ready open drain output signal. When IOCHRDY is driven low, the EPP extends the host cycle.

IORD 31 I IN

I/O Read. An active low RD input signal indicates that the microprocessor has read data.

IOWR 32 I IN

I/O Write. WR is an active low input signal that indicates a write operation from the microprocessor to the controller.

IRQ1,3-7, 9, 11-12

34,35, 37-43

I/O INT/

, O

15/24

Interrupt Request 1, 3-7, 9, 11-12. IRQ polarity and output type selection is software conﬁgurable by the logical device mapped to the IRQ line.

MR 46 I IN

Master Reset. An active high MR input signal resets the device with its default settings.

PCICLK 34 I IN

PCI

PCI Clock. Up to 33 MHz.

SERIRQ 35 I/O IN

T/O15/24

Serial IRQ. Encoded interrupts on a serial line.

TC 54 I IN

DMA Terminal Count. The DMA controller issues TC to indicate the termination of a DMA transfer. TC is accepted only when a

DACK signal is

active. TC is active high in PC-AT mode, and active low in PS/2 mode.

Signal Pin/s I/O Buffer Type Description

IRRX1 57 I IN

IR Reception 1. Primary input to receive serial data from the IR transceiver module.

IRRX2/ IRSL0

41, 128 I/O INT/O

6/12

IRRX2 - IR Reception 2. Auxiliary IR receiver input to support two transceiver modules.

IRSL0 - IR Control Signals 0. Output to control the IR analog front end.

IRTX 56 O O

6/12

IR Transmit. IR serial output data.

1.0 Signal/Pin Connection and Description (Continued)

DETAILED SIGNAL/PIN DESCRIPTIONS

www.national.com

1.4.7 Keyboard and Mouse Controller (KBC)

Signal Pin/s I/O Buffer Type Description

GA20 99 I/O IN

/OD

Gate A20. KBC gate A20 (P21) output.

KBCLK 100 I/O IN

/OD

Keyboard Clock. Transfers the keyboard clock between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P26 signal, and is connected internally to the T0 signal of the KBC. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. However, to enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage.

KBDAT 101 I/O IN

/OD

Keyboard Data. Transfers the keyboard data between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P27 signal, and is connected internally to KBC P10. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity, it must be pulled up to Keyboard and Mouse standby voltage.

KBRST 98 I/O IN

/OD

KBD Reset. Keyboard Reset (P20) output.

MCLK 102 I/O IN

/OD

Mouse Clock. Transfers the mouse clock between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P23 signal, and is connected internally to KBC’s T1. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity, it must be pulled up to Keyboard and Mouse standby voltage.

MDAT 103 I/O IN

/OD

Mouse Data. Transfers the mouse data between the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P22 signal, and is connected internally to KBC’s P11. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity, it must be pulled up to Keyboard and Mouse standby voltage.

P12 42, 98,

127

I/O IN

/OD

I/O Port. KBC open-drain signal for general-purpose input and output, controlled by KBC ﬁrmware.

P17 41, 42,

128

I/O INTS/OD

I/O Port. KBC open-drain signal for general-purpose input and output, controlled by KBC ﬁrmware.

1.0 Signal/Pin Connection and Description (Continued)

www.national.com

DETAILED SIGNAL/PIN DESCRIPTIONS

1.4.8 Parallel Port

1.4.9 Power and Ground

Signal Pin/s I/O Buffer Type Description

ACK 80 I IN

Acknowledge. Pulsed low by the printer to indicate that it has received data from the Parallel Por t.

AFD/ DSTRB

94 O OD

, O

14/14

AFD - Automatic Feed. When low, instructs the printer to automatically feed a line after printing each line. This pin is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pullup resistor should be attached to this pin.

DSTRB - Data Strobe (EPP). Active low, used in EPP mode as a data strobe.

BUSY/WAIT 79 I IN

Busy. Set high by the printer when it cannot accept another character. Wait. In EPP mode, the Parallel Port device uses this active low signal to

extend its access cycle.

ERR 92 I IN

Error. Set active low by the printer when it detects an error.

INIT 90 O OD14-O

14/14

Initialize. When low, initializes the printer. This signal is in TRI-STATE after a 1 is loaded into the corresponding control register bit. Use an external 4.7 KΩ pull-up resistor.

PD7-0 81-84,

87, 89, 91, 93

I/O IN

, O

14/14

Parallel Port Data. Transfer data to and from the peripheral data bus and the appropriate Parallel Port data register. These signals have a high current drive capability.

PE 78 I IN

Paper End. Set high by the printer when it is out of paper. This pin has an internal weak pull-up or pull-down resistor.

PNF 98, 127 I IN

Printer Not Floppy. This input from the Parallel Port connector is used to detect that a ﬂoppy drive is connected to the Parallel Port, and to activates the PPM. The PNF pin is driven to 1 when a parallel device is connected, and to 0 when external FDD is connected. This pin is functional only when the PPM mode is enabled.

SLCT 77 I IN

Select. Set active high by the printer when the printer is selected.

SLIN/ ASTRB

88 O OD

, O

14/14

SLIN - Select Input. When low, selects the printer. This signal is in TRISTATE after a 0 is loaded into the corresponding control register bit. Uses an external 4.7 KΩ pull-up resistor.

ASTRB - Address Strobe (EPP). Active low, used in EPP mode as an address strobe.

STB/ WRITE

95 O OD

, O

14/14

STB - Data Strobe. Indicates to the printer that valid data is available at the printer port. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be employed.

WRITE - Write Strobe. In EPP mode, this active low signal is a write strobe.

Signal Pin/s Buffer Type Description

BAT

122 IN

ULR

Battery Power Supply. Provides battery back-up to the System Wake-Up Control registers, when V

is lost (power-fail). The pin is connected to the

internal logic through a series resistor for UL protection.

17, 86 PWR Main 5V Power Supply.

123 PWR Standby Power Supply. Provides 5V power to the Wake-Up Control circuitry,

while the main power supply is turned off.

18, 51, 85, 116

GND Ground.

1.0 Signal/Pin Connection and Description (Continued)

DETAILED SIGNAL/PIN DESCRIPTIONS

www.national.com

1.4.10 Serial Ports 1 and 2

1.4.11 Strapping

1.4.12 System Wake-Up Control

Signal Pin/s I/O Buffer Type Description

CTS1, CTS2

109, 118

IIN

Clear to Send. When low, indicate that the modem or other data transfer device is ready to exchange data.

DCD1, DCD1

3, 94

IIN

Data Carrier Detected. When low, indicate that the modem or other data transfer device has detected the data carrier.

DSR1, DSR2

105, 113

IIN

Data Set Ready. When low, indicate that the data transfer device, e.g., modem, is ready to establish a communications link.

DTR1/ BOUT1,

DTR2/ BOUT2

110,

119

6/12

Data Terminal Ready. When low, indicate to the modem or other data transfer device that the Serial Port is ready to establish a communications link. After system reset, these pins provides the

DTR function, sets these

signals to inactive high, and loopback operation holds them inactive. Baud Output. Provides the associated serial channel baud rate generator

output signal if test mode is selected, i.e., bit 7 of the EXCR1 Register is set.

DTR1/BOUT1 is used also as BADDR.

RI1, RI2

111, 120

IIN

Ring Indicators (Modem). When low, indicate that a telephone ring signal has been received by the modem. These pins may issue wake-up event.

RTS1, RTS2

107, 115

6/12

Request to Send. When low, indicate to the modem or other data transfer device that the corresponding Serial Port is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them inactive.

SIN1, SIN2

106, 114

IIN

Serial Input. Receive composite serial data from the communications link (peripheral device, modem or other data transfer device).

SOUT1, SOUT2

108, 117

6/12

Serial Output. Send composite serial data to the communications link (peripheral device, modem or other data transfer device). The SOUT2,1 signals are set active high after system reset.

Signal Pin/s I/O Buffer Type Description

BADDR 110 I IN

STRP

Base Address Strap. Determines the base address of the Index and Data registers. It is pulled down by an internal 30 Kohm resistor to get base address 2Eh for the Index register, and 2Fh for the Data register. If the respective base addresses are 15Ch and 15Dh, use an external 10 Kohm pull-up resistor (to V

Signal Pin/s I/O Buffer Type Description

PME1, PME2

125, 126

IIN

Power Management Event 1, 2. Detection of an event on PME1 or PME2 may activate the

PWUREQ signal (wake-up event).

PWUREQ 124 O OD

6/12

Power Up Request. Low level (active) indicates that wake-up event has occurred. This may cause the chipset to turn the power supply on, or to exit its current sleep state. The open-drain output must be pulled up to V

SB,

in order to function during power-off.

RING 125 I IN

Telephone Line Ring. Detection of a pulse-train on the RING pin, is a wake-up event that can activate the power-up request (

PWUREQ).

SUSP 126 I IN

Suspend Power. Power Supply On control signal.

www.national.com

2.0 Device Architecture and Configuration

2.0 Device Architecture and Conﬁguration

The SuperI/O device comprises a collection of generic functional blocks. Each functional block is described in a separate chapter in this book. However, some parameters in the implementation of each functional block may vary per SuperI/O device. This chapter describes the PC87351 structure and provides all device specific information, including special implementation of generic blocks, host interface and device configuration.

2.1 OVERVIEW

The PC87351 consists of 9 logical devices, a host interface, and a central configuration register set, all built around a central, internal bus. The internal bus is a replication of an 8-bit ISA bus protocol.

The host interface serves as a bridge between the external ISA interface and the internal bus. It supports 8-bit I/O read, 8bit I/O write and 8-bit DMA transactions, as defined in

Personal Computer Bus Standard P996

The central configuration register set supports ACPI compliant PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard Registers, defined in Appendix A of the

Plug and Play ISA Specification

Version

1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA channels and IRQ lines) are configured in, and managed by, the central configuration register set. In addition, some function-specific parameters are configurable through this unit and distributed to the functional blocks through special control signals.

Figure 2-1. Detailed PC87351 Block Diagram

DRATE0

CLKIN

BADDR

SIN1 SOUT1

RTS1

DTR1/BOUT1

CTS1 DSR1 DCD1

RI1

RDATA

WDATA

WGATE

HDSEL

DIR

STEP TRK0

INDEX

DSKCHG

MTR1,0

DR1,0

DENSEL

P12,P17 GA20, KBRST KBCLK

KBDAT

MDAT MCLK

Keyboard

with IR

IRRX2,1 IRTX IRSL0

RING

PWUREQ

Fan Speed

Serial Port 1

PD7/MSEN1

SLIN/STEP/ASTRB

PD0/INDEX

PD1/

TRK0

PD2/

PD3/

RDATA

PD4/

DSKCHG

PD5/MSEN0

PD6/DRATE0

PNF

ACK/DR1

BUSY/MTR1/WAIT

PE/WDATA

SLCT/WGATE

AFD/DENSEL/DSTRB

ERR/HDSEL

INIT/DIR

STB/WRITE

and

Mouse

Controller

and Control

Registers

System

Wake-Up

Control

PCICLK

D7-0

DACK3-1 DRQ3-1

SERIRQ

GPIO Ports

GPIO22-20

GPIO17-10

Internal Bus

Parallel

Port

FANOUT0

FDC

Host Interface

Control Signals

FANOUT1

A15-0

AEN

IOCHRDY

IORD

IOWR

IRQ9,11-12 IRQ1,3-7

SIN2 SOUT2

RTS2 DTR2/BOUT2

CTS2 DSR2 DCD2

RI2

Serial

Port 2

PME1

PME2

SUSP

BAT

Conﬁguration

PPM

2.0 Device Architecture and Configuration (Continued)

CONFIGURATION STRUCTURE AND ACCESS

www.national.com

2.2 CONFIGURATION STRUCTURE AND ACCESS

This section describes the structure of the configuration register file, and the method of accessing the configuration registers.

2.2.1 The Index-Data Register Pair

The SuperI/O configuration access is performed via an Index-Data register pair, using only two system I/O byte locations. The base address of this register pair is determined during reset, according to the state of the hardware strapping option on the BADDR pin. Table 2-1 shows the selected base addresses as a function of BADDR.

Table 2-1. BADDR Strapping Options

The Index Register is an 8-bit R/W register located at the selected base address (Base+0). It is used as a pointer to the configuration register file, and holds the index of the configuration register that is currently accessible via the Data Register. Reading the Index Register returns the last value written to it (or the default of 00h after reset).

The Data Register is an 8-bit virtual register, used as a data path to any configuration register. Accessing the data register results with physically accessing the configuration register that is currently pointed by the index register.

2.2.2 Banked Logical Device Registers

Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks, where each bank holds the standard PnP configuration registers of the corresponding logical device. Table 2-2 shows the LDNs of the device functional blocks.

Figure 2-2 shows the structure of the standard PnP configuration register file. The SIO Control and Configuration registers are not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and device configuration registers are duplicated over 9 banks for 9 logical devices. Therefore, accessing a specific register in a specific bank is performed by two dimensional indexing, where the LDN Register selects the bank (or logical device) and the Index Register selects the register within the bank. Accessing the Data Register while the Index Register holds a value of 30h or higher results in a physical access to the configuration register currently pointed to by the Index Register, within the logical device currently selected by the LDN Register.

Figure 2-2. Structure of the PnP Standard Registers

BADDR

I/O Address

Index Register Data Register

0 002Eh 002Fh 1 015Ch 015Dh

07h 20h

30h 60h

75h

F2h

Logical Device Number Register SuperI/O Configuration Registers

Logical Device Control Register

Logical Device Configuration

Special (Vendor-defined) Registers

9 Banks - One per

Logical Device

2Eh

F0h

Bank Select

63h

74h

70h 71h

PnP Standard Registers

2.0 Device Architecture and Configuration (Continued)

www.national.com

CONFIGURATION STRUCTURE AND ACCESS

Table 2-2. Logical Device Number (LDN) Assignments

When accessing unimplemented registers (i.e. accessing the Data Register while the Index Register points to a non-existing register or the LDN is higher than 08h), write is ignored and read returns 00h on all addresses except for 74h, 75h (PnP DMA Configuration Registers) which returns 04h (no DMA channel is active). The configuration registers are accessible immediately after reset.

2.2.3 Standard PnP Register Definitions

Tables 2-3 through 2-8 describe the standard PnP registers. For more detailed information on these registers, refer to the

Plug and Play ISA Specification,

Version 1.0a, May 5, 1994.

Unless otherwise noted:

• All registers are read/write.

• All reserved bits return 0 on reads. To prevent unpredictable results, they must not be modified. Using read-modify-

write is recommended to prevent the values of reserved bits from being changed during write.

• Write only registers should not use read-modify-write during updates.

Table 2-3. PnP Standard Control Registers

Table 2-4. PnP Logical Device Control Registers

LDN Functional Block

00h Floppy Disk Controller (FDC) 01h Parallel Port 02h Serial Port 2 with IR 03h Serial Port 1 04h System Wake-Up Control (SWC) 05h Keyboard and Mouse Controller (KBC) - Mouse interface 06h Keyboard and Mouse Controller (KBC) - Keyboard interface 07h General-Purpose I/O (GPIO) 08h Fan Speed Control (FSC)

Index Name Description

07h Logical Device

Number

This register selects the current logical device.

20h - 2Fh SuperI/O

Conﬁguration

Registers

SuperI/O Conﬁguration Registers and ID Registers

Index Name Description

30h Activate Bit 0 - Logical Device Activation Control

0: Disabled 1: Enabled

Bits 7-1 - Reserved

+ 60 hidden pages