NSC PC87312VF Datasheet

PC87311A/PC87312 (SuperI/OTMII/III)
Floppy Disk Controller with Dual UARTs,
Parallel Port, and IDE Interface

General Description

The PC87311A/12 incorporates a floppy disk controller
(FDC), two full function UARTs, a bidirectional parallel port,
and IDE interface control logic in one chip. The PC87311A
includes standard AT/XT address decoding for on-chip
functions and a Configuration Register, offering a single
chip solution to the most commonly used IBM
PC-XT

, and PC-ATÉperipherals. The PC87312 includes

É

standard AT address decoding for on-chip functions and a
Configuration Register set, offering a single chip solution to
the most commonly used ISA, EISA and Micro Channel pe­ripherals.

The on-chip FDC is software compatible to the PC8477,
which contains a superset of the DP8473 and NEC mPD765
and the N82077 floppy disk controller functions. The on­chip analog data separator requires no external compo­nents and supports the 4 Mb drive format as well as the
other standard floppy drives used with 5.25
dia.

In the PC87311A, the UARTs are equivalent to two
INS8250N-Bs or NS16450s. The bidirectional parallel port
maintains complete compatibility with the IBM PC, XT and
AT. In the PC87312 the UARTs are equivalent to two
NS16450s or PC16550s. The bidirectional parallel port
maintains complete compatibility with the ISA, EISA and Mi­cro Channel parallel ports.

The IDE control logic provides a complete IDE interface ex­cept for the signal buffers. The Configuration Registers con­sist of three byte-wide registers. An Index and a Data Regis­ter which can be relocated within the ISA I/O address space
access the Configuration Registers.

ÉPCÉ

and 3.5×me-

×

Features

Y

100% compatible with IBM PC, XT, and AT architec­tures (PC87311A), or ISA, EISA, and Micro Channel ar­chitectures (PC87312)

Y

FDC:
Ð Software compatible with the DP8473, the 765A and

,

the N82077
Ð 16-byte FIFO (default disabled)
Ð Burst and Non-Burst modes
Ð Perpendicular Recording drive support
Ð High performance internal analog data separator (no

external filter components required)
Ð Low power CMOS with power down mode

Y

UARTs:
Ð Software compatible with the INS8250N-B and the

NS16450 (PC87311A), or PC16550A and PC16450

(PC87312)

Y

Parallel Port:
Ð Bidirectional under either software or hardware

control
Ð Compatible with all IBM PC, XT and AT architectures

(PC87311A), or all ISA, EISA, and Micro Channel ar-

chitectures (PC87312)
Ð Back Voltage protection circuit against damage

caused when printer is powered up

Y

IDE Control Logic:
Ð Provides a complete IDE interface except for option-

al buffers

Y

Address Decoder:
Ð Provides selection of all primary and secondary ISA

addresses including COM 1 –4.

Y

100-pin PQFP package
Ð The PC87311A and PC87312 are pin compatible

October 1993

PC87311A/PC87312 (SuperI/O II/III) Floppy Disk Controller

with Dual UARTs, Parallel Port, and IDE Interface

Block Diagram

TL/F/11362– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

TM

SuperI/O

is a trademark of National Semiconductor Corporation.

IBM

,PCÉ, PC-ATÉ, PC-XTÉand PS/2Éare registered trademarks of International Business Machines Corporation.

É

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/F/11362

Table of Contents

1.0 PIN DESCRIPTION ААААААААААААААААААААААААААААААА6

2.0 CONFIGURATION REGISTERS АААААААААААААААААА12

2.1 Overview ААААААААААААААААААААААААААААААААААААА12

2.2 Software Configuration ААААААААААААААААААААААААА12

2.3 Hardware Configuration АААААААААААААААААААААААА12

2.4 Index and Data Registers ААААААААААААААААААААААА14

2.5 Base Configuration Registers ААААААААААААААААААА14

2.5.1 Function Enable Register (FER) АААААААААААА14

2.5.2 Function Address Register (FAR) ААААААААААА16

2.5.3 Power and Test Register (PTR)ААААААААААААА16

2.6 Power Down Options АААААААААААААААААААААААААА16

2.7 Power Up Procedure and Considerations ААААААААА17

2.7.1 Crystal Stabilization ААААААААААААААААААААААА17

2.7.2 UART Power-Up ААААААААААААААААААААААААА17

2.7.3 FDC Power-Up ААААААААААААААААААААААААААА17

3.0 FDC REGISTER DESCRIPTION АААААААААААААААААА17

3.1 Status Register A (SRA) АААААААААААААААААААААААА18

3.1.1 SRAРPS/2 Mode АААААААААААААААААААААААА19

3.1.2 SRAРModel 30 Mode АААААААААААААААААААА19

3.2 Status Register B (SRB) АААААААААААААААААААААААА19

3.2.1 SRBРPS/2 Mode АААААААААААААААААААААААА19

3.2.2 SRBРModel 30 Mode АААААААААААААААААААА19

3.3 Digital Output Register (DOR) ААААААААААААААААААА20

3.4 Tape Drive Register (TDR)АААААААААААААААААААААА20

3.5 Main Status Register (MSR) АААААААААААААААААААА20

3.6 Data Rate Select Register (DSR) АААААААААААААААА21

3.7 Data Register (FIFO)ААААААААААААААААААААААААААА22

3.8 Digital Input Register (DIR) ААААААААААААААААААААА22

3.8.1 DIRРPC-AT Mode ААААААААААААААААААААААА22

3.8.2 DIRРPS/2 Mode АААААААААААААААААААААААА22

3.8.3 DIRРModel 30 Mode ААААААААААААААААААААА22

3.9 Configuration Control Register (CCR) АААААААААААА23

3.9.1 CCRРPC-AT and PS/2 Modes АААААААААААА23

3.9.2 CCRРModel 30 Mode АААААААААААААААААААА23

3.10 Result Phase Status Registers ААААААААААААААААА23

3.10.1 Status Register 0 (ST0) ААААААААААААААААА23

3.10.2 Status Register 1 (ST1) ААААААААААААААААА23

3.10.3 Status Register 2 (ST2) ААААААААААААААААА24

3.10.4 Status Register 3 (ST3) ААААААААААААААААА24

4.0 FDC COMMAND SET DESCRIPTION ААААААААААААА24

4.1 Command Set Summary ААААААААААААААААААААААА24

4.2 Command Description ААААААААААААААААААААААААА28

4.2.1 Configure Command АААААААААААААААААААААА28

4.2.2 Dumpreg Command АААААААААААААААААААААА29

4.2.3 Format Track CommandААААААААААААААААААА29

4.2.4 Invalid CommandААААААААААААААААААААААААА32

4.2.5 Lock Command АААААААААААААААААААААААААА32

4.2.6 Mode Command ААААААААААААААААААААААААА32

4.2.7 NSC Command АААААААААААААААААААААААААА33

4.2.8 Perpendicular Mode CommandААААААААААААА33

4.2.9 Read Data Command ААААААААААААААААААААА34

4.2.10 Read Deleted Data Command АААААААААА36

4.2.11 Read ID Command АААААААААААААААААААА36

4.2.12 Read A Track Command ААААААААААААААА36

4.2.13 Recalibrate Command ААААААААААААААААА36

4.2.14 Relative Seek Command ААААААААААААААА36

4.2.15 Scan CommandsАААААААААААААААААААААА37

4.2.16 Seek CommandААААААААААААААААААААААА37

4.2.17 Sense Drive Status Command АААААААААА37

4.2.18 Sense Interrupt Command ААААААААААААА37

4.2.19 Set Track CommandААААААААААААААААААА38

4.2.20 Specify CommandААААААААААААААААААААА38

4.2.21 Verify Command АААААААААААААААААААААА39

4.2.22 Version Command АААААААААААААААААААА39

4.2.23 Write Data Command АААААААААААААААААА39

4.2.24 Write Deleted Data Command АААААААААА40

5.0 FDC FUNCTIONAL DESCRIPTION ААААААААААААААА40

5.1 Microprocessor InterfaceАААААААААААААААААААААА40

5.2 Modes of Operation АААААААААААААААААААААААААА41

5.3 Controller Phases АААААААААААААААААААААААААААА41

5.3.1 Command PhaseАААААААААААААААААААААААА41

5.3.2 Execution Phase АААААААААААААААААААААААА41

5.3.2.1 DMA ModeРFIFO Disabled ААААААА41

5.3.2.2 DMA ModeРFIFO Enabled АААААААА42

5.3.2.3 Interrupt ModeÐFIFO Disabled ÀÀÀÀ42

5.3.2.4 Interrupt ModeРFIFO Enabled ААААА43

5.3.2.5 Software Polling АААААААААААААААААА43

5.3.3 Result Phase ААААААААААААААААААААААААААА43

5.3.4 Idle PhaseАААААААААААААААААААААААААААААА43

5.3.5 Drive Polling Phase АААААААААААААААААААААА43

5.4 Data Separator АААААААААААААААААААААААААААААА43

5.5 Crystal Oscillator ААААААААААААААААААААААААААААА45

5.6 Perpendicular Recording Mode АААААААААААААААА46

5.7 Data Rate Selection АААААААААААААААААААААААААА47

5.8 Write Precompensation ААААААААААААААААААААААА47

5.9 FDC Low Power Mode LogicААААААААААААААААААА47

5.10 Reset Operation ААААААААААААААААААААААААААААА47

6.0 SERIAL PORTS АААААААААААААААААААААААААААААААА48

6.1 Introduction АААААААААААААААААААААААААААААААААА48

6.2 PC87311A Serial Ports ААААААААААААААААААААААААА48

6.2.1 Serial Port Registers АААААААААААААААААААААА48

6.2.2 Line Control Register (LCR)АААААААААААААААА48

6.2.3 Programmable Baud Rate GeneratorАААААААА51

6.2.4 Line Status Register (LSR)ААААААААААААААААА51

6.2.5 Interrupt Identification Register (IIR) АААААААА52

6.2.6 Interrupt Enable Register (IER) ААААААААААААА52

6.2.7 MODEM Control Register (MCR) ААААААААААА52

6.2.8 MODEM Status Register (MSR) АААААААААААА53

6.2.9 Scratchpad Register (SCR) АААААААААААААААА53

6.3 PC87312 Serial Ports АААААААААААААААААААААААААА53

6.3.1 Serial Port Registers АААААААААААААААААААААА53

6.3.2 Line Control Register (LCR)АААААААААААААААА53

6.3.3 Programmable Baud Rate GeneratorАААААААА56

2

Table of Contents

6.3.4 Line Status Register (LSR) ААААААААААААААА56

6.3.5 FIFO Control Register (FCR)АААААААААААААА57

6.3.6 Interrupt Identification Register (IIR) ААААААА57

6.3.7 Interrupt Enable Register (IER) АААААААААААА57

6.3.8 MODEM Control Register (MCR) АААААААААА58

6.3.9 MODEM Status Register (MSR) ААААААААААА59

6.3.10 Scratchpad Register (SCR) ААААААААААААААА59

7.0 PARALLEL PORT АААААААААААААААААААААААААААААА59

7.1 Introduction АААААААААААААААААААААААААААААААААА59

7.2 Data Register (DTR) ААААААААААААААААААААААААААА60

7.3 Status Register (STR) АААААААААААААААААААААААААА60

7.4 Control Register (CTR) ААААААААААААААААААААААААА60

8.0 INTEGRATED DEVICE ELECTRONICS
INTERFACE (IDE) АААААААААААААААААААААААААААААА61

8.1 Introduction АААААААААААААААААААААААААААААААААА61

8.2 IDE Signals ААААААААААААААААААААААААААААААААААА61

9.0 DEVICE DESCRIPTION ААААААААААААААААААААААААА62

9.1 DC Electrical Characteristics АААААААААААААААААААА62

9.2 AC Electrical Characteristics АААААААААААААААААААА64

9.2.1 AC Test Conditions АААААААААААААААААААААА64

9.2.2 Clock Timing ААААААААААААААААААААААААААА64

9.2.3 Microprocessor Interface Timing АААААААААА65

9.2.4 Baudout Timing ААААААААААААААААААААААААА66

9.2.5 Transmitter Timing АААААААААААААААААААААА67

9.2.6 Receiver TimingААААААААААААААААААААААААА68

9.2.7 MODEM Control Timing АААААААААААААААААА69

9.2.8 DMA Timing АААААААААААААААААААААААААААА70

9.2.9 Reset Timing ААААААААААААААААААААААААААА71

9.2.10 Write Data Timing ААААААААААААААААААААААА71

9.2.11 Drive Control Timing ААААААААААААААААААААА72

9.2.12 Read Data Timing ААААААААААААААААААААААА72

9.2.13 IDE Timing ААААААААААААААААААААААААААААА72

9.2.14 Parallel Port Timing АААААААААААААААААААААА73

10.0 REFERENCE SECTION АААААААААААААААААААААААА74

10.1 Mnemonic Definitions for FDC Commands ААААААА74

10.2 Example Four Drive Circuit
Using the PC87311A/12 АААААААААААААААААААА75

List of Figures

FIGURE 2-1 PC87311A/87312 Configuration Registers АААААААААААААААААААААААААААААААААААААААААААААААААААААААААА12

FIGURE 3-1 FDC Functional Block DiagramААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА18

FIGURE 4-1 IBM, Perpendicular, and ISO Formats Supported by Format Command АААААААААААААААААААААААААААААААААА30

FIGURE 5-1 FDC Data Separator Block Diagram АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА44

FIGURE 5-2 PC87311A/87312 Dynamic Window Margin Performance ААААААААААААААААААААААААААААААААААААААААААААА45

FIGURE 5-3 Read Data AlgorithmРState DiagramААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА46

FIGURE 5-4 Perpendicular Recording Drive R/W Head and Pre-Erase Head АААААААААААААААААААААААААААААААААААААААА46

FIGURE 6-1 PC87311A Composite Serial Data АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА48

FIGURE 6-2 PC87312 Composite Serial Data ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА54

FIGURE 9-1 Clock Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА64

FIGURE 9-2 Microprocessor Read Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА65

FIGURE 9-3 Microprocessor Write Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА66

FIGURE 9-4 Baudout Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА66

FIGURE 9-5 Transmitter Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА67

FIGURE 9-6a Receiver TimingАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА68

FIGURE 9-6b PC87312 FIFO Mode Receiver Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА68

FIGURE 9-6c PC87312 Timeout Receiver Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА69

FIGURE 9-7 MODEM Control Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА69

FIGURE 9-8 DMA Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА70

FIGURE 9-9 Reset Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА71

FIGURE 9-10 Write Data Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА71

FIGURE 9-11 Drive Control Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА72

FIGURE 9-12 Read Data Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА72

FIGURE 9-13 IDE Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА72

FIGURE 9-14 Parallel Port Interrupt Timing (Compatible Mode) ААААААААААААААААААААААААААААААААААААААААААААААААААААА73

FIGURE 9-15 Parallel Port Interrupt Timing (Extended Mode) ААААААААААААААААААААААААААААААААААААААААААААААААААААААА73

FIGURE 9-16 Typical Parallel Port Data Exchange АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА73

FIGURE 10-1 PC87311A/87312 Four Floppy Drive Circuit ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА75

FIGURE 10-2 IDE Interface Signal Equations ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА75

FIGURE 10-3 PC87311A/87312 Adapter Card Schematic ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА76

3

List of Tables

TABLE 2-1 Default Configurations Controlled by Hardware АААААААААААААААААААААААААААААААААААААААААААААААААААААААА13

TABLE 2-2 Index and Data Register Optional Locations ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА14

TABLE 2-3 Primary and Secondary Drive Address Selection ААААААААААААААААААААААААААААААААААААААААААААААААААААААА15

TABLE 2-4 Encoded Drive and Motor Pin Information ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА15

TABLE 2-5 Parallel Port AddressesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА16

TABLE 2-6a COM Port Selection for UART1 АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА16

TABLE 2-6b COM Port Selection for UART2 АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА16

TABLE 2-7 Address Selection for COM3 and COM4 АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА16

TABLE 3-1 Register Description and AddressesАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА18

TABLE 3-2 Drive Enable Values ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА20

TABLE 3-3 Tape Drive Assignment Values АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА20

TABLE 3-4 Write Precompensation Delays АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА21

TABLE 3-5 Default Precompensation Delays АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА21

TABLE 3-6 Data Rate Select Encoding ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА22

TABLE 4-1 Typical Format Gap Length ValuesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА31

TABLE 4-2 DENSEL EncodingААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА33

TABLE 4-3 DENSEL Default EncodingАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА33

TABLE 4-4 Effect of Drive Mode and Data Rate on Format and Write CommandsААААААААААААААААААААААААААААААААААААА34

TABLE 4-4a Effect of GAP and WG on Format and Write Commands АААААААААААААААААААААААААААААААААААААААААААААААА34

TABLE 4-5 Sector Size Selection АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА34

TABLE 4-6 SK Effect on Read Data CommandААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА35

TABLE 4-7 Result Phase Termination Values with No Error АААААААААААААААААААААААААААААААААААААААААААААААААААААААА35

TABLE 4-8 SK Effect on Read Deleted Data Command ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА36

TABLE 4-9 Maximum Recalibrate Step Pulses Based on R255 and ETRААААААААААААААААААААААААААААААААААААААААААААА36

TABLE 4-10 Scan Command Termination Values ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА37

TABLE 4-11 Status Register 0 Termination Codes ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА38

TABLE 4-12 Set Track Register Address ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА38

TABLE 4-13 Step Rate (SRT) Values АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА38

TABLE 4-14 Motor Off Time (MFT) ValuesАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА39

TABLE 4-15 Motor On Time (MNT) Values ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА39

TABLE 4-16 Verify Command Result Phase Table ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА40

TABLE 6-1 PC87311A UART Register Addresses (AEN

TABLE 6-2 PC87311A Register Summary for an Individual UART ChannelААААААААААААААААААААААААААААААААААААААААААА49

TABLE 6-3 PC87311A UART Reset ConfigurationАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА50

TABLE 6-4 PC87311A UART Divisors, Baud Rates, and Clock Frequencies ААААААААААААААААААААААААААААААААААААААААА51

TABLE 6-5 PC87311A Interrupt Control FunctionsАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА52

TABLE 6-6 PC87312 UART Register Addresses (AEN

TABLE 6-7 PC87312 Register Summary for an Individual UART Channel АААААААААААААААААААААААААААААААААААААААААААА54

TABLE 6-8 PC87312 UART Reset Configuration ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА55

TABLE 6-9 PC87312 UART Divisors, Baud Rates, and Clock Frequencies ААААААААААААААААААААААААААААААААААААААААААА56

TABLE 6-10 PC87312 Interrupt Control Functions ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА58

TABLE 7-1 Parallel Interface Register Addresses АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА59

TABLE 7-2 Data Register Read and Write Modes АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА59

TABLE 7-3 Parallel Port Mode of Operation ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА59

TABLE 7-4 Parallel Port Reset StatesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА60

TABLE 8-1 IDE Registers and Their ISA AddressesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА61

TABLE 9-1 Nominal t

TABLE 9-2 Minimum t

TABLE 10-1 PC87311A/87312 Four Floppy Drive Encoding АААААААААААААААААААААААААААААААААААААААААААААААААААААААА75

Values АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА64

ICP,tDRP

Values ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА71

WDW

e

0) АААААААААААААААААААААААААААААААААААААААААААААААААААААА48

e

0) ААААААААААААААААААААААААААААААААААААААААААААААААААААААА53

4

Basic Configuration

*Note: PC87311A only

TL/F/11362– 2

5

1.0 Pin Description

Connection Diagram

Plastic Quad Flatpak, EIAJ

*Note: XTSEL PC87311A only TL/F/11362– 3

Order Number PC87311AVF or PC87312VF

See NS Package Number VLJ100A

6

1.0 Pin Description (Continued)

Symbol Pin I/O Function

A9–A0 21–30 I Address. These address lines from the microprocessor determine which internal register is accessed.

ACK 85 I Acknowledge. This input is pulsed low by the printer to indicate that it has received data from the

AFD 78 O Automatic Feed XT. When this signal is low the printer should automatically line feed after each line is

AEN 20 I Address Enable. This input disables function selection via A9 – A0 when it is high. Access to the FDC

BADDR0 55 I Base Address. This bit determines one of two base addresses from which the Index and Data

BOUT1,2 73, 65 O BAUD Output. This multi-function pin provides the associated serial channel Baud Rate generator

BUSY 84 I Busy. This pin is set high by the printer when it can’t accept another character. This pin has a nominal

CFG0–4 65, 66, I Default Configuration. These CMOS inputs select 1 of 32 default configurations in which the

71, 73,

74

CSOUT 3OChip Select Output. When the associated bit in the Power and Test Configuration Register is set, this

CTS1,2 72, 64 I Clear to Send. When low, this indicates that the MODEM or data set is ready to exchange data. The

D7–D0 10–17 I/O Data. Bi-directional data lines to the microprocessor. D0 is the LSB and D7 is the MSB. These signals

DACK 5IDMA Acknowledge. Active low input to acknowledge the FDC DMA request and enable the RD and

DCD1,2 77, 69 I Data Carrier Detect. When low, this indicates that the data carrier has been detected by the MODEM

DENSEL 48 O Density Select. Indicates when a high FDC density data rate (500 kb/s or 1 Mb/s) or a low density

DIR 41 O Direction. This output determines the direction of the floppy disk drive (FDD) head movement (active

A0–A9 are don’t cares during an FDC DMA transfer.

parallel port. This pin has a nominal 25 kX pull-up resistor attached.

printed. This pin will be in a TRI-STATEÉcondition 10 ns after a zero is loaded into the corresponding
Control Register bit. The system should pull this pin high using a 4.7 kX resistor.

Data Register during DMA transfer is NOT affected by this pin.

Registers will be offset (see Table 2-2). An internal pull-down resistor of 40 kX is on each pin. Use a
10 kX resistor to pull this pin to the required level during reset.

output signal, if test mode is selected in the Power and Test Configuration Register and the DLAB bit
(LCR7) is set. After Master Reset this pin provides the SOUT function. (See SOUT and CFG0–4 for
further information.)

25 kX pull-down resistor attached to it.

PC87311A/12 will power-up (see Table 2-1). An internal pull-down resistor of 40 kX is on each pin.
Usea10kXresistor to pull these pins to the required level during reset.

multi-function pin provides an active signal each time the internal address decoder decodes an
address enabled for the PC87311A/12. (See PWDN

CTS

signal is a MODEM status input whose condition the CPU can test by reading bit 4 (CTS) of the
MODEM Status Register (MSR) for the appropriate serial channel. Bit 4 is the complement of the CTS
signal. Bit 0 (DCTS) of the MSR indicates whether the CTS input has changed state since the previous
reading of the MSR. CTS

Note: Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled.

all have 24 mA (sink) buffered outputs.

WR

inputs during a DMA transfer. When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of
the Digital Output Register (DOR). When in PS/2Émode, DACK is always enabled, and bit D3 of the
DOR is reserved. DACK

or data set. The DCD
7 (DCD) of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 7 is the
complement of the DCD
changed state since the previous reading of the MSR.

Note: Whenever the DDCD bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

data rate (250 or 300 kb/s) has been selected. DENSEL is active high for high density (5.25
when IDENT is high, and active low for high density (3.5
programmable via the Mode command (see Section 4.2.6).

e

step in, inactiveestep out) during a seek operation. During read or writes, DIR will be inactive.

has no effect on the transmitter.

should be held high during PIO accesses.

signal is a MODEM status input whose condition the CPU can test by reading bit

signal. Bit 3 (DDCD) of the MSR indicates whether the DCD input has

for further information.)

drives) when IDENT is low. DENSEL is also

×

drives)

×

7

1.0 Pin Description (Continued)

Symbol Pin I/O Function

DR0,1 44, 45 O Drive Select 0,1. These are the decoded drive select outputs that are controlled by Digital Output

DRATE0,1 52, 51 O Data Rate 0,1. These outputs reflect the currently selected FDC data rate, (bits 0 and 1 in the

DRQ 4 O DMA Request. Active high output to signal the DMA controller that a FDC data transfer is needed.

DRV2 49 I Drive2. This input indicates whether a second disk drive has been installed. The state of this pin is

DSKCHG 32 I Disk Change. The input indicates if the drive door has been opened. The state of this pin is available

DSR1,2 76, 68 I Data Set Ready. When low, this indicates that the data set or MODEM is ready to establish a

DTR1,2 71, 63 O Data Terminal Ready. When low, this output indicates to the MODEM or data set that the UART is

ERR 79 I Error. This input is set low by the printer when it has detected an error. This pin has nominal 25 kX

HCS0 58 O Hard Drive Chip Select 0. This output is active in the AT mode when the hard drive registers from

HCS1 57 O Hard Drive Chip Select 1. This output is active in the AT mode when the hard drive registers from

HDSEL 34 O Head Select. This output determines which side of the FDD is accessed. Active selects side 1,

IDED7 60 I/O IDE Bit 7. This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the

IDEHI 56 O IDE High Byte. This output enables the high byte data latch during a read or write to the hard drive if

IDELO 55 O IDE Low Byte. This output enables the low byte data latch during a read or write to the hard drive .

Register bits D0, D1. The Drive Select outputs are gated with DOR bits 4–7. These are active low
outputs. They are encoded with information to control four FDDs when bit 4 of the Function Enable
Register (FER) is set. (See MTR0,1

Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written
to last). These pins are totem-pole buffered outputs (6 mA sink, 6 mA source).

When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode,
DRQ is always enabled, and bit D3 of the DOR is reserved.

available from Status Register A in PS/2 mode.

from the Digital Input register. This pin can also be configured as the RGATE data separator
diagnostic input via the Mode command (see Section 4.2.6).

communications link. The DSR
reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel. Bit 5 is the
complement of the DSR
changed state since the previous reading of the MSR.

Note: Whenever the DDSR bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

ready to establish a communications link. The DTR
bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset operation sets this signal
to its inactive (high) state. In the PC87312, loop mode operation holds this signal to its inactive state.
(See CFG4–0 for further information.) In the PC87311A, loop mode operation holds this signal to its
inactive state if the XTSEL pin is high during reset. If the XTSEL pin is low during reset, the associated
pin state is controlled by the MCR0 bit during loop mode operation. (See XTSEL and CFG0–4 for
further information.)

pull-up resistor attached to it.

1F0–1F7h are selected if the primary address is used or when 170 – 177h are selected if the
secondary address is used. In the XT mode (PC87311A) this output is active if the addresses from
320–324h are selected. This output is inactive if the IDE interface is disabled via the Configuration
Register. (See POE for further information.)

3F6–7 are selected if the primary address is used or when 376 – 377 are selected if the secondary
address is used. In the XT mode (PC87311A) this output is inactive. This output is also inactive if the
IDE interface is disabled via the Configuration Register. (See PDIR for further information.)

inactive selects side 0.

address range 1F0–1F7h, 170 – 177h and 3F6h and 376h. This pin is TRI-STATE during read or write
accesses to 3F7h and 377h.

the hard drive returns IOCS16
Configuration Register.

This output is inactive if the IDE interface is disabled via the Configuration Register. (See BADDR0 for
further information.)

signal. Bit 1 (DDSR) of the MSR indicates whether the DSR input has

and Table 2-4 for more information.)

signal is a MODEM status input whose condition the CPU can test by

signal can be set to an active low by programming

. This output is inactive if the IDE interface is disabled via the

8

1.0 Pin Description (Continued)

Symbol Pin I/O Function

IDENT 54 I Identity. During chip reset, the IDENT and MFM pins are sampled to determine the mode of operation

INDEX 47 I Index. This input signals the beginning of a FDD track.

INIT 80 O Initialize. When this signal is low it causes the printer to be initialized. This pin will be in a TRI-STATE

IOCS16 59 I I/O Chip Select 16-Bit. This input will be driven by the peripheral device when it can accommodate a

IRQ3,4 1, 100 O Interrupt 3 and 4. These are active high interrupts associated with the serial ports. IRQ3 presents the

IRQ5 98 O Interrupt 5. Active high output that indicates a parallel port interrupt. When enabled this bit follows the

IRQ6 97 O Interrupt 6. Active high output to signal the completion of the execution phase for certain FDC

IRQ7 96 O Interrupt 7. Active high output that indicates a parallel port interrupt. When enabled this bit follows the

MR 2 I Master Reset. Active high input that resets the controller to the idle state, and resets all disk interface

according to the following table:

IDENT MFM MODE

1 1 or NC PC-AT Mode
1 0 Illegal
0 1 or NC PS/2 Mode
0 0 Model 30 Mode

AT ModeÐThe DMA enable bit in the DOR is valid. TC is active high. Status Registers A and B are
disabled (TRI-STATE).

Model 30 ModeÐThe DMA enable bit in the DOR is valid. TC is active high. Status Registers A and B
are enabled.

PS/2 ModeÐThe DMA enable bit in the DOR is a don’t care, and the DRQ and IRQ6 signals will always
be enabled. TC is active low. Status Registers A and B are enabled.

After chip reset, the state of IDENT determines the polarity of the DENSEL output.
When IDENT is a logic ‘‘1’’, DENSEL is active high for the 500 kbs/1 Mbs data rates.
When IDENT is a logic ‘‘0’’, DENSEL is active low for the 500 kbs/1 Mbs data rates.
(See Mode command for further explanation of DENSEL.)

condition 10 ns after a zero is loaded into the corresponding Control Register bit. The system should pull
this pin high using a 4.7 kX resistor.

16-bit access.

signal if the serial channel has been designated as COM2 or COM4. IRQ4 presents the signal if the serial
port is designated as COM1 or COM3. The appropriate interrupt goes active whenever it is enabled via
IER, the associated Interrupt Enable bit (Modem Control Register bit 3, MCR3), and any of the following
conditions are active: Receiver Error, Receive Data available, Transmitter Holding Register Empty, or a
Modem Status Flag is set. The interrupt is reset low (inactive) after the appropriate interrupt service
routine is executed, after being disabled via the IER, or after a Master Reset. Either interrupt can be
disabled, putting them into TRI-STATE, by setting the MCR3 bit low.

ACK

signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is
designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled or when operating in
the XT mode this signal is TRI-STATE.

commands. Also used to signal when a data transfer is ready during a Non-DMA operation. When in
PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode, IRQ6 is
always enabled, and bit D3 of the DOR is reserved.

ACK

signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is
designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled this signal is

TRI-STATE.

outputs to their inactive states. The DOR, DSR, CCR, Mode command, Configure command, and Lock
command parameters are cleared to their default values. The Specify command parameters are not
affected. The Configuration Registers are set to their selected default values.

9

1.0 Pin Description (Continued)

Symbol Pin I/O Function

MFM 53 I/O MFM. During a chip reset when in PS/2 mode (IDENT low), this pin is sampled to select the PS/2 mode

MTR0,1 46, 43 O Motor Select 0,1. These are the motor enable lines for drives 0 and 1, and are controlled by bits

PD0–7 94– 91, I/O Parallel Port Data. These bidirectional pins transfer data to and from the peripheral data bus and the

89–86

PDIR 57 I Parallel Port Direction. During reset the state of this pin determines the direction of the parallel port

PDWN 3IPower Down. This multi-function pin will stop the clocks and/or the external crystal based on the

PE 83 I Paper End. This input is set high by the printer when it is out of paper. This pin has a nominal 25 kX

POE 58 I Parallel Port Output Enable. This pin is sensed during reset. If it is low, bit 7 of the Power and Test

RD 19 I Read. Active low input to signal a data read by the microprocessor.

RDATA 35 I Read Data. This input is the raw serial data read from the floppy disk drive.

RI1,2 70, 62 I Ring Indicator. When low this indicates that a telephone ringing signal has been received by the

RTS1,2 74, 66 O Request to Send. When low, this output indicates to the MODEM or data set that the UART is ready to

SIN1,2 75, 67 I Serial Input. This input receives composite serial data from the communications link (peripheral device,

SLCT 82 I Select. This input is set high by the printer when it is selected. This pin has a nominal 25 kX pull-down

SLIN 81 O Select Input. When this signal is low it selects the printer. This pin will be in a TRI-STATE condition

(MFM high), or the Model 30 mode (MFM low). An internal pull-up or external pull-down 10 kX resistor
will select between the two PS/2 modes. When the PC-AT mode is desired, (IDENT high), MFM should
be left pulled high internally. MFM reflects the current data encoding format when RESET is inactive.

e

MFM

high, FMelow. Defaults to low after a chip reset. This signal can also be configured as the

PUMP data separator diagnostic output via the Mode command (see Section 4.2.6).

D7–D4 of the Digital Output register. They are active low outputs. They are encoded with information to
control four FDDs when bit 4 of the Function Enable Register (FER) is set. (See DR0,1
for more information.)

parallel port Data Register. These pins have high current drive capability. (See DC Electrical
Characteristics.)

data, if the PTR7
input (scanner) when PDIR
Usea10kXresistor to pull this pin to the required level during reset.

selections made in the Power and Test Register bits 1-2. (See CSOUT for additional information.)

pull-down resistor attached to it.

Register (PTR7) is set high and the parallel port will operate in the Extended Mode. In this mode
software determines the direction of parallel port data via the parallel port Control Register (CTR5). If
this pin is high (PTR7
by the state of PDIR pin at reset. An internal pull-down resistor of 40 kX is on this pin. Use a 10 kX
resistor to pull this pin to the required level during reset.

MODEM. The RI
of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 6 is the complement of the
RI

signal. Bit 2 (TERI) of the MSR indicates whether the RI input has changed from low to high since the

previous reading of the MSR.

Note: Whenever the TERI bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

exchange data. The RTS
Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. In
the PC87312, loop mode operation holds this signal to its inactive state. (See CFG0–4 for further
information.) In the PC87311A, loop mode operation holds this signal to its inactive state if the XTSEL
pin is high during reset. If the XTSEL pin is low during reset, the associated pin state is controlled by the
MCR1 bit during loop mode operation. (See CFG0–4 for further information.)

MODEM, or data set).

resistor attached to it.

10 ns after a zero is loaded into the corresponding Control Register bit. The system should pull this pin
high using a 4.7 kX resistor.

e

0. The direction will be output (printer) when PDIRe0 and PTR7e0 and it will be

e

1 and PTR7e0. An internal pull-down resistor or 40 kX is on this pin.

e

0) then the Compatible Mode is selected and the data direction is determined

signal is a MODEM status input whose condition the CPU can test by reading bit 6 (RI)

signal can be set to an active low by programming bit 1 (RTS) of the MODEM

and Table 2-4

10

1.0 Pin Description (Continued)

Symbol Pin I/O Function

SOUT1,2 73, 65 O Serial Output. This output sends composite serial data to the communications link (peripheral device,

STB 95 O Data Strobe. This output indicates to the printer that valid data is available at the printer port. This pin

STEP 40 O Step. This output signal issues pulses to the disk drive at a software programmable rate to move the

TC 6 I Terminal Count. Control signal from the DMA controller to indicate the termination of a DMA transfer.

TRK0 37 I Track 0. This input indicates to the controller that the head of the selected floppy disk drive is at track

VDDA 33 Analog Supply. This pin is the 5V supply for the analog data separator.

VDDB,C 50, 99 Digital Supply. This is the 5V supply voltage for the digital circuitry.

VSSA 31 Analog Ground. This is the analog ground for the data separator.

VSSB-E 42, 9, Digital Ground. This is the ground for the digital circuitry.

90, 61

WR 18 I Write. Active low input to signal a write from the microprocessor to the controller.

WDATA 39 O Write Data. This output is the write precompensated serial data that is written to the selected floppy

WGATE 38 O Write Gate. This output signal enables the write circuitry of the selected disk drive. WGATE has been

WP 36 I Write Protect. This input indicates that the disk in the selected drive is write protected.

X1/OSC 7 I Crystal1/Clock. One side of an external 24 MHz crystal is attached here. If a crystal is not used, a TTL

X2 8 O Crystal2. One side of an external 24 MHz crystal is attached here. This pin is left unconnected if an

XTSEL* 63 I XT Select. When this pin is high during reset the chip will operate in the XT mode. When this pin is low

*Note: XTSEL is an option for the PC87311A only.

MODEM, or data set). The SOUT signal is set to a marking state (logic 1) after a Master Reset
operation. (See BOUT and CFG0–4 for further information on these pins.)

will be in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding Control Register bit.
The system should pull this pin high using a 4.7 kX resistor.

head during a seek operation.

TC is accepted only when DACK
low in PS/2 mode.

zero.

disk drive. Precompensation is software selectable.

designed to prevent glitches during power up and power down. This prevents writing to the disk when
power is cycled.

or CMOS compatible clock is connected to this pin.

external clock is used.

during reset the chip will operate in the AT mode. An internal pull-down resistor of 40 kX is on this pin.
Usea10kXresistor to pull this pin to the required level during reset.

There are five differences between AT and XT mode. One concerns hard disk operation and the other
four concern UART operation. In AT mode the IDE hard drive chip selects (HCS0
for addresses 1F0–7H and 3F6, 7H; respectively. In XT mode the IDE chip select HCS0
addresses 320–3H and HCS1
bit (see Section 6.5 bit 6), the modem control outputs during loop back mode (see Section 6.8 bit 4), the
Scratch Pad Register (see Section 6.10), and the availability of edge (XT) or level (AT) sensitive UART
interrupts.

is active. TC is active high in PC-AT and Model 30 modes, and active

, HCS1) will be active

responds to

is inactive. The differences in UART operation are: the function of LSR

11

2.0 Configuration Registers

2.1 OVERVIEW

Three registers constitute the Base Configuration Register
set which controls the set-up of the PC87311A/12. In gen­eral, these registers control the enabling of each major
function (e.g., FDC, UARTs, parallel port, etc.), the I/O ad­dresses of those functions, and whether those functions
power down via hardware control or not. These three con­figuration registers are called the Function Enable Register
(FER), the Function Address (FAR) Register and the Power
and Test Register (PTR).

These registers can be accessed via hardware or software.
During reset, the PC87311A/12 loads a set of default val­ues selected by a hardware strapping option into the Config­uration Registers. This defines the setting of all Configura­tion Registers via hardware.

An index and data register pair are used to read and write
these registers. Each Configuration Register is pointed to by
the value loaded into the Index Register. The data to be
written into the Configuration Register is transferred via the
Data register. Reading a Configuration Register is done in a
similar way (i.e., by pointing to it via the Index Register and
then reading its contents via the Data Register).

Accessing the Configuration Registers in this way requires
only two system I/O addresses. Since that I/O space is
shared by other devices the Index and Data Registers could
still be inadvertantly accessed, even though, there are only
two registers in this I/O address space. In order to reduce
the chances of an inadvertant access, a simple procedure
(Section 2.2) has been developed.

2.2 SOFTWARE CONFIGURATION

If the system requires access to the Configuration Registers
after reset, then the following procedure is used to change
data in the registers.

1. Determine the default location of the PC87311A/12 In­dex Register.

A. Check the two possible default locations (see Table

2-2) by reading them twice. The first byte is the ID byte
(88H). The second byte read is always 00H. Compare
the data read with the ID byte and then 00h. A match
will occur at the correct location. Note that the ID byte
is only issued from the Index Register during the first
read after a reset. Subsequent reads return the value
loaded into the Index Register. Bits 2 – 6 are reserved
and always read 0.

2. Load the Configuration Registers.

A. Disable CPU interrupts.

B. Write the index of the Configuration Register (00h –

02h) to the Index Register one time.

C. Write the correct data for the Configuration Register in

two consecutive write accesses to the Data Register.

D. Enable CPU interrupts.

3. Load the Configuration Registers (read-modify-write).

A. Disable CPU interrupts.

B. Write the index of the Configuration Register (00h –

02h) to the Index Register one time.

C. Read the configuration data in that register via the

Data Register.

D. Modify the configuration data.

E. Write the changed data for the Configuration Register

in two consecutive writes to the Data Register. The
register updates on the second consecutive write.

F. Enable CPU interrupts.

A single read access to the Index and Data Registers can
be done at any time without disabling CPU interrupts. When
the Index Register is read, the last value loaded into the
Index Register will be returned. When the Data Register is
read, the Configuration Register data pointed to by the In­dex Register will be returned.

TL/F/11362– 38

TL/F/11362– 39

TL/F/11362– 40

FIGURE 2-1. PC87311A/12 Configuration Registers

2.3 HARDWARE CONFIGURATION

During reset, 1 of 32 possible sets of default values are
loaded into the Configuration Registers. A strapping option
on five pins (CFG0–4) selects the set of values that is load­ed. This allows for automatic configuration without software
intervention. Table 2-1 shows the 32 possible default con­figurations. The default configuration can be modified by
software at any time after reset by using the access proce­dure described in the Software Configuration Section.

12

2.0 Configuration Registers (Continued)

TABLE 2-1. Default Configurations Controlled by Hardware

Configuration Pins (CFGn)

43210

00000FAR

00001FAR

00010FAR

00011FAR

00100FAR

00101FAR

00110FAR

00111FAR

01000FAR

01001FAR

01010FAR

01011FAR

01100FAR

01101FAR

01110FAR

01111FAR

10000FAR

10001FAR

10010FAR

10011FAR

10100FAR

10101FAR

10110FAR

10111FAR

11000FAR

11001FAR

Data

(Hex)

FERe4F, CF FDC, IDE, UART1, UART2,llPORT

PTRe00 Power Down Clocks Option

e

10 PRI, PRI, COM1, COM2, LPT2

e

11 PRI, PRI, COM1, COM2, LPT1

e

11 PRI, SEC, COM1, COM2, LPT1

e

39 PRI, PRI, COM3, COM4, LPT1

e

24 PRI, PRI, COM2, COM3, LPT2

e

38 PRI, SEC, COM3, COM4, LPT2

FERe4B, CB FDC, IDE, UART1,llPORT

PTRe00 Power Down Clocks Option

e

00 PRI, PRI, COM1, LPT2

e

01 PRI, PRI, COM1, LPT1

e

01 PRI, SEC, COM1, LPT1

e

09 PRI, PRI, COM3, LPT1

e

08 PRI, PRI, COM3, LPT2

e

08 PRI, SEC, COM3, LPT2

FERe0F FDC, UART1, UART2,llPORT

PTRe00 Power Clocks Option

e

10 PRI, COM1, COM2, LPT2

e

11 PRI, COM1, COM2, LPT1

e

39 PRI, COM3, COM4, LPT1

e

24 PRI, COM2, COM3, LPT2

FERe49, C9 FDC, IDE,llPORT

PTRe00 Power Down Clocks Option

e

00 PRI, PRI, LPT2

e

01 PRI, PRI, LPT1

e

01 PRI, SEC, LPT1

e

00 PRI, SEC, LPT2

FERe07 UART1, UART2,llPORT

PTRe00 Power Down Clocks Option

e

10 COM1, COM2, LPT2

e

11 COM1, COM2, LPT1

e

39 COM3, COM4, LPT1

e

24 COM2, COM3, LPT2

FERe47, C7 IDE, UART1, UART2,llPORT

PTRe00 Power Down Clocks Option

e

10 PRI, COM1, COM2, LPT2

e

11 PRI, COM1, COM2, LPT1

Activated Functions

13

2.0 Configuration Registers (Continued)

TABLE 2-1. Default Configurations Controlled by Hardware (Continued)

Configuration Pins (CFGn)

43210

11010FAR

11011FAR

11100FAR

11101FAR

11110FER

11111FER

Data

(Hex)

e

11 SEC, COM1, COM2, LPT1

e

39 PRI, COM3, COM4, LPT1

e

24 PRI, COM2, COM3, LPT2

e

38 SEC, COM3, COM4, LPT2

e

08 FDC

PTRe00 Power Down Clocks Option

FARe10, 80 PRI

e

00 None

PTRe02, 82 Power Down XTAL and Clocks

FARe10 NA

Activated Functions

Table 2-1 is organized in the following way. The logic values
of the 5 external Configuration Pins are associated with the
resulting Configuration Register Data and the activated
functions. The activated functions are grouped into 7 cate­gories based on the data in the FER. In some cases the
data in the FER is given as one of two options. This is be­cause the primary or secondary IDE address is chosen via
the FER.

The PTR has one value associated with the active functions
in the FER. This value allows the power down of all clocks
when the PWDN
functions are active after reset, activating the PWDN
also stop the crystal.

Most of the variability available is through the FAR. Ad­dresses controlled by the FAR are coded in the following
way:

PRI is the PRImary floppy or IDE address (i.e., 3F0 –7h

or 1F0 – 7, 3F6, 7h)

SEC is the SECondary IDE address (170 – 7, 376, 7h)

COM1 is the UART address at 3F8 – Fh

COM2 is the UART address at 2F8 – Fh

COM3 is the UART address at 3E8 – Fh

COM4 is the UART address at 2E8 – Fh

LPT1 is the parallel port (

LPT2 is the

The chosen addresses are given under active functions and
are in the same order as the active functions they are asso­ciated with. In other words, if the active functions are given
as FDC, IDE, UART1, UART2,
are given as PRI, PRI, COM1, COM2, LPT2; then the func­tions and the addresses are associated as follows: FDC
PRI, IDEePRI, UART1eCOM1, UART2eCOM2,

PORTeLPT2.

ll

2.4 INDEX AND DATA REGISTERS

One more general aspect of the Configuration Registers is
that the Index and the Data Register pair can be relocated
to any one of two locations. This is controlled through a
hardware strapping option on one pin (BADDR0) and it al­lows the registers to avoid conflicts with other adapters in
the I/O address space. Table 2-2 shows the address op­tions.

pin goes active. In the last case where no

PORT ) address at 3BC – 3BEh

PORT address at 378 – 37Fh

ll

ll

PORT and the addresses

ll

pin will

TABLE 2-2. Index and Data

Register Optional Locations

BADDR0 Index Addr. Data Addr.

0 398h 399h

1 26Eh 26Fh

2.5 BASE CONFIGURATION REGISTERS

2.5.1 Function Enable Register (FER, Index 0)

This register enables and disables all major chip functions.
Disabled functions have their clocks automatically powered
down, but the data in their registers remains intact. It also
selects whether the FDC and the IDE controller will be lo­cated at their primary or secondary address.

Bit 0 When this bit is one the parallel port can be accessed

at the address specified in the FAR.

Bit 1 When this bit is one, UART1 can be accessed at the

address specified in the FAR. When this bit is zero,
access to UART1 is blocked and it will be in power
down mode. The UART1 registers retain all data in
power down mode. Caution: Any UART1 interrupt
that is enabled and active or becomes active after
UART1 is disabled will assert the associated IRQ pin
when UART1 is disabled. If disabling UART1 via soft­ware, clear the IRQ Enable bit (MCR3) to zero before
clearing FER 1. This is not an issue after reset be­cause MCR3 will be zero until it is written.

Bit 2 When this bit is one, UART2 can be accessed at the

address specified in the FAR. When this bit is zero,
access to UART2 is blocked and it will be in power

e

14

down mode. The UART2 registers retain all data in
power down mode. Caution: Any UART2 interrupt
that is enabled and active or becomes active after
UART2 is disabled will assert the associated IRQ pin
when UART2 is disabled. If disabling UART2 via soft­ware, clear the IRQ Enable bit (MCR3) to zero before
clearing FER2. This is not an issue after reset be­cause MCR3 will be zero until it is written.

2.0 Configuration Registers (Continued)

Bit 3 When this bit is one, the FDC can be accessed at the

address specified in FER[5]. When this bit is zero ac­cess to the FDC is blocked and it will be in power
down mode. The FDC registers retain all data in power
down mode.

Bit 4 When this bit is zero the PC87311A/12 can control

two floppy disk drives directly without an external de­coder. When this bit is one the two drive select signals
and two motor enable signals from the FDC are en­coded so that four floppy disk drives can be controlled
(see Table 2-4). Controlling four FDDs requires an ex­ternal decoder. The pin states shown in Table 2-4 are
a direct result of the bit patterns shown. All other bit
patterns produce pin states that should not be decod­ed to enable any drive or motor.

TABLE 2-3. Primary and Secondary Drive Address Selection

BIT 5 BIT 7 DRIVE AT AT XT (Note)

ÐÐ Ð Primary Secondary Ð

0 X FDC 3F0– 7h Ð Ð

1 X FDC Ð 370–7h Ð

X X FDC Ð Ð 3F0– 7h

X 0 IDE 1F0–7, 3F6, 3F7h Ð Ð

X 1 IDE Ð 170–7, 376-7h Ð

X X IDE Ð Ð 320– 3h

Note: PC87311A only

TABLE 2-4. Encoded Drive and Motor Pin Information (FER 4e1)

Digital Output Reg Drive Control Pins

7 6 5 4 3 2 1 0 MTR1 MTR0 DR1 DR0

XXX1X X 0 0 (Note 1) 0 0 0 Activate Drive 0 and Motor 0

XX1X X X 0 1 (Note 1) 0 0 1 Activate Drive 1 and Motor 1

X 1 X X X X 1 0 (Note 1) 0 1 0 Activate Drive 2 and Motor 2

1 X X X X X 1 1 (Note 1) 0 1 1 Activate Drive 3 and Motor 3

XXX0X X 0 0 (Note 1) 1 0 0 Activate Drive 0 and Deactivate Motor 0

XX0X X X 0 1 (Note 1) 1 0 1 Activate Drive 1 and Deactivate Motor 1

X 0 X X X X 1 0 (Note 1) 1 1 0 Activate Drive 2 and Deactivate Motor 2

0 X X X X X 1 1 (Note 1) 1 1 1 Activate Drive 3 and Deactivate Motor 3

Note 1: When FER4e1, MTR1 will present a pulse that is the inverted image of the IOW strobe. This inverted pulse will be active whenever an I/O write to

address 3F2h or 372h takes place. This pulse is delayed by 25 ns –80 ns after the leading edge of IOW and its leading edge can be used to clock data into an
external latch (e.g., 74LS175). Address 3F2h will be used if the FDC is located at the primary address (FER5
located at the secondary address (FER5

e

1). See the AC Electrical Characteristics (Section 9.2) for detailed timing.

Bit 5 This bit selects the primary or secondary FDC address

in the PC87312. In the PC87311A, this bit selects the
primary or secondary FDC address when in the AT
mode. In the XT mode it has no significance (see Ta­ble 2-3).

Bit 6 When this bit is a one the IDE drive interface can be

accessed at the address specified by FER bit 7. When
it is zero, access to the IDE interface is blocked, the
IDE control signals (i.e., HCS0

, HCS1, IDELO, IDEHI)
are held in the inactive state, and the IDED7 signal will
be in TRI-STATE.

Bit 7 This bit selects the primary or secondary IDE address

in the PC87312. In the PC87311A, this bit selects the
primary or secondary IDE address when in the AT
mode. In the XT mode it has no significance (see Ta­ble 2-3).

Decoded Functions

e

0) and address 372h will be used if the FDC is

15

2.0 Configuration Registers (Continued)

e

2.5.2 Function Address Register (FAR, Index

This register selects the ISA I/O address range to which
each peripheral function will respond.

Bits 0,1 These bits select the parallel port address as

shown in Table 2-5:

TABLE 2-5. Parallel Port Addresses

Bit1Bit

Parallel

0

Port

Address

InterruptATInterrupt

0 0 LPT2 (378– 37F) IRQ5 (Note) IRQ7

0 1 LPT1 (3BC– 3BE) IRQ7 IRQ7

1 0 LPT3 (278– 27F) IRQ5 IRQ7

1 1 Reserved TRI-STATE TRI-STATE

e

(CTR4

Note: The interrupt assigned to this address can be changed to IRQ7 by
setting Bit 3 of the power and test register.

Bits 2–5 These bits determine which ISA I/O address range

is associated with each UART (see Tables 2-6a,
2-6b).

TABLE 2-6a. COM Port Selection for UART1

FAR UART1

Bit 3 Bit 2 COM

0 0 1 (3F8-F)

0 1 2 (2F8-F)

1 0 3 (Table 2 – 7)

1 1 4 (Table 2 – 7)

TABLE 2-6b. COM Port Selection for UART2

FAR UART2

Bit 5 Bit 4 COM

00 1

01 2

10 3

11 4

Note: COM3 and COM4 addresses are determined by Bits 6 and 7.

Bits 6,7 These bits select the addresses that will be used

for COM3 and COM4 (see Table 2-7).

TABLE 2-7. Address Selection for COM3 and COM4

Bit 7 Bit 6 COM3 IRQ4 COM4 IRQ3

0 0 3E8–Fh 2E8–Fh

0 1 338–Fh 238–Fh

1 0 2E8–Fh 2E0–7h

1 1 220–7h 228–Fh

2.5.3 Power and Test Register (PTR, Indexe2)

This register determines several power down features: the
power down method used when the power down pin

1)

XT

0) (CTR4e0)

Ý

Ý

(PWDN

) is asserted (crystal and clocks vs clocks only),
whether hardware power down is enabled, and provides a
bit for software power down of all enabled functions. It se­lects whether IRQ7 or IRQ5 is associated with LPT2. It puts
the enabled UARTs into their test mode. Independent of this
register the floppy disk controller can enter low power mode
via the Mode Command or the Data Rate Select Register.

Bit 0 Setting this bit causes all enabled functions to be

powered down. If the crystal power down option is
selected (see Bit 1) the crystal will also be powered
down. All register data is retained when the crystal or
clocks are stopped.

Bit 1 When the Power Down pin or Bit 0 is asserted this bit

determines whether the enabled functions will have
their internal clocks stopped (Bit 1
nal crystal (Bit 1

e

1) will be stopped. Stopping the

e

0) or the exter-

crystal is the lowest power consumption state of the
part. However, if the crystal is stopped, a finite
amount of time (E8 ms) will be required for crystal
stabilization once the Power Down pin (PWDN

)or
Bit 0 is deasserted. If all internal clocks are stopped,
but the crystal continues to oscillate, no stabilization
period is required after the Power Down pin or Bit 0 is
deasserted.

Bit 2 Setting this bit enables the chip select function of the

PWDN

/CSOUT pin. Resetting this bit enables the

power down function of this pin.

Bit 3 Setting this bit associates the parallel port with IRQ7

when the address for the parallel port is 378 – 37Fh
(LPT2). This bit is a ‘‘don’t care’’ when the parallel
port address is 3BC –3BEh (LPT1) or 278–27Fh
(LPT3).

Bit 4 Setting this bit puts UART1 into a test mode, which

causes its Baudout clock to be present on its SOUT1
pin if the Line Control Register bit 7 is set to 1.

Bit 5 Setting this bit puts UART2 into a test mode, which

causes its Baudout clock to be present on its SOUT2
pin if the Line Control Register bit 7 is set to 1.

Bit 6 Setting this bit to a one prevents all further write ac-

cesses to the Configuration Registers. Once this bit is
set by software it can only be cleared by a hardware
reset. After the initial hardware reset this bit is zero.

Bit 7 This bit determines the operating mode of the parallel

port. If PTR7 is low, then the parallel port is in Com­patible Mode. If PTR7 is high, then the parallel port is
in Extended Mode. This bit will be the inverse of the
state of the POE

pin immediately after reset has oc-

curred. PTR7 can be programmed at any time.

2.6 POWER DOWN OPTIONS

There are various methods for entering the power down
mode. All methods result in one of three possible modes.
This section associates the methods of entering the power
down with the resulting mode.

Mode 1: The internal clock stops for a specific function (i.e.,
UART1 and/or UART2 and/or FDC).

This mode is entered by:

A. Clearing the FER bit for the specific function that will be

powered down. See Section 2.5.1 FER bits 1 – 3.

B. Also during reset by setting certain CFG0 – 4 pins. See

Table 2-1.

16

2.0 Configuration Registers (Continued)

C. Or by executing the FDC Mode Command with the PTR

e

bit 1

0. (XTAL/CLK) See Section 4.2.6 LOW PWR.

D. Or by setting Data Rate Select Register bit 6 high in the

FDC with the PTR bit 1

Mode 2: The internal clocks are stopped for all enabled
functions.

Note: Clocks to disabled functions are always inactive.

This mode is entered by:

A. Clearing all FER bits for any enabled function. See Sec-

tion 2.5.1 (FER bits 1 –3).

B. Or by clearing PTR bits 1 (XTAL/CLK) and 2 (CSOUT/

PWDN select) and then asserting the PWDN
See Section 2.5.3 PTR bits 1,2 and Section 1.0 PWDN
pin.

C. Or by clearing PTR bit 1 and then setting PTR bit 0 (Pow-

er Down) high. See Section 2.5.3 (PTR bits 0 and 1).

Mode 3: The external crystal is stopped and internal clocks
are stopped for all enabled functions.

This mode is entered by:

A. Clearing all FER bits that enable the FDC, UART1, and

UART2 functions. See Section 2.5.1 (FER bits 1 – 3).

B. Setting PTR bit 1 (XTAL/CLK), clearing PTR bit 2

(CSOUT/PWDN select), and then asserting the PWDN
signal low. See Section 2.5.3 PTR bits 1,2 and Section

1.0 PWDN

C. Or by setting PTR bit 1 and then setting PTR bit 0 high.

See Section 2.5.3 PTR bits 0 and 1.

D. Or during reset by pulling CFG0 – 4 pins high.

E. Or by executing the FDC Mode Command with the PTR

bit 1

F. Or by setting Data Rate Select Register bit 6 high in the

FDC with the PTR bit 1

2.7 POWER-UP PROCEDURE AND CONSIDERATIONS

2.7.1 Crystal Stabilization

If the crystal is stopped by putting either the FDC or the
UARTs into low power mode, then a finite amount of time
(E8 ms) must be allowed for crystal stabilization during
subsequent power-up. The stabilization period can be
sensed by reading the Main Status Register in the FDC, if
the FDC is being powered up. (The Request for Master bit
will not be set forE8 ms.) If either one of the UARTs are
being powered up, but the FDC is not, then the software
must determine theE8 ms crystal stabilization period. Sta­bilization of the crystal can also be sensed by putting the
UART into local loopback mode and sending bytes until
they are received correctly.

2.7.2 UART Power-Up

The clock signal to the UARTs is controlled through the
Configuration Registers (FER, PTR). In order to restore the
clock signal to one or both UARTs the following conditions
must exist:

1. The appropriate enable bit (FER1,2) for the UART(s)
must be set

2. and the Power Down bit (PTR0) must not be set

pin.

e

1. See Section 4.2.6 LOW PWR.

e

0. See Section 3.6 bit 6.

e

1. See Section 3.6 bit 6.

signal low.

3. and if the PWDN pin option (PTR2) is used the CSOUT/
PDWN pin must be inactive.

If the crystal has been stopped follow the guidelines in Sec­tion 2.7.1 before sending data or signaling that the receiver
channel is ready.

2.7.3 FDC Power-Up

The clock signal to the FDC is controlled through the Con­figuration Registers, the FDC Mode Command and the Data
Rate Select Register. In order to restore the clock signal to
the FDC the following conditions must exist:

1. The appropriate enable bit (FER3) must be set

2. and the Power Down bit (PTR0) must not be set

3. and if the PWDN pin option (PTR2) is used the CSOUT/
PDWN pin must be inactive.

In addition to these conditions, one of the following must be
done to initiate the recovery from Power Down mode:

1. Read the Main Status Register until the ROM bit (MSR7)
is set

2. or write to the Data Rate Select Register and set the
Software Reset bit (DSR7)

3. or write to the Digital Output Register and set, and then
the clear Reset bit (DOR2)

4. or read the Data Register and the Main Status Register
until the ROM bit is set.

If the crystal has been stopped, read the RQM bit in the
Main Status Register until it is set. The RQM bit does not get
set until the crystal has stabilized.

3.0 FDC Register Description

The floppy disk controller is suitable for all PC-AT, EISA,
PS/2, and general purpose applications. The operational
mode (PC-AT, PS/2, and Model 30) of the FDC is deter­mined by hardware strapping of the IDENT and MFM pins.
DP8473 and N82077 software compatibility is provided. Key
features include the 16-byte FIFO, PS/2 diagnostic register
support, the perpendicular recording mode, CMOS disk in­terface, and a high performance analog data separator.

The FDC supports the standard PC data rates of 250 kb/s,
300 kb/s and 500 kb/s, and 1 Mb/s in MFM encoded data
mode, but is no longer guaranteed through functional test­ing to support the older FM encoded data mode. Refer­ences to the older FM mode remain in this document to
clarify the true functional operation of the device.

The 1 Mb/s data rate is used by new high performance tape
and floppy drives emerging in the PC market today. The new
floppy drives utilize high density media which requires the
FDC supported perpendicular recording mode format. When
used with the 1 Mb/s data rate this new format allows the
use of 4 MB floppy drives which format ED media to 2.88
MB data capacity.

The high performance internal analog data separator needs
no external components. It improves on the window margin
performance standards of the DP8473, and is compatible
with the strict data separator requirements of floppy and
floppy-tape drives.

17

3.0 FDC Register Description (Continued)

FIGURE 3-1. FDC Functional Block Diagram

The FDC contains write precompensation circuitry that will
default to 125 ns for 250, 300, and 500 kb/s (41.67 ns at
1 Mb/s). These values can be overridden in software to
disable write precompensation or to provide levels of pre­compensation up to 250 ns. The FDC has internal 24 mA
data bus buffers which allow direct connection to the sys­tem bus. The internal 40 mA totem-pole disk interface buff­ers are compatible with both CMOS drive inputs and 150X
resistor terminated disk drive inputs.

The following FDC registers are mapped into the addresses
shown below, with the base address range being provided
by the on-chip address decoder pin. For PC-AT or PS/2
applications, the diskette controller primary address range is
3F0 to 3F7 (hex), and the secondary address range is 370
to 377 (hex). The FDC supports three different register
modes: the PC-AT mode, PS/2 mode (Micro Channel sys­tems), and the Model 30 mode (Model 30). See Section 5.1
for more details on how each register mode is enabled.
When applicable, the register definition for each mode of
operation will be given. If no special notes are made, then
the register is valid for all three register modes.

TL/F/11362– 4

TABLE 3-1. Register Description and Addresses

A2 A1 A0 IDENT R/W Register

0 0 0 0 R Status Register A SRA
0 0 1 0 R Status Register B SRB
0 1 0 X R/W Digital Output Register DOR
0 1 1 X R/W Tape Drive Register TDR
1 0 0 X R Main Status Register MSR
1 0 0 X W Data Rate Select Register DSR
1 0 1 X R/W Data Register (FIFO) FIFO
1 1 0 X X None (Bus TRI-STATE)
1 1 1 X R Digital Input Register DIR
1 1 1 X W Configuration Control Register CCR

Note: SRA and SRB are enabled by IDENTe0 during a chip reset only.

3.1 STATUS REGISTER A (SRA) Read Only

This is a read-only diagnostic register that is part of the
PS/2 floppy controller register set, and is enabled when in
the PS/2 or Model 30 mode. This register monitors the state
of the IRQ6 pin and some of the disk interface signals. The
SRA can be read at any time when in PS/2 mode. In the
PC-AT mode, D7 – D0 are TRI-STATE during a mP read.

18

3.0 FDC Register Description (Continued)

3.1.1 SRAÐPS/2 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC IRQ6

RESET
COND

D7 Interrupt Pending: This active high bit reflects the

D6 2nd Drive Installed

D5 Step: Active high status of the STEP disk interface

D4 Track 0

D3 Head Select: Active high status of the HDSEL disk

D2 Index

D1 Write Protect

D0 Direction: Active high status of the DIR disk inter-

3.1.2 SRAÐ Model 30 Mode

DESC IRQ6

RESET
COND

D7 Interrupt Pending: This active high bit reflects that

D6 DMA Request: Active high status of the DRQ signal.

D5 Step: Active high status of the latched STEP disk

D4 Track 0: Active high status of TRK0 disk interface

D3 Head Select

D2 Index: Active high status of the INDEX disk inter-

D1 Write Protect: Active high status of the WP disk

D0 Direction

DRV2

PEND

0 N/A 0 N/A 0 N/A N/A 0

STEP TRK0 HDSEL INDX WP DIR

state of the IRQ6 pin.

: Active low status of the
DRV2 disk interface input, indicating if a second
drive has been installed.

output.

: Active low status of the TRK0 disk inter-

face input.

interface output.

: Active low status of the INDEX disk interface

input.

: Active low status of the WP disk in-

terface input.

face output.

D7 D6 D5 D4 D3 D2 D1 D0

DRQ STEP TRK0 HDSEL

PEND

0 0 0 N/A 1 N/A N/A 1

INDX WP DIR

state of the IRQ6 pin.

interface output. This bit is latched with the STEP
output going active, and is cleared with a read from
the DIR, or with a hardware or software reset.

input.

: Active low status of the HDSEL disk

interface output.

face input.

interface input.

: Active low status of the DIR disk inter-

face output.

3.2 STATUS REGISTER B (SRB) Read Only

This is a read-only diagnostic register that is part of the
PS/2 floppy controller register set, and is enabled when in
the PS/2 or Model 30 mode. The SRB can be read at any
time when in PS/2 mode. In the PC-AT mode, D7–D0 are
TRI-STATE during a mP read.

3.2.1 SRBÐPS/2 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC 1 1 DR0 WDATA RDATA WGATE MTR1 MTR0

RESET

N/A N/A 0 0 0 0 0 0

COND

D7 Reserved: Always 1.

D6 Reserved: Always 1.

D5 Drive Select 0: Reflects the status of the Drive Se-

lect 0 bit in the DOR (address 2, bit 0). This bit is
cleared after a hardware reset, not a software reset.

D4 Write Data: Every inactive edge transition of the

WDATA disk interface output causes this bit to
change states.

D3 Read Data: Every inactive edge transition of the

RDATA disk interface output causes this bit to
change states.

D2 Write Gate: Active high status of the WGATE disk

interface output.

D1 Motor Enable 1: Active high status of the MTR1

disk interface output. Low after a hardware reset,
unaffected by a software reset.

D0 Motor Enable 0: Active high status of the MTR0

disk interface output. Low after a hardware reset,
unaffected by a software reset.

3.2.2 SRBÐModel 30 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC DRV2 DR1 DR0 WDATA RDATA WGATE DR3 DR2

RESET

N/A 1 1 0 0 0 1 1

COND

D7 2nd Drive Installed: Active low status of the

DRV2 disk interface input.

D6 Drive Select 1

: Active low status of the DR1 disk

interface output.

D5 Drive Select 0

: Active low status of the DR0 disk

interface output.

D4 Write Data: Active high status of latched WDATA

signal. This bit is latched by the inactive going edge
of WDATA and is cleared by a read from the DIR.
This bit is not gated by WGATE.

19

3.0 FDC Register Description (Continued)

D3 Read Data: Active high status of latched RDATA

signal. This bit is latched by the inactive going edge
of RDATA and is cleared by a read from the DIR.

D2 Write Gate: Active high status of latched WGATE

signal. This bit is latched by the active going edge of
WGATE and is cleared by a read from the DIR.

D1 Drive Select 3

interface output. (Note 1)

D0 Drive Select 2

interface output. (Note 1)

3.3 DIGITAL OUTPUT REGISTER (DOR) Read/Write

The DOR controls the drive select and motor enable disk
interface outputs, enables the DMA logic, and contains a
software reset bit. The content of the DOR is set to 00 (hex)
after a hardware reset, and is unaffected by a software re­set. (Note 2)

DOR

D7 D6 D5 D4 D3 D2 D1 D0

DESC MTR3 MTR2 MTR1 MTR0 DMAEN RESET

RESET

0000 0 0 0 0

COND

D7 Motor Enable 3: This bit controls the MTR3 disk

interface output.A1inthis bit causes the MTR3 pin
to go active. (Note 1)

D6 Motor Enable 2: Same function as D7 except for

MTR2. (Note 1)

D5 Motor Enable 1: Same function as D7 except for

MTR1.

D4 Motor Enable 0: Same function as D7 except for

MTR0.

D3 DMA Enable: This bit has two modes of operation.

PC-AT mode or Model 30 mode: Writinga1tothis

bit will enable the DRQ, DACK
Writinga0tothis bit will disable the DACK
pins and TRI-STATE the DRQ and the IRQ6 pins.
This bit is a 0 after a reset when in these modes.
PS/2 mode: This bit is reserved, and the DRQ,
DACK

, TC, and IRQ6 pins will always be enabled.
During a reset, the DRQ, DACK
will remain enabled, and D3 will be a 0.

D2 Reset Controller: Writinga0tothis bit resets the

controller. It will remain in the reset condition until a
1 is written to this bit. A software reset does not
affect the DSR, CCR, and other bits of the DOR. A
software reset will affect the Configure and Mode
command bits (see Section 4.0 Command Set De­scription). The minimum time that this bit must be
low is 100 ns. Thus, toggling the Reset Controller bit
during consecutive writes to the DOR is an accept­able method of issuing a software reset.

D1,D0 Drive Select: These two bits are binary encoded for

the four drive selects DR0–DR3, so that only one
drive select output is active at a time. (Note 1)

: Active low status of the DR3 disk

: Active low status of the DR2 disk

DRIVE DRIVE

SEL 1 SEL 0

, TC, and IRQ6 pins.

and TC

, TC, and IRQ6 lines

It is common programming practice to enable both the mo­tor enable and drive select outputs for a particular drive.
Table 3-2 below shows the DOR values to enable each of
the four drives.

TABLE 3-2. Drive Enable Values

Drive DOR Value

0 1C (hex)
12D
24E
38F

3.4 TAPE DRIVE REGISTER (TDR) Read/Write

This register is used to assign a particular drive number with
the tape drive support mode of the data separator. All other
logical drives are assigned floppy drive support with the
data separator. Any future reference to the assigned tape
drive will invoke tape drive support. The TDR is unaffected
by a software reset.

TDR

D7 D6 D5 D4 D3 D2 D1 D0

DESC

RESET
COND

XXXXXX

N/A N/A N/A N/A N/A N/A 0 0

TAPE TAPE
SEL 1 SEL 0

D7–D2 Reserved: These bits are ignored when written to

and are TRI-STATE when read.

D1,D0 Tape Select 1,0: These two bits assign a logical

drive number to be a tape drive. Drive 0 is not avail­able as a tape drive, and is reserved as the floppy
disk boot drive. See Table 3-3 for the tape drive
assignment values.

TABLE 3-3. Tape Drive Assignment Values

TAPESEL1 TAPESEL0

Drive

Selected

0 0 None
011
102
113

3.5 MAIN STATUS REGISTER (MSR) Read Only

The read-only Main Status Register indicates the current
status of the disk controller. The Main Status Register is
always available to be read. One of its functions is to control
the flow of data to and from the Data Register (FIFO). The
Main Status Register indicates when the disk controller is
ready to send or receive data through the Data Register. It
should be read before each byte is transferred to or from
the Data Register except during a DMA transfer. No delay is
required when reading this register after a data transfer.

Note 1: The MTR3, MTR2, DRV3, DRV2 pins are only available in 4-drive mode (FER4e1) and require external logic.

Note 2: The DOR can be written to at any time, but only one drive select output in conjunction with its corresponding motor is active at a time.

20

3.0 FDC Register Description (Continued)

After a hardware or software reset, or recovery from a pow­er down state, the Main Status Register is immediately avail­able to be read by the mP. It will contain a value of 00 hex
until the oscillator circuit has stabilized, and the internal reg­isters have been initialized. When the FDC is ready to re­ceive a new command, it will report an 80 hex to the mP.
The system software can poll the MSR until it is ready. The
worst case time allowed for the MSR to report an 80 hex
value (RQM set) is 2.5 ms after reset or power up.

MSR

D7 D6 D5 D4 D3 D2 D1 D0

DESC RQM DIO NON CMD DRV3 DRV2 DRV1 DRV0

RESET

0000 0000

COND

D7 Request for Master: Indicates that the controller is

ready to send or receive data from the mP through
the FIFO. This bit is cleared immediately after a byte
transfer and will become set again as soon as the
disk controller is ready for the next byte. During a
Non-DMA Execution phase, the RQM indicates the
status of the interrupt pin.

D6 Data I/O (Direction): Indicates whether the con-

troller is expecting a byte to be written to (0) or read
from (1) the Data Register.

D5 Non-DMA Execution: Indicates that the controller

is in the Execution Phase of a byte transfer opera­tion in the Non-DMA mode. Used for multiple byte
transfers by the mP in the Execution Phase through
interrupts or software polling.

D4 Command in Progress: This bit is set after the first

byte of the Command Phase is written. This bit is
cleared after the last byte of the Result Phase is
read. If there is no Result Phase in a command, the
bit is cleared after the last byte of the Command
Phase is written.

D3 Drive 3 Busy: Set after the last byte of the Com-

mand Phase of a Seek or Recalibrate command is
issued for drive 3. Cleared after reading the first
byte in the Result Phase of the Sense Interrupt
Command for this drive.

D2 Drive 2 Busy: Same as above for drive 2.

D1 Drive 1 Busy: Same as above for drive 1.

D0 Drive 0 Busy: Same as above for drive 0.

3.6 DATA RATE SELECT REGISTER (DSR) Write Only

This write-only register is used to program the data rate,
amount of write precompensation, power down mode, and
software reset. The data rate is programmed via the CCR,
not the DSR, for PC-AT and PS/2 Model 30 and MicroChan­nel applications. Other applications can set the data rate in
the DSR. The data rate of the floppy controller is deter­mined by the most recent write to either the DSR or CCR.

DMA PROG BUSY BUSY BUSY BUSY

The DSR is unaffected by a software reset. A hardware re­set will set the DSR to 02 (hex), which corresponds to the
default precompensation setting and 250 kb/s.

DSR

D7 D6 D5 D4 D3 D2 D1 D0

DESC S/W LOW0PRE- PRE- PRE-

RESET POWER COMP2 COMP1 COMP0

RESET

0000001 0

COND

DRATE1 DRATE0

D7 Software Reset: This bit has the same function as

the DOR RESET (D2) except that this software re­set is self-clearing.

D6 Low Power: A 1 to this bit will put the controller into

the Manual Low Power mode. The oscillator and
data separator circuits will be turned off. Manual
Low Power can also be accessed via the Mode
command. The chip will come out of low power after
a software reset, or access to the Data Register or
Main Status Register.

D5 Undefined. Should be set to 0.

D4–D2 Precompensation Select: These three bits select

the amount of write precompensation the floppy
controller will use on the WDATA disk interface out­put. Table 3-4 shows the amount of precompensa­tion used for each bit pattern. In most cases, the
default values (Table 3-5) can be used; however,
alternate values can be chosen for specific types of
drives and media. Track 0 is the default starting
track number for precompensation. The starting
track number can be changed in the Configure com­mand.

TABLE 3-4. Write Precompensation Delays

Precomp 432 Precompensation Delay

111 0.0 ns
001 41.7 ns
010 83.3 ns
011 125.0 ns
100 166.7 ns
101 208.3 ns
110 250.0 ns
000 DEFAULT

TABLE 3-5. Default Precompensation Delays

Data Rate Precompensation Delay

1 Mb/s 41.7 ns
500 kb/s 125.0 ns
300 kb/s 125.0 ns
250 kb/s 125.0 ns

21

3.0 FDC Register Description (Continued)

D1,D0 Data Rate Select 1,0: These bits determine the

data rate for the floppy controller. See Table 3-6 for
the corresponding data rate for each value of D1,
D0. The data rate select bits are unaffected by a
software reset, and are set to 250 kb/s after a hard­ware reset.

TABLE 3-6. Data Rate Select Encoding

Data Rate Select Data Rate

1 0 MFM FM

1 1 1 Mb/s Illegal
0 0 500 kb/s 250 kb/s
0 1 300 kb/s 150 kb/s
1 0 250 kb/s 125 kb/s

Note: FM mode is not guaranteed through functional testing.

3.7 DATA REGISTER (FIFO) Read/Write

The FIFO (read/write) is used to transfer all commands,
data, and status between the mP and the FDC. During the
Command Phase, the mP writes the command bytes into the
FIFO after polling the RQM and DIO bits in the MSR. During
the Result Phase, the mP reads the result bytes from the
FIFO after polling the RQM and DIO bits in the MSR.

The enabling of the FIFO and setting of the FIFO threshold
is done via the Configure command. If the FIFO is enabled,
only the Execution Phase byte transfers use the 16 byte
FIFO. The FIFO is always disabled during the Command
and Result Phases of a controller operation. If the FIFO is
enabled, it will not be disabled after a software reset if the
LOCK bit is set in the Lock Command. After a hardware
reset, the FIFO is disabled to maintain compatibility with
PC-AT systems.

The 16-byte FIFO can be used for DMA, Interrupt, or soft­ware polling type transfers during the execution of a read,
write, format, or scan command. In addition, the FIFO can
be put into a Burst or Non-Burst mode with the Mode com­mand. In the Burst mode, DRQ or IRQ6 remains active until
all of the bytes have been transferred to or from the FIFO. In
the Non-Burst mode, DRQ or IRQ6 is deasserted for 350 ns
to allow higher priority transfer requests to be serviced. The
Mode command can also disable the FIFO for either reads
or writes separately. The FIFO allows the system a larger
latency without causing a disk overrun/underrun error. Typi­cal uses of the FIFO would be at the 1 Mb/s data rate, or
with multi-tasking operating systems. The default state of
the FIFO is disabled, with a threshold of zero. The default
state is entered after a hardware reset.

Data Register (FIFO)

D7 D6 D5 D4 D3 D2 D1 D0

Byte Mode

DRP

]

b

(16ct

ICP

)

DESC Data[7:0

RESET
COND

During the Execution Phase of a command involving data
transfer to/from the FIFO, the system must respond to a
data transfer service request based on the following formu­la:

Maximum Allowable Data Transfer Service Time

(THRESH

a

1)c8ct

This formula is good for all data rates with the FIFO enabled
or disabled. THRESH is a four bit value programmed in the

Configure command, which sets the FIFO threshold. If the
FIFO is disabled, THRESH is zero in the above formula. The
last term of the formula, (16
to the microcode overhead required by the FDC. This delay
is also data rate dependent. See Table 9-1 for the t
t

times.

ICP

c

t

) is an inherent delay due

ICP

DRP

and

The programmable FIFO threshold (THRESH) is useful in
adjusting the floppy controller to the speed of the system. In
other words, a slow system with a sluggish DMA transfer
capability would use a high value of THRESH, giving the
system more time to respond to a data transfer service re­quest (DRQ for DMA mode or IRQ6 for Interrupt mode).
Conversely, a fast system with quick response to a data
transfer service request would use a low value of THRESH.

3.8 DIGITAL INPUT REGISTER (DIR) Read Only

This diagnostic register is used to detect the state of the
DSKCHG disk interface input and some diagnostic signals.
The function of this register depends on the register mode
of operation. When in the PC-AT mode, the D6 – D0 are
TRI-STATE to avoid conflict with the fixed disk status regis­ter at the same address. The DIR is unaffected by a soft­ware reset.

3.8.1 DIRÐPC-AT Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC DSKCHG XXXXXXX

RESET
COND

N/A N/A N/A N/A N/A N/A N/A N/A

D7 Disk Changed: Active high status of DSKCHG disk

interface input. During power down this bit will be
invalid, if it is read by the software.

D6–D0 Undefined: TRI-STATE. Used by Hard Disk Con-

troller Status Register.

3.8.2 DIRÐPS/2 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC

DSKCHG 1 1 1 1 DRATE1 DRATE0

RESET

N/A N/A N/A N/A N/A N/A N/A 1

COND

1

HIGH

DEN

D7 Disk Changed: Active high status of DSKCHG disk

interface input. During power down this bit will be
invalid, if it is read by the software.

D6–D3 Reserved: Always 1.

D2,D1 Data Rate Select 1,0: These bits indicate the

status of the DRATE1,0 bits programmed through
the DSR CCR.

D0 High Density

: This bit is low when the 1 Mb/s or

500 kb/s data rate is chosen, and high when the
300 kb/s or 250 kb/s data rate is chosen. This bit is
independent of the IDENT value.

3.8.3 DIRÐModel 30 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC DSKCHG 0 0 0 DMAEN NOPRE DRATE1 DRATE0

RESET

N/A 0 0 0 0 0 1 0

COND

22

3.0 FDC Register Description (Continued)

D7 Disk Changed

interface input. During power down this bit will be
invalid, if it is read by the software.

D6–D4 Reserved: Always 0.

D3 DMA Enable: Active high status of the DMAEN bit

in the DOR.

D2 No Precompensation: Active high status of the

NOPRE bit in the CCR.

D1,D0 Data Rate Select 1,0: These bits indicate the

status of the DRATE 1,0 bits programmed through
the DSR/CCR.

3.9 CONFIGURATION CONTROL REGISTER (CCR)

Write Only

This is the write-only data rate register commonly used in
PC-AT applications. This register is not affected by a soft­ware reset, and is set to 250 kb/s after a hardware reset.
The data rate of the floppy controller is determined by the
last write to either the CCR or DSR.

3.9.1 CCRÐPC-AT and PS/2 Modes

D7 D6 D5 D4 D3 D2 D1 D0

DESC 000000DRATE1 DRATE0

RESET

N/A N/A N/A N/A N/A N/A 1 0

COND

D7–D2 Reserved: Should be set to 0.

D1,D0 Data Rate Select 1,0: These bits determine the

data rate of the floppy controller. See Table 3-6 for
the appropriate values.

3.9.2 CCRÐModel 30 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC 0 0 0 0 0 NOPRE DRATE1 DRATE0

RESET

N/A N/A N/A N/A N/A N/A 1 0

COND

D7–D3 Reserved: Should be set to 0.

D2 No Precompensation: This bit can be set by soft-

ware, but it has no functionality. It can be read by bit
D2 of the DIR when in the Model 30 register mode.
Unaffected by a software reset.

D1,D0 Data Rate Select 1,0: These bits determine the

data rate of the floppy controller. See Table 3-6 for
the appropriate values.

3.10 RESULT PHASE STATUS REGISTERS

The Result Phase of a command contains bytes that hold
status information. The format of these bytes is described
below. Do not confuse these status bytes with the Main
Status Register, which is a read only register that is always
valid. The Result Phase status registers are read from the
Data Register (FIFO) only during the Result Phase of certain
commands (see Section 4.1 Command Set Summary). The
status of each register bit is indicated when the bit is a 1.

3.10.1 Status Register 0 (ST0)

D7 D6 D5 D4 D3 D2 D1 D0

DESC IC IC SE EC 0 HDS DS1 DS0

RESET
COND

00000 0 0 0

: Active low status of DSKCHG disk

D7–D6 Interrupt Code:

00eNormal Termination of Command.

01eAbnormal Termination of Command. Execu-

tion of command was started, but was not
successfully completed.

e

10

Invalid Command Issued. Command issued
was not recognized as a valid command.

e

11

Internal drive ready status changed state dur­ing the drive polling mode. Only occurs after a
hardware or software reset.

D5 Seek End: Seek, Relative Seek, or Recalibrate

command completed by the controller. (Used during
a Sense Interrupt command.)

D4 Equipment Check: After a Recalibrate command,

Track 0 signal failed to occur. (Used during Sense
Interrupt command.)

D3 Not Used. Always 0.

D2 Head Select: Indicates the active high status of the

HDSEL pin at the end of the Execution Phase.

D1,D0 Drive Select 1,0: These two binary encoded bits

indicate the logical drive selected at the end of the
Execution Phase.

e

00

Drive 0 selected.

01eDrive 1 selected.

10eDrive 2 selected.

e

Drive 3 selected.

11

3.10.2 Status Register 1 (ST1)

D7 D6 D5 D4 D3 D2 D1 D0

DESC ET 0 CE OR 0 ND NW MA

RESET
COND

000 00 0 0 0

D7 End of Track: Controller transferred the last byte of

the last sector without the TC pin becoming active.
The last sector is the End of Track sector number
programmed in the Command Phase.

D6 Not Used. Always 0.

D5 CRC Error: If this bit is set and bit 5 of ST2 is clear,

then there was a CRC error in the Address Field of
the correct sector. If bit 5 of ST2 is also set, then
there was a CRC error in the Data Field.

D4 Overrun: Controller was not serviced by the mP

soon enough during a data transfer in the Execution
Phase. For read operations, indicates a data over­run. For write operations, indicates a data underrun.

D3 Not Used. Always 0.

D2 No Data: Three possible problems:

1. Controller cannot find the sector specified in the
Command Phase during the execution of a Read,
Write, Scan, or Verify command. An address
mark was found however, so it is not a blank disk.

2. Controller cannot read any Address Fields with­out a CRC error during a Read ID command.

3. Controller cannot find starting sector during exe­cution of Read A Track command.

D1 Not Writable: Write Protect pin is active when a

Write or Format command is issued.

23

3.0 FDC Register Description

(Continued)

D0 Missing Address Mark: If bit 0 of ST2 is clear then

the controller cannot detect any Address Field Ad­dress Mark after two disk revolutions. If bit 0 of ST2
is set then the controller cannot detect the Data
Field Address Mark after finding the correct Ad­dress Field.

3.10.3 Status Register 2 (ST2)

D7 D6 D5 D4 D3 D2 D1 D0

DESC 0 CM CD WT SEH SNS BT MD

RESET
COND

D7 Not Used. Always 0.

D6 Control Mark: Controller tried to read a sector

D5 CRC Error in Data Field: Controller detected a

D4 Wrong Track: Only set if desired sector is not

D3 Scan Equal Hit: ‘‘Equal’’ condition satisfied during

D2 Scan Not Satisfied: Controller cannot find a sector

D1 Bad Track: Only set if the desired sector is not

D0 Missing Address Mark in Data Field: Controller

3.10.4 Status Register 3 (ST3)

DESC 0 WP 1 TK0 1 HDS DS1 DS0

RESET
COND

D7 Not Used. Always 0.

D6 Write Protect: Indicates active high status of the

D5 Not Used. Always 1.

D4 Track 0: Indicates active high status of the TRK0

D3 Not Used. Always 1.

D2 Head Select: Indicates the active high status of the

D1,D0 Drive Select 1,0: These two binary encoded bits

0000 0 0 00

which contained a deleted data address mark dur­ing execution of Read Data or Scan commands. Or,
if a Read Deleted Data command was executed, a
regular address mark was detected.

CRC error in the Data Field. Bit 5 of ST1 is also set.

found, and the track number recorded on any sector
of the current track is different from the track ad­dress specified in the Command Phase.

any Scan command.

on the track which meets the desired condition dur­ing any Scan command.

found, the track number recorded on any sector on
the track is FF (hex) indicating a hard error in IBM
format, and is different from the track address spec­ified in the Command Phase.

cannot find the Data Field AM during a Read, Scan,
or Verify command. Bit 0 of ST1 is also set.

D7 D6 D5 D4 D3 D2 D1 D0

001010 0 0

WP pin.

pin.

HD bit in the Command Phase.

indicate the DS1,DS0 bits in the Command Phase.

4.0 FDC Command Set Description

The following is a table of the FDC command set. Each
command contains a unique first command byte called the
opcode byte which will identify to the controller how many
command bytes to expect. If an invalid command byte is
issued to the controller, it will immediately go into the Result
Phase and the status will be 80 (hex), which signifies Invalid
Command.

4.1 COMMAND SET SUMMARY

CONFIGURE

Command Phase

0 0 0 1 0011

0 0 0 0 0000

0 EIS FIFO POLL THRESH

PRETRK

Execution Phase: Internal registers written.

No Result Phase

DUMPREG

Command Phase

00001110

Execution Phase: Internal registers read.

Result Phase

PTR Drive 0

PTR Drive 1

PTR Drive 2

PTR Drive 3

Step Rate Time Motor Off Time

Motor On Time DMA

Sector per Track/End of Track

LOCK 0 DC3 DC2 DC1 DC0 GAP WG

0 EIS FIFO POLL THRESH

PRETRK

Note: Sectors per Track parameter returned if last command issued was
Format. End of Track parameter returned if last command issued was Read
or Write.

FORMAT TRACK

Command Phase

0 MFM 0 0 1 1 0 1

X X XXXHDDR1DR0

Bytes per Sector

Sectors per Track

Format Gap

Data Pattern

Execution Phase: System transfers four ID bytes (track,
head, sector, bytes/sector) per sector to the floppy control­ler via DMA or Non-DMA modes. The entire track is format­ted. The data block in the Data Field of each sector is filled
with the data pattern byte.

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