NSC PC87303-IAT-VUL Datasheet

TL/C/12074

PC87303VUL SuperI/O Sidewinder Lite Floppy Disk Controller, Keyboard Controller,

Real-Time Clock, Dual UARTs, IEEE 1284 Parallel Port, and IDE Interface

PRELIMINARY

February 1995

PC87303VUL SuperI/OTMSidewinder Lite Floppy Disk Controller, Keyboard Controller, Real-Time Clock, Dual UARTs, IEEE 1284 Parallel Port, and IDE Interface

General Description

The PC87303VUL is a single chip solution incorporating a Keyboard and PS/2

Mouse Controller (KBC), Real Time Clock (RTC) and most commonly used I/O peripherals in ISA, EISA and MicroChannel

based computers. In addition to the KBC and RTC, a Floppy Disk Controller (FDC), two full featured UARTs, an IEEE 1284 compatible parallel port and all the necessary control logic for an IDE interface provides support for most commonly used I/O peripherals. Standard PC-AT

address decoding for all the peripherals, a set of configuration registers, and two user selectable chip selects are also implemented in this highly integrated member of the SuperI/O family. The advanced features and high integration of the PC87303 result in several benefits for low cost, high performance systems. Printed circuit board space savings, fewer components on the motherboard and compatibility with the latest industry standard peripherals are only a few of the benefits of using a PC87303.

The KBC is fully software compatible with the 8042AH microcontroller. It contains system timing, control logic, custom ROM program memory, RAM data memory and 18 programmable I/O lines necessary to implement dedicated control functions. It is an efficient controller which uses predominantly single byteinstructions withsupport for binary and BCD arithmetic and extensive bit handling capabilities.

(Continued)

Features

The Floppy Disk Controller: Ð Software compatible with the DP8477, the 765A and

the N82077 Ð 16-byte FIFO (disabled by default) Ð Burst and Non-Burst modes Ð Perpendicular Recording drive support Ð High performance internal analog data separator

(no external filter components required) Ð Low power CMOS with power-down mode Ð Automatic media-sense support with full IBM TDR

(Tape Drive Register) implementation for PC-AT and

PS/2 floppy drive types

The Keyboard Controller: Ð 8042AH and PC87911 software compatible Ð 8-bit Microcomputer with 2 kbytes custom ROM and

256 bytes data RAM Ð Asynchronous access to two data registers and one

status register during normal operation Ð Dedicated open drain outputs for keyboard controller

application Ð Supports both interrupt and polling Ð Supports DMA handshake Ð 18 programmable I/O pins Ð 4 dedicated open-drain outputs Ð 8-bit Timer/Counter Ð Binary and BCD arithmetic Ð Expandable I/O (Continued)

Block Diagram

TL/C/12074– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation. SuperI/O

is a trademark of National Semiconductor Corporation.

MicroChannel

, PC-ATÉand PS/2Éare registered trademarks of International Business Machines Corporation.

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

General Description (Continued)

The RTC is a low-power design that provides a time-of-day clock, a 100-year calendar, several alarm features and 242 bytes of general purpose RAM. An external battery is used to maintain the time and contents of the general purpose RAM, when power is removed from the PC87303. The PC87303 RTC is compatible with the DS1287 and MC146818 RTC devices.

The PC87303 FDC uses a high performance analog data separator eliminating need for any external filter components. The FDC is fully compatible with the PC8477 and incorporates a superset of DP8473, NEC mPD765 and N82077 floppy disk controller function. All popular 5.25

and 3.5×floppy drives, including 2.88 MB 3.5×floppy drive, are supported. Full TDR support for PC-AT and PS/2 floppy drive types is also provided.

The two UARTs are fully NS16450 and NS16550 compatible.

The parallel port is fully IEEE 1284 level 2 compatible. The SPP (Standard Parallel Port) is fully compatible with ISA, EISA and MicroChannel parallel ports. In addition to the SPP, EPP (Enhanced Parallel Port) and ECP (Extended Capabilities Port) modes are supported by the parallel port.

All IDE control signals with DMA support, including support for Type F DMA are provided by the PC87303. Only external signal buffers are required to implement a complete IDE interface.

A set of fourteen configuration registers are provided to control various functions of the PC87303. These registers are accessed using two 8-bit wide index and data registers. The ISA I/O address of the register pair can be relocated using a power-up strapping option.

Two general purpose user programmable chip selects are available. These chip selects can be used to decode game port addresses.

Features (Continued)

The Real-Time Clock: Ð DS1287, MC146818 and PC87911 compatible Ð 242 bytes battery backed-up CMOS RAM in two

banks

Ð Selective lock mechanism locks any half of the RTC

RAM

Ð Calendar in days, day of the week, months and

years with automatic leap-year adjustment

Ð Time of day in seconds, minutes and hours:

Ð12 or 24 hour format

Ð Optional daylight savings adjustment Ð BCD or binary format for time keeping Ð Three individually maskable interrupt event flags:

ÐPeriodic rates from 122 ms to 500 ms

ÐTime-of-day alarm once per second to once per

day Ð Separate battery pin, 2.4V operation Ð2mA power consumption Ð Double buffer time registers

The UARTs: Ð Software compatible with the PC16550A and

NS16450

Parallel Port: Ð EPP, ECP compatible with ECP level 2 support Ð ISA, EISA and MicroChannel compatible architecture Ð Bi-directional data transfer under software or hard-

ware control

Ð Includes protection circuit to prevent damage to the

parallel port when a connected printer is powered up or is operated at a higher voltage

IDE: Ð All IDE control signals, with DMA and support for

Type F DMA. Only external signal buffers are required to implement the full IDE interface

The Programmable Chip Selects: Ð Separater pins for two user programmable chip se-

lect decoders provide ability to control a game port

The address decoder: Ð Provides selection of all primary and secondary ISA

addresses including COM1– 4

General: Ð Low power CMOS technology Ð Ability to stop clocks to all modules Ð The PC87303 is a drop-in replacement for the

PC87323VUL Ð Reduced pin leakage current Ð Special configuration register for power-down Ð Disable bit for RTC Ð 160-pin PQFP package

Table of Contents

1.0 PIN DESCRIPTIONАААААААААААААААААААААААААААААА10

2.0 CONFIGURATION REGISTERS АААААААААААААААААА16

2.1 Overview ААААААААААААААААААААААААААААААААААААА16

2.2 Software Configuration ААААААААААААААААААААААААА16

2.3 Hardware Configuration АААААААААААААААААААААААА19

2.4 Index and Data Registers ААААААААААААААААААААААА19

2.5 Base Configuration Registers ААААААААААААААААААА21

2.5.1 Function Enable Register АААААААААААААААААА21

2.5.2 Function Address RegisterААААААААААААААААА22

2.5.3 Power and Test Register АААААААААААААААААА22

2.5.4 Function Control Register ААААААААААААААААА23

2.5.5 Printer Control Register ААААААААААААААААААА23

2.5.6 KBC and BTC Control Register ААААААААААААА24

2.5.7 Power Management Control Register ААААААА24

2.5.8 Tape, UARTs and Parallel Port Configuration RegisterААААААААААААААААААААААААААААААААА25

2.5.9 SIO Identification Register ААААААААААААААААА25

2.5.10 Advanced SIO Configuration Register АААААА25

2.5.11 Chip Select 0 Configuration Register 0 ААААА25

2.5.12 Chip Select 0 Configuration Register 1 ААААА25

2.5.13 Chip Select 1 Configuration Register 0 ААААА26

2.5.14 Chip Select 1 Configuration Register 1 ААААА26

2.6 Power-Down Options АААААААААААААААААААААААААА26

2.7 Power-Up Procedure and Considerations ААААААААА26

2.7.1 Crystal Stabilization ААААААААААААААААААААААА26

2.7.2 UART Power-Up ААААААААААААААААААААААААА26

2.7.3 FDC Power-Up ААААААААААААААААААААААААААА26

3.0 FDC REGISTER DESCRIPTION АААААААААААААААААА27

3.1 FDC Control Registers ААААААААААААААААААААААААА28

3.1.1 Status Register A (SRA) ААААААААААААААААААА28

3.1.2 Status Register B (SRB) ААААААААААААААААААА28

3.1.3 Digital Output Register (DOR) АААААААААААААА29

3.1.4 Tape Drive Register (TDR)ААААААААААААААААА29

3.1.5 Main Status Register (MSR) ААААААААААААААА31

3.1.6 Data Rate Select Register (DSR) ААААААААААА31

3.1.7 Data Register (FIFO)АААААААААААААААААААААА32

3.1.8 Digital Input Register (DIR) АААААААААААААААА32

3.1.9 Configuration Control Register (CCR) ААААААА33

3.2 Result Phase Status Registers АААААААААААААААААА33

3.2.1 Status Register 0 (ST0) ААААААААААААААААААА33

3.2.2 Status Register 1 (ST1) ААААААААААААААААААА33

3.2.3 Status Register 2 (ST2) ААААААААААААААААААА34

3.2.4 Status Register 3 (ST3) ААААААААААААААААААА34

4.0 FDC COMMAND SET DESCRIPTION ААААААААААААА34

4.1 Command Descriptions АААААААААААААААААААААААА34

4.1.1 Configure Command АААААААААААААААААААААА34

4.1.2 Dumpreg Command АААААААААААААААААААААА35

4.1.3 Format Track CommandААААААААААААААААААА35

4.1.4 Invalid CommandААААААААААААААААААААААААА38

4.1.5 Lock Command АААААААААААААААААААААААААА38

4.1.6 Mode Command ААААААААААААААААААААААААА38

4.1.7 NSC Command АААААААААААААААААААААААААА39

4.1.8 Perpendicular Mode CommandААААААААААААА40

4.1.9 Read Data Command ААААААААААААААААААААА41

4.1.10 Read Deleted Data Command АААААААААААА43

4.1.11 Read ID Command АААААААААААААААААААААА43

4.1.12 Read A Track Command ААААААААААААААААА43

4.1.13 Recalibrate Command ААААААААААААААААААА44

4.1.14 Relative Seek Command ААААААААААААААААА44

4.1.15 Scan Commands АААААААААААААААААААААААА45

4.1.16 Seek Command ААААААААААААААААААААААААА46

4.1.17 Sense Drive Status Command АААААААААААА46

4.1.18 Sense Interrupt CommandАААААААААААААААА46

4.1.19 Set Track Command ААААААААААААААААААААА47

4.1.20 Specify Command ААААААААААААААААААААААА47

4.1.21 Verify Command АААААААААААААААААААААААА48

4.1.22 Version CommandААААААААААААААААААААААА49

4.1.23 Write Data Command АААААААААААААААААААА50

4.1.24 Write Deleted Data Command АААААААААААА50

4.2 Command Set Summary ААААААААААААААААААААААА51

4.3 Mnemonic Definitions for FDC Commands АААААААА56

5.0 FDC FUNCTIONAL DESCRIPTION ААААААААААААААА57

5.1 Microprocessor Interface ААААААААААААААААААААААА57

5.2 Modes of Operation ААААААААААААААААААААААААААА57

5.3 Controller Phases ААААААААААААААААААААААААААААА57

5.3.1 Command Phase ААААААААААААААААААААААААА57

5.3.2 Execution Phase ААААААААААААААААААААААААА57

5.3.2.1 DMA ModeРFIFO Disabled ААААААААА58

5.3.2.2 DMA ModeРFIFO Enabled ААААААААА58

5.3.2.3 Interrupt ModeРFIFO DisabledАААААА59

5.3.2.4 Interrupt ModeРFIFO Enabled АААААА59

5.3.2.5 Software Polling ААААААААААААААААААА59

5.3.3 Result Phase АААААААААААААААААААААААААААА59

5.3.4 Idle Phase ААААААААААААААААААААААААААААААА59

5.3.5 Drive Polling Phase ААААААААААААААААААААААА60

5.4 Data SeparatorАААААААААААААААААААААААААААААААА60

5.5 Crystal Oscillator АААААААААААААААААААААААААААААА62

5.6 Perpendicular Recording ModeАААААААААААААААААА62

5.7 Data Rate Selection ААААААААААААААААААААААААААА64

5.8 Write Precompensation АААААААААААААААААААААААА64

5.9 FDC Low Power Mode Logic АААААААААААААААААААА64

5.10 Reset Operation ААААААААААААААААААААААААААААА64

Table of Contents (Continued)

6.0 SERIAL PORTS АААААААААААААААААААААААААААААААА65

6.1 Serial Port Registers ААААААААААААААААААААААААААА65

6.2 Line Control Register АААААААААААААААААААААААААА65

6.3 Programmable Baud Rate GeneratorААААААААААААА68

6.4 Line Status Register ААААААААААААААААААААААААААА69

6.5 FIFO Control RegisterАААААААААААААААААААААААААА70

6.6 Interrupt Identification Register АААААААААААААААААА70

6.7 Interrupt Enable Register ААААААААААААААААААААААА70

6.8 MODEM Control Register АААААААААААААААААААААА70

6.9 MODEM Status Register ААААААААААААААААААААААА72

6.10 Scratchpad Register АААААААААААААААААААААААААА72

7.0 PARALLEL PORT АААААААААААААААААААААААААААААА72

7.1 Introduction АААААААААААААААААААААААААААААААААА72

7.2 Data Register (DTR) ААААААААААААААААААААААААААА73

7.3 Status Register (STR) АААААААААААААААААААААААААА73

7.4 Control Register (CTR) ААААААААААААААААААААААААА74

7.5 Enhanced Parallel Port Operation ААААААААААААААА74

7.6 Extended Capabilities Parallel PortААААААААААААААА79

7.6.1 IntroductionАААААААААААААААААААААААААААААА79

7.6.2 Software Operation ААААААААААААААААААААААА80

7.7 Register Definitions АААААААААААААААААААААААААААА80

7.8 Software Controlled Data Transfer ААААААААААААААА82

7.9 Automatic Data Transfer ААААААААААААААААААААААА82

7.9.1 Forward Direction АААААААААААААААААААААААА82

7.9.2 ECP Forward Write Cycle АААААААААААААААААА82

7.9.3 Backward Direction ААААААААААААААААААААААА82

7.9.4 ECP Backward Read Cycle АААААААААААААААА82

7.10 FIFO Test Access (Mode 110) ААААААААААААААААА83

7.11 Configuration Registers Access АААААААААААААААА83

7.12 Interrupt Generation АААААААААААААААААААААААААА83

8.0 INTEGRATED DEVICE ELECTRONICS

INTERFACE (IDE) АААААААААААААААААААААААААААААА83

8.1 Introduction АААААААААААААААААААААААААААААААААА83

8.2 IDE Signals ААААААААААААААААААААААААААААААААААА83

9.0 KEYBOARD CONTROLLER AND REAL-TIME

CLOCK АААААААААААААААААААААААААААААААААААААААА85

9.1 PC87303 KBC Function АААААААААААААААААААААААА85

9.1.1 Host System Interface АААААААААААААААААААА86

9.1.2 Program Memory ААААААААААААААААААААААААА87

9.1.3 Data Memory and Registers ААААААААААААААА87

9.1.4 I/O InterfaceААААААААААААААААААААААААААААА88

9.1.5 Timer/Counter ААААААААААААААААААААААААААА89

9.1.6 InterruptsАААААААААААААААААААААААААААААААА89

9.1.7 Oscillator and Instruction TimingАААААААААААА90

9.2 Real Time Clock Function АААААААААААААААААААААА91

9.2.1 Memory Map АААААААААААААААААААААААААААА91

9.2.2 Bus Interface АААААААААААААААААААААААААААА91

9.2.3 Time Generation ААААААААААААААААААААААААА91

9.2.4 Time Keeping АААААААААААААААААААААААААААА92

9.2.5 RAMАААААААААААААААААААААААААААААААААААА93

9.2.6 Power Management АААААААААААААААААААААА93

9.2.7 System Bus Lock Out and Power-Up Detection АААААААААААААААААА93

9.2.8 Oscillator АААААААААААААААААААААААААААААААА93

9.2.9 Interrupt Handling АААААААААААААААААААААААА93

9.2.10 Control RegistersАААААААААААААААААААААААА94

10.0 ELECTRICAL CHARACTERISTICS АААААААААААААА96

10.1 DC Electrical Characteristics ААААААААААААААААААА96

10.1.1 Microprocessor, Parallel Port, and IDE Interface PinsАААААААААААААААААААААААААА97

10.1.2 Disk Interface Pins ААААААААААААААААААААА97

10.1.3 Oscillator Pins ААААААААААААААААААААААААА97

10.1.4 Parallel Port Pins ААААААААААААААААААААААА97

10.1.5 Keyboard Controller and Real-Time Clock PinsААААААААААААААААААААААААААААА98

10.2 AC Electrical Characteristics ААААААААААААААААААА98

10.2.1 AC Test Conditions ААААААААААААААААААААА98

10.2.2 Clock Timing АААААААААААААААААААААААААА99

10.2.3 Microprocessor Interface Timing АААААААА100

10.2.4 Baud Out Timing АААААААААААААААААААААА102

10.2.5 Transmitter Timing АААААААААААААААААААА102

10.2.6 Receiver Timing АААААААААААААААААААААА103

10.2.7 MODEM Control Timing АААААААААААААААА104

10.2.8 DMA Timing АААААААААААААААААААААААААА105

10.2.9 Reset Timing ААААААААААААААААААААААААА107

10.2.10 FDC Write Data Timing ААААААААААААААА107

10.2.11 FDC Read Data Timing ААААААААААААААА108

10.2.12 Drive Control TimingАААААААААААААААААА108

10.2.13 IDE Timing АААААААААААААААААААААААААА108

10.2.14 Parallel Port Timing АААААААААААААААААА109

10.2.15 Enhanced Parallel Port Timing ААААААААА110

10.2.16 Extended Capabilities Port Timing АААААА111

10.2.17 RTCАААААААААААААААААААААААААААААААА112

10.2.18 Programmable Chip Select Timing ААААА113

List of Figures

FIGURE 2-1 PC87303 Configuration Registers ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА17

FIGURE 2-2 PC87303 Four Floppy Drive Circuit АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА21

FIGURE 3-1 FDC Functional Block Diagram ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА27

FIGURE 4-1 FDC Command Structure АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА34

FIGURE 4-2 IBM, Perpendicular, and ISO Formats Supported by Format Command ААААААААААААААААААААААААААААААААА37

FIGURE 5-1 FDC Data Separator Block Diagram ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА61

FIGURE 5-2 PC87303 Dynamic Window Margin Performance АААААААААААААААААААААААААААААААААААААААААААААААААААА62

FIGURE 5-3 Read Data AlgorithmРState DiagramАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА63

FIGURE 5-4 Perpendicular Recording Drive R/W Head and Pre-Erase Head ААААААААААААААААААААААААААААААААААААААА63

FIGURE 6-1 PC87303 Composite Serial Data АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА65

FIGURE 6-2 Receiver FIFO Trigger LevelАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА70

FIGURE 7-1 EPP 1.7 Address WriteААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА76

FIGURE 7-2 EPP 1.7 Address ReadААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА76

FIGURE 7-3 EPP Write with ZWS ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА77

FIGURE 7-4 EPP 1.9 Address WriteААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА77

FIGURE 7-5 EPP 1.9 Address ReadААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА78

FIGURE 7-6 ECP Forward Write Cycle АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА82

FIGURE 7-7 ECP Backward Read Cycle ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА82

FIGURE 8-1 IDE Interface Signal Equations (Non-DMA) ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА84

FIGURE 9-1 Keyboard Controller Functional Block DiagramАААААААААААААААААААААААААААААААААААААААААААААААААААААА84

FIGURE 9-2 Keyboard Controller to Host System Interface АААААААААААААААААААААААААААААААААААААААААААААААААААААА86

FIGURE 9-3 Status Register ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА86

FIGURE 9-4 PSW Register BitsААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА87

FIGURE 9-5 Keyboard Controller Data Memory Map АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА87

FIGURE 9-6 Keyboard Controller Stack OrganizationАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА87

FIGURE 9-7 Active Pull-Up I/O Port Structure АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА88

FIGURE 9-8 Using Port Pins as InputsААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА88

FIGURE 9-9 Timing Generation and Timer Circuit ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА89

FIGURE 9-10 Internal Clock Connection АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА90

FIGURE 9-11 External Clock Connection ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА90

FIGURE 9-12 Instruction Cycle TimingАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА90

FIGURE 9-13 Oscillator Internal and External CircuitryАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА92

FIGURE 9-14 Interrupt/Status Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА92

FIGURE 9-15 Typical Battery Configuration ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА93

FIGURE 9-16 Typical Battery Current During Battery Backed Mode АААААААААААААААААААААААААААААААААААААААААААААААА93

FIGURE 10-1 Clock Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА99

FIGURE 10-2 Microprocessor Read Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА101

FIGURE 10-3 Microprocessor Write Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА101

FIGURE 10-4 Read after Write Operation to All Registers and RAM TimingААААААААААААААААААААААААААААААААААААААААА101

FIGURE 10-5 Baud Out Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА102

FIGURE 10-6 Transmitter Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА102

FIGURE 10-7 Sample Clock Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА103

FIGURE 10-8 Receiver Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА103

FIGURE 10-9 FIFO Mode Receiver TimingААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА103

FIGURE 10-10 Timeout Receiver TimingАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА104

FIGURE 10-11 MODEM Control TimingААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА104

FIGURE 10-12a FDC DMA Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА105

FIGURE 10-12b ECP DMA Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА106

List of Figures (Continued)

FIGURE 10-13 Reset Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА107

FIGURE 10-14 Write Data Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА107

FIGURE 10-15 Read Data Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА108

FIGURE 10-16 Drive Control Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА108

FIGURE 10-17 IDE Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА108

FIGURE 10-18 Compatible Mode Parallel Port Interrupt Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААА109

FIGURE 10-19 Extended Mode Parallel Port Interrupt Timing ААААААААААААААААААААААААААААААААААААААААААААААААААААААА109

FIGURE 10-20 Typical Parallel Port Data Exchange ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА109

FIGURE 10-21 Enhanced Parallel Port Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА110

FIGURE 10-22 ECP Parallel Port Forward Timing Diagram ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА111

FIGURE 10-23 ECP Parallel Port Backward Timing Diagram АААААААААААААААААААААААААААААААААААААААААААААААААААААААА111

FIGURE 10-24 IRQ

Release Delay АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА112

FIGURE 10-25 PWRGOOD VCCTimingАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА112

FIGURE 10-26 PWRGOOD MR Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА112

FIGURE 10-27 Chip Select Timing АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА113

List of Tables

TABLE 1-1 Pin Descriptions (Alphabetical) АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА10

TABLE 2-1 Default Configurations Controlled by Hardware АААААААААААААААААААААААААААААААААААААААААААААААААААААААА19

TABLE 2-2 Index and Data Register Optional Locations ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА19

TABLE 2-3 Encoded Drive and Motor Pin Information ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА21

TABLE 2-4 Primary and Secondary Drive Address Selection ААААААААААААААААААААААААААААААААААААААААААААААААААААААА22

TABLE 2-5 Parallel Port AddressesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА22

TABLE 2-6 COM Port Selection for UART1 АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА22

TABLE 2-7 COM Port Selection for UART2 АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА22

TABLE 2-8 Address Selection for COM3 and COM4 АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА22

TABLE 2-9 Logical Drive Exchange АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА23

TABLE 2-10 Parallel Port Mode ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА23

TABLE 3-1 Register Description and AddressesАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА28

TABLE 3-2 Drive Enable Values ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА29

TABLE 3-3 TDR Operation Modes ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА30

TABLE 3-4 Media ID Bit Functions ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА30

TABLE 3-5 Tape Drive Assignment Values АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА30

TABLE 3-6 Write Precompensation Delays АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА31

TABLE 3-7 Default Precompensation Delays АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА32

TABLE 3-8 Data Rate Select Encoding ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА32

TABLE 4-1 Typical Format GAP3 Length Values Based on Drive Data RateАААААААААААААААААААААААААААААААААААААААААА36

TABLE 4-2 Typical Format GAP3 Length Values Based on PC Compatible Diskette MediaААААААААААААААААААААААААААААА36

TABLE 4-3 DENSEL Default EncodingАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА39

TABLE 4-4 DENSEL EncodingААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА39

TABLE 4-5 Head Settle Time CalculationАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА39

TABLE 4-6 Effect of Drive Mode and Data Rate on Format and Write CommandsААААААААААААААААААААААААААААААААААААА40

TABLE 4-7 Effect of GAP and WG on Format and Write Commands АААААААААААААААААААААААААААААААААААААААААААААААА40

TABLE 4-8 Sector Size Selection АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА41

TABLE 4-9 SK Effect on the Read Data Command ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА42

TABLE 4-10 Result Phase Termination Values with No Error АААААААААААААААААААААААААААААААААААААААААААААААААААААААА42

TABLE 4-11 SK Effect on Read Deleted Data Command ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА43

TABLE 4-12 Maximum Recalibrate Step Pulses Based on R255 and ETRААААААААААААААААААААААААААААААААААААААААААААА44

TABLE 4-13 Scan Command Termination Values ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА45

TABLE 4-14 Status Register 0 Termination Codes ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА47

TABLE 4-15 Set Track Register Address ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА47

TABLE 4-16 Step Rate Time (SRT) Values ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА47

List of Tables (Continued)

TABLE 4-17 Motor Off Time (MFT) ValuesАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА48

TABLE 4-18 Motor On Time (MNT) Values ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА48

TABLE 4-19 Verify Command Result Phase АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА49

TABLE 6-1 PC87303 UART Register Addresses (AEN

0) ААААААААААААААААААААААААААААААААААААААААААААААААААААААА65

TABLE 6-2 PC87303 Register Summary for an Individual UART Channel АААААААААААААААААААААААААААААААААААААААААААА67

TABLE 6-3 PC87303 UART Reset Configuration ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА68

TABLE 6-4 PC87303 UART Divisors, Baud Rates, and Clock Frequencies ААААААААААААААААААААААААААААААААААААААААААА68

TABLE 6-5 PC87303 Interrupt Control Functions ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА71

TABLE 7-1 Parallel Interface Register Addresses АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА72

TABLE 7-2 Standard Parallel Port Modes SelectionААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА72

TABLE 7-3 SPP Data Register Read and Write Modes АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА72

TABLE 7-4 Parallel Port Reset StatesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА74

TABLE 7-5 EPP RegistersААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА75

TABLE 7-6 Parallel Port Pin OutАААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА78

TABLE 7-7 ECP Registers АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА79

TABLE 8-1 IDE Registers and Their ISA AddressesААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА83

TABLE 9-1 Summary of System Interface Operations ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА86

TABLE 9-2 RTC Memory Map ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА91

TABLE 10-1 Nominal t

ICP,tDRP

Values АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА99

TABLE 10-2 Minimum t

WDW

Values АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА107

Basic Configuration

TL/C/12074– 2

Connection Diagram

Plastic Quad Flatpak

TL/C/12074– 3

Note: Do not connect pins marked Reserved.

Order Number PC87303VUL

See NS Package Number VUL160A

1.0 Pin Description

TABLE 1-1. Pin Descriptions (Alphabetical)

Symbol Pin I/O Function

A10–A0 46–56 I Address. These address lines from the microprocessor determine which internal register is

accessed. A0–A10 are don’t cares during an DMA transfer. A10 is used only during ECP operations.

ACK 125 I Acknowledge. This input is pulsed low by a connected printer to indicate that it has received

data from the parallel port. This pin has a nominal 25 kX pull-up resistor attached to it. (See DR1

and Table 7-5 for further information.)

ADRATE0 16 O Additional Data Rate 0. When selected this output is identical to DRATE0. It is provided in

addition to DRATE0. It reflects the currently selected FDC data rate (bit 0 in the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last). ADRATE0 is configured when bit 0 of Advanced SuperI/O Configuration Register (ASC) is 1. (See IRQ5 for further information.)

AFD 116 I/O Automatic Feed XT. When this signal is low the printer should automatically line feed after

each line is printed. This pin is in a TRI-STATE

condition 10 ns aftera0isloaded into the corresponding Control Register bit. The system should pull this pin high using a 4.7 kX resistor. (See DSTRB

and Table 7-5 for further information.)

AEN 45 I Address Enable. This input disables function selection via A10 – A0 when it is high. Access

during DMA transfer is NOT affected by this pin.

ASTRB 119 O Address Strobe. This signal is used in Enhanced Parallel Port (EPP) mode as an address

strobe. It is active low. (See SLIN

and Table 7-5 for further information.)

BADDR0,1 86, 89 I Base Address. These CMOS inputs are sensed during reset to determine one of four base

addresses from which the Index and Data Registers are offset (see Table 2-2). An internal pull-down resistor of 30 kX is present on this pin. Use a 10 kX resistor to pull this pin to V

(See IDELO

, HCS0 for further information.)

BOUT1,2 110,100 O BAUD Output. This multi-function pin provides the associated serial channel Baud Rate

generator output signal when test mode is selected in the Power and Test Configuration Register and the DLAB bit (LCR7) is set. After a Master Reset, this pin provides the Serial Output (SOUT) function. (See SOUT and CFG0–4 for further information.)

BUSY 124 I Busy. This pin is set high by a connected printer when it cannot accept another character. It

has a nominal 25 kX pull-down resistor attached to it. (See WAIT and Table 7-5 for further information.)

CFG0–4 100, 103, I Configuration on Power-Up. These CMOS inputs select 1 of 32 default configurations in

which the PC87303 powers-up (see Table 2-1). They are provided with CMOS input buffers.

108, 110,

An internal pull-down resistor of 30 kX is present on each pin. Use a 10 kX resistor to pull

111

these pins to V

CS 2IChip Select. Enables the host to access the keyboard controller through D0 – D7, when bit 7

of Chip Select 0 Configuration Register 1 (CS0CF1) is 0. (See CS0 for further information.)

CSOUT 21 O Chip Select Read Output. This is the data buffer output enable pin. It indicates any read from

the PC87303, except for IDE accesses. This signal is valid when bit 2 of PTR is 1. CSOUT

not active during read in PC-AT mode from registers 3F7 and 377. CSOUT

is not active when

the read is from a disabled module. (See PWDN for further information.)

CTS1,2 109, 99 I Clear to Send. When low, this indicates that the MODEM or data set is ready to exchange

data. The CTS

signal is a MODEM status input whose condition the CPU can test by reading bit 4 (CTS) of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 4 is the complement of the CTS signal. Bit 0 (DCTS) of the MSR indicates whether the CTS input has changed state since the previous reading of the MSR. CTS

has no effect on the

transmitter.

Note: Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled.

CS0,1 2, 23 O Programmable Chip Select. CS0,1 are programmable chip select and/or enable and/or

output enable signals that can be used for a game port, I/O port expander or other add-on peripheral. The decoded address and the assertion conditions are configured via the PC87303 configuration registers, 0Ah–0Dh. When either of these two pins is acting as CS0,1 output enable, the PC87303 assumes the relevant input is 1. (See SYSCLK and CS for further information.)

D7–D0 33, 34, 35, 36, I/O Data. Bi-directional data lines to the microprocessor. D0 is the LSB and D7 is the MSB. These

signals all have 24 mA (sink) buffered outputs.

37, 38, 39, 42

1.0 Pin Description (Continued)

TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)

Symbol Pin I/O Function

DCD1,2 114, 106 I Data Carrier Detect. When low, this signal indicates that the MODEM or data set has detected the

data carrier. The DCD

signal is a MODEM status input whose condition the CPU can test by reading bit 7 (DCD) of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 7 is the complement of the DCD

signal. Bit 3 (DDCD) of the MSR indicates whether the DCD input has

changed state since the previous reading of the MSR.

Note: Whenever the DDCD bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

DENSEL 77 O Density Select. Indicates that a high FDC density data rate (500 kbps or 1 Mbps) or a low density

data rate (250 kbps or 300 kbps) is selected. DENSEL is active high for high density (5.25

drives)

when IDENT is high, and active low for high density (3.5

drives) when IDENT is low. DENSEL is

also programmable via the Mode command (see Section 4.2.6).

DIR 69 O Direction. This output determines the direction of the floppy disk drive (FDD) head movement

(active

step in, inactiveestep out) during a seek operation. During reads or writes, DIR is

inactive.

DR0,1 73, 74 O Drive Select 0,1. These are the decoded Drive Select outputs that are controlled by the Digital

Output Register bits D0,D1. The Drive Select outputs are gated with DOR bits 4–7. These are active low outputs. They are encoded with information to control four FDDs when bit 4 of the Function Enable Register (FER) is set. (See MTR0,1

for more information.)

DR23 78 O Drive 2 or 3. DR23 is asserted when either Drive 2 or Drive 3 is accessed (except during logical

drive exchange, see bit 3 of TDR). This pin is configured when bit 1 of ASC is 1. (See DRV2

for

further information.)

DRATE0,1 83, 82 O Data Rate 0,1. These outputs reflect the currently selected FDC data rate (bits 0 and 1 in the

Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last). These pins are totem-pole buffered outputs (6 mA sink, 6 mA source). (See MSEN0,1 for further information.)

DRID0,1 90, 87 I Drive ID. These pins accept input from the floppy disk drive which indicates the type of drive in use.

These pins should be tied low if they are not used. DRID0,1 is configured when bit 2 of ASC is 1. (See IOCS16

, IDEHI, and VLD0 for further information.)

DRV2 78 I Drive2. This input indicates whether a second floppy disk drive has been installed. The state of this

pin is available from Status Register A in PS/2 mode. This pin is confgured when bit 1 of ASC is 0. (See DR23

for further information.)

DSKCHG 60 I Disk Change. This input indicates if the drive door has been opened. The state of this pin is

available from the Digital Input register. This pin can also be configured as the Read Gate (RGATE) data separator diagnostic input via the Mode command (see Section 4.2.6).

DSR1,2 113, 105 I Data Set Ready. When low, this signal indicates that the data set or MODEM is ready to establish a

communications link. The DSR

signal is a MODEM status input whose condition the CPU can test by reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel. Bit 5 is the complement of the DSR

signal. Bit 1 (DDSR) of the MSR indicates whether the DSR input has

changed state since the previous reading of the MSR.

Note: Whenever the DDSR bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

DSTRB 116 O Data Strobe. This signal is used in EPP mode as a data strobe. It is active low. (See AFD and

Table 7-5 for further information.)

DTR1,2 108, 98 O Data Terminal Ready. When low, this output indicates to the MODEM or data set that the UART is

ready to establish a communications link. The DTR signal can be set to an active low by programming bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal to its inactive state. (See CFG0–4 for further information.)

ERR 117 I Error. A connected printer sets this input low when it has detected an error. This pin has a nominal

25 kX pull-up resistor attached to it.

FDACK 28 I DMA Acknowledge. Active low input to acknowledge the FDC DMA request and enable the RD

and WR inputs during a DMA transfer. When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of the Digital Output Register (DOR). When in PS/2 mode, FDACK

is always enabled, and bit

D3 of the DOR is reserved. FDACK

should be held high during I/O accesses.

1.0 Pin Description (Continued)

TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)

Symbol Pin I/O Function

FDRQ 27 O DMA Request. Active high output to signal the DMA controller that a FDC data transfer is needed.

When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode, FDRQ is always enabled, and bit D3 of the DOR is reserved.

HCS0 89 O Hard Drive Chip Select 0. This output is active in the PC-AT mode when 1) the hard drive registers

from 1F0–1F7h are selected and the primary address is used or 2) when the hard drive registers from 170–177h are selected and the secondary address is used. This output is inactive if the IDE interface is disabled via the Configuration Register. (See BADDR1 for further information.)

HCS1 88 O Hard Drive Chip Select 1. This output is active in the PC-AT mode when 1) the hard drive registers

from 3F6–7 are selected and the primary address is used or 2) the hard drive registers from 376 – 377 are selected and the secondary address is used. This output is also inactive, if the IDE interface is disabled via the Configuration Register.

HDSEL 62 O Head Select. This output determines which side of the FDD is accessed. When Active, the head

selects side 1. When inactive, the head selects side 0.

IDEACK 85 I IDE DMA Acknowledge. This is the IDE DMA acknowledge input pin when bit 1 of FCR is 1. In this

case the DENSEL polarity is active high (IDENT assumed 1). This pin is the IDENT input pin when bit 1 of FCR is 0. (See IDENT pin for further information.)

IDED7 91 I/O IDE Bit 7. This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the

address range 1F0–1F7h, 170 – 177h, 3F6h and 376h. This pin is TRI-STATE during read or write accesses to 3F7h and 377h.

IDEHI 87 O IDE High Byte. This output enables the high byte data latch during a read or write to the hard drive if

the hard drive returns IOCS16. This output is inactive if the IDE interface is disabled via the Configuration Register. (See VLD0

and DRID1 for further information.)

IDELO 86 O IDE Low Byte. This output enables the low byte data latch during a read or write to the hard drive. This

output is inactive if the IDE interface is disabled via the Configuration Register. (See BADDR0 for further information.)

IDENT 85 I Identity. After chip reset, the state of IDENT determines the polarity of the DENSEL output. When

IDENT is a logic ‘‘1’’, DENSEL is active high for the 500 kbps and 1 Mbps data rates. When IDENT is a logic ‘‘0’’, DENSEL is active low for the 500 kbps and 1 Mbps data rates. (See Mode command for explanation of DENSEL.) (See IDEACK

for further information.)

INDEX 76 I Index. This input signals the beginning of a FDD track.

INIT 118 I/O Initialize. When this signal is low it causes a connected printer to be initialized. This pin is in a TRI-

STATE condition 10 ns aftera1isloaded into the corresponding Control Register bit. The system should pull this pin high using a 4.7 kX resistor.

IOCHRDY 22 O I/O Channel Ready. This is the I/O Channel Ready open drain output. When IOCHRDY is driven low,

the EPP extends the host cycle.

IOCS16 90 I I/O Chip Select 16-Bit. This input is driven by a connected peripheral device which can accommodate

a 16-bit access. This pin is configured when bit 2 of ASC is 0. (See DRID0 for further information.)

IRQ3,4 19, 18 O Interrupt 3 and 4. These are active high interrupts associated with the serial ports. IRQ3 presents the

signal if the serial channel has been designated as COM2 or COM4. IRQ4 presents the signal if the serial port is designated as COM1 or COM3. The appropriate interrupt goes active whenever it is enabled via the Interrupt Enable Register (IER), the associated Interrupt Enable bit (Modem Control Register bit 3, MCR3), and any of the following conditions are active: Receiver Error, Receive Data available, Transmitter Holding Register Empty, or a Modem Status Flag is set. The interrupt signal is reset low (inactive) after the appropriate interrupt service routine is executed, after being disabled via the IER, or after a Master Reset. Either interrupt can be disabled, putting them into TRI-STATE, by setting the MCR3 bit low.

1.0 Pin Description (Continued)

TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)

Symbol Pin I/O Function

IRQ5 16 I/O Interrupt 5. Active high output that indicates a parallel port interrupt. When enabled this bit follows

the ACK

signal input. When bit 4 in the parallel port Control Register is set and the parallel port address is designated as shown in Table 2-5, this interrupt is enabled. When it is not enabled this signal is TRI-STATE.

This pin is I/O only when ECP is enabled, IRQ5 is configured, and bit 6 of PCR is 1. (See ADRATE0 for further information.)

IRQ6 15 O Interrupt 6. Active high output to signal the completion of the execution phase for certain FDC

commands. Also used to signal when a data transfer is ready during a Non-DMA operation. When in PC-AT or Model 30 mode, this signal is enabled by bit D3 of the DOR. When in PS/2 mode, IRQ6 is always enabled, and bit D3 of the DOR is reserved.

IRQ7 14 I/O Interrupt 7. Active high output that indicates a parallel port interrupt. When enabled this bit follows

the ACK

This pin is I/O only when ECP is enabled, IRQ7 is configured, and bit 6 of PCR is 1. For ECP operation, refer to the interrupt ECP Section 7.11.1

IRQ8 13 O Interrupt 8. Real-Time Clock interrupt request output. This is an open-drain output.

KBCLK 96 O Keyboard Clock output.

KBDAT 95 O Keyboard Data output.

MCLK 93 O Mouse Clock output.

MDAT 94 O Mouse Data output.

MR 20 I Master Reset. Active high input that resets the controller to the idle state, and resets all disk

interface outputs to their inactive states. The DOR, DSR, CCR, Mode command, Configure command, and Lock command parameters are cleared to their default values. The Specify command parameters are not affected. The Configuration Registers are set to their selected default values.

MTR0,1 75, 72 O Motor Select 0,1. These are the motor enable lines for drives 0 and 1, and are controlled by bits

D7–D4 of the Digital Output register. They are active low outputs. They are encoded with information to control four FDDs when bit 4 of the Function Enable Register (FER) is set. MTR0 exchanges logical motor values with MTR1 when bit 4 of FCR is set. (See DR0,1.)

MSEN0,1 83, 82 I Media Sense. These pins are Media Sense input pins when bit 0 of FCR is 0. Each pin has a 40 kX

internal pull-up resistor. When bit 0 of FCR is 1, these pins are Data Rate output pins, and the pullup resistors are disabled. (See DRATE0,1 for further information.)

P10–P17 141–148 I/O I/O Port. Quasi-bidirectional port for general purpose input and output.

P20–P27 151–158 I/O I/O Port. Quasi-bidirectional port for general purpose input and output.

PD0–7 134 – 131, I/O Parallel Port Data. These bidirectional pins transfer data to and from the peripheral data bus and

the parallel port Data Register. These pins have high current drive capability. (See DC Electrical

129–126

Characteristics.)

PDACK 26 I Printer DMA Acknowledge. Active low input to acknowledge a connected printer’s DMA request,

and enable the RD

and WR inputs during a DMA transfer. This input is valid only in Enhanced

Capabilities Port (ECP) mode.

PDRQ 25 O Printer DMA Request. Active high output which signals the DMA controller that a printer data

transfer is required. This pin is in TRI-STATE when ECP is disabled (PCR2

0) or when it is

configured without DMA (PMC3

0). This output is valid only in ECP mode.

1.0 Pin Description (Continued)

TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)

Symbol Pin I/O Function

PDWN 21 I Power-Down. This multi-function pin stops the clocks and/or the external crystal based on the

selections made in the Power and Test Register (PTR) bits 1 and 2. (See CSOUT

for additional

information.)

PE 123 I Paper End. This input is set high by a connected printer which is out of paper. This pin has a

nominal 25 kX pull-down resistor attached to it.

PWRGOOD 12 I Power Supply Good. An input to the PC87303 indicating that the power supply is good. This input

should be held low until the power supply is stable.

RD 44 I Read. Active low input to signal a data read by the microprocessor.

RDATA 63 I Read Data. This input is the raw serial data read from the floppy disk drive.

RI1,2 107, 97 I Ring Indicator. When low this indicates that a telephone ring signal has been received by the

MODEM. The RI signal is a MODEM status input whose condition the CPU can test by reading bit 6 (RI) of the MODEM Status Register (MSR) for the appropriate serial channel. Bit 6 is the complement of the RI signal. Bit 2 (TERI) of the MSR indicates whether the RI input has changed from low to high since the previous reading of the MSR.

Note: When the TERI bit of the MSR is set, an interrupt is generated if MODEM Status interrupts are enabled.

RTS1,2 111, 103 O Request to Send. When low, this output indicates to the MODEM or data set that the UART is

ready to exchange data. The RTS

signal can be set to an active low by programming bit 1 (RTS) of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal to its inactive state. (See CFG0–4 for further information.)

SIN1,2 112, 104 I Serial Input. This input receives composite serial data from the communications link (e.g.

peripheral device, MODEM, or data set).

SLCT 122 I Select. When a printer is connected, it sets this input high. This pin has a nominal 25 kX pull-down

resistor attached to it.

SLIN 119 O Select Input. When this signal is low it selects the printer. This pin is a TRI-STATE condition 10 ns

aftera0isloaded into the corresponding Control Register bit. The system should pull this pin high using a 4.7 kX resistor.

SOUT1,2 110, 100 O Serial Output. This output sends composite serial data to the communications link (peripheral

device, MODEM, or data set). The SOUT signal is set to a marking state (logic 1) after a Master Reset operation. (See BOUT and CFG0–4 for further information.)

STB 135 I/O Data Strobe. This output indicates to the printer that valid data is available at the printer port. This

pin is in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding Control Register bit. The system should pull this pin high using a 4.7 kX resistor. (See WRITE

for further

information.)

STEP 68 O Step. This output signal issues pulses to the disk drive at a software programmable rate to move

the head during a seek operation.

SYNC 5 I/O Synch. 32 kHz Real-Time Clock output signal when bit 4 of KRR is 1. SYNC is an input when MR

is high and is sampled by the falling edge of MR. It is a TTL strap input buffer. It is sampled to bit 2 of PTR. A 40 kX internal pullup resistor is present on this pin.

SYSCLK 23 I System Clock. This input is the system clock when bit 7 of CS1CF0 is 0. (See CS1 for further

information.)

T0 4 I Test 0. This input can be directly tested by the conditional jump instructions JT0 and JNT0 of the

Keyboard Controller.

T1 3 I Test 1. This input can be directly tested by the conditional jump instructions JT1 and JNT1 of the

Keyboard Controller. T1 can also be used as the external input to the 8-bit counter/timer of the Keyboard Controller.

TC 29 I Terminal Count. Control signal from the DMA controller to indicate the termination of a DMA

transfer. TC is accepted only when FDACK

or PDACK is active. TC is active high in PC-AT and

Model 30 modes, and active low in PS/2 mode.

1.0 Pin Description (Continued)

TABLE 1-1. Pin Descriptions (Alphabetical) (Continued)

Symbol Pin I/O Function

TRK0 65 I Track 0. This input indicates to the controller that the head of the selected floppy disk drive is at

track zero.

VBAT 8 Battery. Real-Time Clock battery pin.

VDD 1, 17, Digital Supply. This is the 5V supply voltage for the digital circuitry.

41, 57,

79, 101,

121, 140,

150

VDDA 61 Analog Supply. This pin is the 5V supply for the analog data separator.

VLD0,1 87, 98 I Valid Data. These inputs are sensed during reset, and determine the state of bit 5 in the FDC Tape

Drive Register (3F3h). Thus, they determine whether bits 6 and 7 of this register contain valid media id information for floppy drives 0 and 1. If VLD0

is sensed low at reset, then whenever drive 0 is accessed, bit 5 of the Tape Drive Register is a 0 indicating that bits 6 and 7 contain valid media id information. If VLD0

is sensed high at reset, then whenever drive 0 is accessed, bit 5 of the Tape Drive Register is a 1 indicating that bits 6 and 7 do not contain valid media id information. The same is true of VLD1

relative to the media id information for drive 1.

If bit 0 of FCR is 1, the VLD

bits have no meaning. VLD0 value during reset is loaded into bit 0 of FCR (to select between media sense or DRATE). A 30 kX internal pulldown resistor is present on each pin. Use a 10 kX resistor to pull these pins high during reset. These strap option pins are CMOS input buffers. (See IDEHI

, DRID1 and DTR2 for further information.)

VSSA 59 Analog Ground. This is the analog ground for the data separator.

VSS 7, 11, Digital Ground. This is the ground for the digital circuitry.

32, 40, 58, 70, 71, 80,

81, 92, 102, 115, 120, 130, 136, 139,

149, 160

WAIT 124 I Wait. This signal is used, in EPP mode, by the parallel port device to extend its access cycle. It is

active low. (See BUSY and Table 7-5 for further information.)

WR 43 I Write. Active low input to signal to indicate a write from the microprocessor to the controller.

WDATA 67 O Write Data. This output is the write precompensated serial data that is written to the selected floppy

disk drive. Precompensation is software selectable.

WGATE 66 O Write Gate. This output signal enables the write circuitry of the selected disk drive. WGATE has been

designed to prevent glitches during power up and power-down. This prevents writing to the disk when power is cycled.

WP 64 I Write Protect. This input indicates that the floppy disk in the selected drive is write protected.

WRITE 135 O Write Strobe. This signal is used in EPP mode as a write strobe. It is active low. (See STB and Table

7-5 for further information.)

X1/OSC 30 I Crystal1/Clock. One side of an external 24 MHz crystal is attached here. The other side is

connected to X2. If a crystal is not used, a TTL or CMOS compatible clock is connected to this pin.

X1C 9 I Crystal1 Slow. Input for the internal Real-Time Clock crystal oscillator amplifier.

X2C 10 O Crystal2 Slow. Output for the internal Real-Time Clock crystal oscillator amplifier.

X2 31 O Crystal2. One side of an external 24 MHz crystal is attached here. The other side is connected to

X1/OSC. This pin is left unconnected if an external clock is used.

ZWS 24 O Zero Wait State. This pin is the Zero Wait State open drain output pin. ZWS is driven low when the

EPP, or the ECP, is written, and the access can be shortened.

2.0 Configuration Registers

2.1 OVERVIEW

Fourteen registers constitute the Base Configuration Register set, and control the PC87303 setup. In general, these registers control the enabling of major functions (FDC, UARTs, parallel port, pin functionalty etc.), the I/O addresses of these functions, and whether they power-down via hardware control or not. These registers are the Function Enable Register (FER), the Function Address Register (FAR), the Power and Test Register (PTR), the Function Control Register (FCR), the Printer Control Register (PCR), the Keyboard and Real-Time Clock Control Register (KRR), the Power Management Control Register (PMC), the Tape, UARTs and Parallel Port Register (TUP), the SuperI/O Identification Register (SID), the Advanced SIO Configuration Register (ASC), the Chip Select 0 Configuraton Register 0 (CS0CF0), the Chip Select 0 Configuration Register 1 (CS0CF1), the Chip Select 1 Configuration Register 0 (CS1CF0) and the Chip Select 1 Configuration Register 1 (CS1CF1).

The FER, FAR, and PTR can be accessed via hardware or software. During reset, the PC87303 loads a set of default values, selected by a hardware strapping option, into these three Configuration Registers. FCR, PCR and KRR can only be accessed by software.

An index and data register pair are used to read and write these registers. Each Configuration Register is pointed to by the value loaded into the Index Register. The data to be written into the Configuration Register is transferred via the Data register. A Configuration Register is read in a similar way (i.e., by pointing to it via the Index Register and then reading its contents via the Data Register).

Accessing the Configuration Registers in this way requires only two system I/O addresses. Since that I/O space is shared by other devices the Index and Data Registers can still be inadvertantly accessed. To reduce the chances of an inadvertant access, a simple procedure (see Section 2.2) has been developed.

2.2 SOFTWARE CONFIGURATION

If the system requires access to the Configuration Registers after reset, the following procedure must be used to change data in the registers.

1. Determine the PC87303 Index Register’s default location.

Check the four possible locations (see Table 2-1) by reading them twice. The first byte is the ID byte 88h. The second byte read is always 00h, but read after write always brings the value of the written byte. Compare the data read with the ID byte and then 00h. A match occurs at the correct location. Note that the ID byte is only issued from the Index Register during the first read after a reset. Subsequent reads return the value loaded into the Index Register. Bits 5 – 6 are reserved and always read 0.

2. Load the Configuration Registers.

A. Disable CPU interrupts.

B. Write the index of the Configuration Register (00h –

0Dh) to the Index Register one time.

C. Write the correct data for the Configuration Register in

two consecutive write accesses to the Data Register.

D. Enable CPU interrupts.

3. Load the Configuration Registers (read-modify-write).

A. Disable CPU interrupts.

B. Write the index of the Configuration Register (00h –

0Dh) to the Index Register one time.

C. Read the configuration data in that register via the

Data Register.

D. Modify the configuration data.

E. Write the changed data for the Configuration Register

in two consecutive writes to the Data Register. The register updates on the second consecutive write.

F. Enable CPU interrupts.

A single read access to the Index and Data Registers can be done at any time without disabling CPU interrupts. When the Index Register is read, the last value loaded into the Index Register is returned. When the Data Register is read, the Configuration Register data pointed to by the Index Register is returned.

2.0 Configuration Registers (Continued)

TL/C/12074– 4

TL/C/12074– 6

TL/C/12074– 8

TL/C/12074– 10

TL/C/12074– 12

TL/C/12074– 5

TL/C/12074– 7

TL/C/12074– 9

TL/C/12074– 11

TL/C/12074– 13

FIGURE 2-1. PC87303 Configuration Registers

2.0 Configuration Registers (Continued)

TL/C/12074– 14

TL/C/12074– 15

TL/C/12074– 16

TL/C/12074– 17

FIGURE 2-1. PC87303 Configuration Registers (Continued)

2.0 Configuration Registers (Continued)

2.3 HARDWARE CONFIGURATION

During reset, 1 of 32 possible sets of default values are loaded into the first three Configuration Registers. A strapping option on five pins (CFG0– 4) selects the set of values that is loaded. This allows for automatic configuration without software intervention. Table 2-1 shows the 32 possible default configurations. The default configuration can be modified by software at any time after reset by using the access procedure described in the Software Configuration Section.

Table 2-1 is organized as follows. The logic values of the five external Configuration Pins are associated with the resulting Configuration Register Data and the activated functions. The activated functions are grouped into seven categories based on the data in the FER. In some cases the data in the FER is given as one of two options. This is because the primary or secondary IDE address is chosen via the FER.

The PTR has one value associated with the active functions in the FER. This value allows the power-down of all clocks when the PWDN

pin goes active. In the last case where no

functions are active after reset, activating the PWDN

also stops the crystal.

Most of the variability available is through the FAR. Addresses controlled by the FAR are coded as follows:

PRI is the PRImary floppy or IDE address (i.e., 3F0 – 7h

or 1F0 – 7, 3F6, 7h)

SEC is the SECondary IDE address (170 – 7, 376, 7h)

COM1 is the UART address at 3F8 – Fh

COM2 is the UART address at 2F8 – Fh

COM3 is the UART address at 3E8 – Fh

COM4 is the UART address at 2E8 – Fh

LPTA is the parallel port (

PORT ) address at 3BC – 3BEh

LPTB is the

PORT address at 378 –37Fh

The chosen addresses are given under active functions and are in the same order as the active functions they are associated with. In other words, if the active functions are given as FDC, IDE, UART1, UART2,

PORT and the addresses are given as PRI, PRI, COM1, COM2, LPTB; then the functions and the addresses are associated as follows: FDC

PRI, IDEePRI, UART1eCOM1, UART2eCOM2,

PORTeLPTB.

2.4 INDEX AND DATA REGISTERS

One more general aspect of the Configuration Registers is that the Index and the Data Register pair can be relocated to any one of two locations. This is controlled through a hardware strapping option on two pins (BADDR0,1) and it allows the registers to avoid conflicts with other adapters in the I/O address space. Table 2-2 shows the address options.

TABLE 2-2. Index and Data Register

Optional Locations

BADDR1 BADDR0 Index Addr. Data Addr.

0 0 398 399

0 1 26E 26F

1 0 15C 15D

1 1 2E 2F

TABLE 2-1. Default Configurations Controlled by Hardware

Configuration Pins (CFGn)

(Hex)

Data

Activated Functions

43210

FERe4F, CF FDC, IDE, UART1, UART2,llPORT

PTRe00 Power-Down Clocks Option

00000FAR

10 PRI, PRI, COM1, COM2, LPTB

00001FAR

11 PRI, PRI, COM1, COM2, LPTA

00010FAR

11 PRI, SEC, COM1, COM2, LPTA

00011FAR

39 PRI, PRI, COM3, COM4, LPTA

00100FAR

24 PRI, PRI, COM2, COM3, LPTB

00101FAR

38 PRI, SEC, COM3, COM4, LPTB

FERe4B, CB FDC, IDE, UART1,llPORT

PTRe00 Power-Down Clocks Option

00110FAR

00 PRI, PRI, COM1, LPTB

00111FAR

01 PRI, PRI, COM1, LPTA

01000FAR

01 PRI, SEC, COM1, LPTA

01001FAR

09 PRI, PRI, COM3, LPTA

01010FAR

08 PRI, PRI, COM3, LPTB

01011FAR

08 PRI, SEC, COM3, LPTB

2.0 Configuration Registers (Continued)

TABLE 2-1. Default Configurations Controlled by Hardware (Continued)

Configuration Pins (CFGn)

(Hex)

Data

Activated Functions

43210

FERe0F FDC, UART1, UART2,llPORT

PTRe00 Power Clocks Option

01100FAR

10 PRI, COM1, COM2, LPTB

01101FAR

11 PRI, COM1, COM2, LPTA

01110FAR

39 PRI, COM3, COM4, LPTA

01111FAR

24 PRI, COM2, COM3, LPTB

FERe49, C9 FDC, IDE,llPORT

PTRe00 Power-Down Clocks Option

10000FAR

00 PRI, PRI, LPTB

10001FAR

01 PRI, PRI, LPTA

10010FAR

01 PRI, SEC, LPTA

10011FAR

00 PRI, SEC, LPTB

FERe07 UART1, UART2,llPORT

PTRe00 Power-Down Clocks Option

10100FAR

10 COM1, COM2, LPTB

10101FAR

11 COM1, COM2, LPTA

10110FAR

39 COM3, COM4, LPTA

10111FAR

24 COM2, COM3, LPTB

FERe47, C7 IDE, UART1, UART2,llPORT

PTRe00 Power-Down Clocks Option

11000FAR

10 PRI, COM1, COM2, LPTB

11001FAR

11 PRI, COM1, COM2, LPTA

11010FAR

11 SEC, COM1, COM2, LPTA

11011FAR

39 PRI, COM3, COM4, LPTA

11100FAR

24 PRI, COM2, COM3, LPTB

11101FAR

38 SEC, COM3, COM4, LPTB

FERe08 FDC

PTRe00 Power-Down Clocks Option

11110FAR

10 PRI

FERe00 None

PTRe02, 02 Power-Down XTAL and Clocks

11111FAR

10 NA

Note: Bit 2 of PTR is sampled during reset according to the value of the SYNC pin.

2.0 Configuration Registers (Continued)

2.5 BASE CONFIGURATION REGISTERS

2.5.1 Function Enable Register (FER, Index 00h)

This register enables and disables major chip functions. Disabled functions have their clocks automatically powered down, but the data in their registers remains intact. It also selects whether the FDC and the IDE controller is located at their primary or secondary address.

Bit 0 When this bit is one the parallel port can be accessed

at the address specified in the FAR.

Bit 1 When this bit is one, UART1 can be accessed at the

address specified in the FAR. When this bit is zero, access to UART1 is blocked and it is in power-down mode. The UART1 registers retain all data in power down mode.

Caution: Any UART1 interrupt that is enabled and active or becomes active after UART1 is disabled asserts the associated IRQ pin when UART1 is disabled. If disabling UART1 via software, clear the IRQ Enable bit (MCR3) to zero before clearing FER 1. This is not an issue after reset because MCR3 is zero until it is written.

Bit 2 When this bit is one, UART2 can be accessed at the

address specified in the FAR. When this bit is zero, access to UART2 is blocked and it is in power-down mode. The UART2 registers retain all data in power down mode.

Caution: Any UART2 interrupt that is enabled and active or becomes active after UART2 is disabled asserts the associated IRQ pin when UART1 is disabled

If disabling UART2 via software, clear the IRQ Enable bit (MCR3) to zero before clearing FER1. This is not an issue after reset because MCR3 is zero until it is written.

Bit 3 When this bit is one, the FDC can be accessed at the

address specified in the FER bits. When this bit is zero access to the FDC is blocked and it is in powerdown mode. The FDC registers retain all data in power down mode.

Bit 4 When this bit is zero the PC87303 can control two

floppy disk drives directly without an external decoder. When this bit is one the two drive select signals and two motor enable signals from the FDC are encoded so that four floppy disk drives can be controlled (see Table 2-3 and

Figure 2-2

). Controlling four FDDs requires an external decoder. The pin states shown in Table 2-3 are a direct result of the bit patterns shown. All other bit patterns produce pin states that should not be decoded to enable any drive or motor.

Bit 5 This bit selects the primary or secondary FDC ad-

dress. (See Table 2-4.)

Bit 6 When this bit is a one the IDE drive interface can be

accessed at the address specified by FER bit 7. When it is zero, bit 0 of PMC determines whether the HCS0,1

pins are inactive, or in TRI-STATE. IDEHI and IDEHLO are inactive and IDED7 is in TRISTATE.

Bit 7 This bit selects the primary or secondary IDE ad-

dress. (See Table 2-4).

TABLE 2-3. Encoded Drive and Motor Pin Information (FER 4

Digital Output Register Drive Control Pins

Decoded Functions

7 6 5 4 3 2 1 0 MTR1 MTR0 DR1 DR0

XXX1X X 0 0 (Note) 0 0 0 Activate Drive 0 and Motor 0

XX1X X X 0 1 (Note) 0 0 1 Activate Drive 1 and Motor 1

X 1 X X X X 1 0 (Note) 0 1 0 Activate Drive 2 and Motor 2

1 X X X X X 1 1 (Note) 0 1 1 Activate Drive 3 and Motor 3

XXX0X X 0 0 (Note) 1 0 0 Activate Drive 0 and Deactivate Motor 0

XX0X X X 0 1 (Note) 1 0 1 Activate Drive 1 and Deactivate Motor 1

X 0 X X X X 1 0 (Note) 1 1 0 Activate Drive 2 and Deactivate Motor 2

0 X X X X X 1 1 (Note) 1 1 1 Activate Drive 3 and Deactivate Motor 3

Note: When FER4e1, MTR1 presents a pulse that is the inverted image of the IOW strobe. This inverted pulse is active whenever an I/O write to address 3F2h or

372h takes place. This pulse is delayed by 25 ns –80 ns after the leading edge of IOW and its leading edge can be used to clock data into an external latch (e.g., 74LS175). Address 3F2h is used if the FDC is located at the primary address (FER5

0) and address 372h is used if the FDC is located at the secondary address

(FER5

1).

TL/C/12074– 85

Hex Buffers I

40 mA

open collector

FIGURE 2-2. PC87303 Four Floppy Drive Circuit

2.0 Configuration Registers (Continued)

TABLE 2-4. Primary and Secondary

Drive Address Selection

Bit 5 Bit 7 Drive PC-AT Mode

0 X FDC Primary,

3F0–7h

1 X FDC Secondary,

3F0–7h

X 0 IDE Primary,

1F0–7, 3F6, 3F7h

X 1 IDE Secondary

170–7, 376, 7h

2.5.2 Function Address Register (FAR, Indexe01h)

This register selects the ISA I/O address range to which each peripheral function responds.

Bits 0,1 These bits select the parallel port address as

shown in Table 2-5:

TABLE 2-5. Parallel Port Addresses

ASC FAR FAR

Parallel

PC-AT

Bit 0 Bit 1 Bit 0

Port

Interrupt

Address

0 0 0 LPTB (378 – 37F) IRQ5 (Note)

X 0 1 LPTA (3BC– 3BE) IRQ7

0 1 0 LPTC (278 – 27F) IRQ5

X 1 1 Reserved TRI-STATE

(CTR4

1 0 0 LPTB (378 – 37F) IRQ7

1 1 0 LPTC (278 – 27F) IRQ7

Note: The interrupt assigned to this address can be changed to IRQ7 by setting Bit 3 of the power and test register.

Bits 2–5 These bits determine which ISA I/O address range

is associated with each UART (see Tables 2-6, 2-7).

TABLE 2-6. COM Port Selection for UART1

FAR UART1

Bit 3 Bit 2 COM

0 0 1 (3F8-F)

0 1 2 (2F8-F)

1 0 3 (Table 2-8)*

1 1 4 (Table 2-8)*

*Note: COM3 and COM4 addresses are determined by Bits 6 and 7.

TABLE 2-7. COM Port Selection for UART2

FAR UART2

Bit 5 Bit 4 COM

0 0 1 (3F8-F)

0 1 2 (2F8-F)

1 0 3 (Table 2-8)*

1 1 4 (Table 2-8)*

*Note: COM3 and COM4 addresses are determined by Bits 6 and 7.

Bits 6, 7 These bits select the addresses that are used for

COM3 and COM4 (see Table 2-8).

TABLE 2-8. Address Selection for COM3 and COM4

Bit 7 Bit 6 COM3 IRQ4 COM4 IRQ3

0 0 3E8–Fh 2E8–Fh

0 1 338–Fh 238–Fh

1 0 2E8–Fh 2E0–7h

1 1 220–7h 228–Fh

2.5.3 Power and Test Register (PTR, Indexe02h)

This register determines several power-down features: the power-down method used when the power-down pin (PWDN

) is asserted (crystal and clocks vs clocks only), whether hardware power-down is enabled, and provides a bit for software power-down of all enabled functions. It selects whether IRQ7 or IRQ5 is associated with LPTB. It puts the enabled UARTs into their test mode.

Independent of this register the floppy disk controller can enter low power mode via the Mode Command or the Data Rate Select Register.

Bit 0 Setting this bit causes all enabled functions to be

powered down. If the crystal power-down option is selected (see Bit 1) the crystal is also powered down. All register data is retained when the crystal or clocks are stopped.

Bit 1 When the power-down pin or Bit 0 is asserted this bit

determines whether the enabled functions have their internal clocks stopped (Bit 1

0) or the external

crystal (Bit 1

1) is stopped. Stopping the crystal is the lowest power consumption state of the part. However, if the crystal is stopped, a finite amount of time (E8 ms) is required for crystal stabilization once the power-down pin (PWDN

) or Bit 0 is deasserted. If all internal clocks are stopped, but the crystal continues to oscillate, no stabilization period is required after the power-down pin or Bit 0 is deasserted.

Bit 2 Setting this bit enables the chip select function of the

PWDN

/CSOUT pin. Resetting this bit enables the power-down function of this pin. Sync pin is sampled during reset to this bit.

2.0 Configuration Registers (Continued)

Bit 3 Setting this bit associates the parallel port with IRQ7

when the address for the parallel port is 378 –37Fh (LPTB). This bit is a ‘‘don’t care’’ when the parallel port address is 3BC–3BEh (LPTA) or 278 –27Fh (LPTC).

Bit 4 Setting this bit puts UART1 into a test mode, which

causes its Baud Out clock to be present on its SOUT1 pin if the Line Control Register bit 7 is set to 1.

Bit 5 Setting this bit puts UART2 into a test mode, which

causes its Baud Out clock to be present on its SOUT2 pin if the Line Control Register bit 7 is set to 1.

Bit 6 Setting this bit to a 1 prevents all further write access-

es to the Configuration Registers. Once it is set by software it can only be cleared by a hardware reset. After the initial hardware reset it is 0.

Bit 7 When not in EPP or ECP modes, this bit controls

Compatible/Extended mode, thus controlling Pulse/ Level interrupt.

Set this bit to 0 for Compatible mode, Pulse Interrupt. Set this bit to 1 for Extended mode, Level Interrupt.

Note: Parallel port interrupt (Pulse/Level) in EPP and ECP modes is

always pulse.

In EPP mode this bit selects Regular/Automatic bi-di-

rectional mode, thus selecting the direction control

method:

Set this bit to 0 for Automatic mode, Host RD and WR signals control the direction.

Set this bit to 1 for Regular mode, bit 5 of CTR controls the direction.

After hardware reset, this bit is 0.

2.5.4 Function Control Register (FCR, Index

03h)

This register determines several pin options: It selects between Data Rate output and automatic media sense inputs, and between IDENT or IDEACK

inputs for

DMA control of IDE.

For Enhanced Parallel Port it enables the ZWS

option.

On reset the FCR 2– 7 bits are cleared to 0.

Bit 0 Media Sense/Data Rate select bit. When this bit is

0, the MSEN0 – 1 pins are Media Sense inputs. When this bit is 1, the DRATE0-1 pins are Data Rate outputs. VLD0

pin is sampled during reset to this bit. When ths bit is 0, bits 5 –7 of TDR are valid. When this bit is 1, bits 2–7 of TDR are TRI-STATE during read. When bit 2 of ASC Register is 1, TDR is not controlled by this bit.

Bit 1 IDENT/IDEACK

select bit. When this bit is 0, the IDENT pin is used, and the IDE DMA is disabled. When this bit is 1, the IDE DMA is enabled, and the IDENT input is assumed to be 1.

Bit 2 Reserved.

Bit 3 Parallel Port Floating Control bit.

When this bit is 0, there is no software unconditional float control. This bit does not affect the parallel port pins. When this bit is 1, the parallel port outputs are in TRI-STATE, and their pull-ups are disconnected.

Bit 4 Logical Drive Exchange bit. This bit allows software

to exchange the physical floppy-disk control signals, assigned to drives 0 and 1, thus exchanging the logical drives A and B.

This is accomplished by exchanging control of the DR0

and MTR0 pins with the DR1 and MTR1 pins. The result is undefined if this bit is set while bit 4 of FER is 1. Table 2-9 shows the associations between the Configuration Register bit, the Digital Output Register bits (DRVSEL0,1 and MTR0,1) and the drive and motor control pins (DR0,1

and

MTR0,1

). When bit 2 of ASC Register is 1, the logical drive exchange function is controlled by bits 2 and 3 of TDR.

TABLE 2-9. Logical Drive Exchange

FCR Digital Output Register (FDC) Asserted

Bit 4 MTR1 MTR0 DRVSEL1 DRVSEL0

FDC Pins

00 1 0 0

DR0

MTR0

01 0 0 1

DR1

MTR1

10 1 0 0

DR1

MTR1

11 0 0 1

DR0

MTR0

Bit 5 Zero Wait State enable bit. If this bit is 1, ZWS is

driven low when the Enhanced Parallel Port (EPP), or the ECP, can accept a short host read/ write-cycle, otherwise the ZWS

open drain output

is not driven. EPP ZWS

operation should be configured when the system’s device is fast enough to support it.

Bits 6, 7 Reserved. Use Read Modified Write to change the

FCR register.

2.5.5 Printer Control Register (PCR, Index

04h)

This register enables the EPP and ECP version modes, and interrupt options. It also enables the RTC RAM write mask bit. On reset the PCR bits are cleared to 0.

The parallel port mode is software configurable as follows:

TABLE 2-10. Parallel Port Mode

Operation FER PTR PCR PCR

Mode Bit 0 Bit 7 Bit 0 Bit 2

None 0 X X X

Compatible 1000

Extended 1100

EPP 1 X 1 0

ECP 1 X 0 1

Bit 0 EPP enable bit. When this bit is 0, the EPP is dis-

abled, and the EPP registers are not accessible (access ignored).

When this bit is 1, and bit 2 of PCR is 0, the EPP is enabled. Note that the EPP should not be configured with base address 3BCh.

For further information refer to bit 5 of FCR.

2.0 Configuration Registers (Continued)

Bit 1 EPP version select bit. When this bit is 0, Version

1.7 is supported, and STB

, AFD, INIT, and SLIN

are open drain outputs.

When this bit is 1, Version 1.9 is supported (IEEE

1284), and STB

, AFD, INIT, and SLIN are push-pull outputs. This bit has the same affect on the output buffers in ECP modes 0 and 2.

Bit 2 ECP enabIe bit. When this bit is 0 the ECP is dis-

abled and in power-down mode. The ECP registers are not accessible (access ignored) and the ECP interrupt and DMA are inactive. When this bit is 1 the ECP is enabled. The software should change this bit to 1 only when bits 0, 1, and 2 of the existing CTR are 1, 0 and 0 respectively.

Bit 3 ECP clock freeze control bit. In power-down

modes 2 and 3: When this bit is 0, the clock provided to the ECP is stopped; and

When this bit is 1, the clock provided to the ECP is not stopped.

Bit 4 Reserved. This bit must be set to 0.

Bit 5 Parallel port interrupt (IRQ5 or IRQ7) polarity con-

trol bit. When this bit is 0 the interrupt polarity is level high or negative pulse. When this bit is 1 the interrupt polarity is inverted.

Bit 6 Parallel port interrupt (IRQ5 or IRQ7) open drain

control bit. When this bit is 0 the configured interrupt line (IRQ5 or IRQ7) has a totem-pole output. When this bit is 1 the configured interrupt line has an open drain output (drive low, no drive high, no internal pullup).

Bit 7 RTC RAM write mask bit. When this bit is 0, the

RTC RAM is writeable. When this bit is 1, the RTC RAM is not writeable, and writes are ignored.

2.5.6 KBC and RTC Control Register (KRR, Index

05h)

This register enables and disables the keyboard controller (KBC) and the Real-Time Clock (RTC). It selects the clock source and operating mode of the KBC, selects different banks of CMOS RAM in the RTC, and selects the RTC test mode. When PWRGOOD is low, KRR is initialized to

00000001.

Bit 0 KBC Enable bit. When this bit is zero the KBC

clock is frozen and the state of its dedicated pins cannot be altered. When this bit is one the KBC is functional.

Bit 1 KBC Speed control bit. Controls the KBC speed

when X1/OSC clock source is selected (KRR7 is

0). This bit is ignored when SYSCLK clock source is selected (KRR7 is 1).

When this bit is 0 the KBC clock is the X1/OSC frequency divided by three (typically 8 MHz). When this bit is 1 the KBC clock is the X1/OSC frequency divided by two (typically 12 MHz).

Bit 2 PAE

. Program Access Enable of the keyboard

controller. This bit should be set to 1.

Bit 3 RTC Enable bit. When this bit is 0 the RTC is dis-

abled and IRQ8

is in TRI-STATE. When this bit is 1

the RTC is enabled.

Bit 4 CLKTEST. RTC clock test mode select. When this

bit is 1 the SYNC pin outputs the 32 kHz RTC clock. When this bit is 0 the SYNC pin is not driven. When PWRGOOD is low, this bit is initialized to

Bit 5 RAMSREL. RTC CMOS RAM bank select. When

this bit is 1 it selects the upper 128 bytes of CMOS RAM. When this bit is 0 it selects the lower 128 bytes of CMOS RAM.

Bit 6 On-chip KBC Address Decoder Enable bit. When

this bit is 0 (and KRR0 is 1) the KBC is accessed when CS

is low, and the address pin A2 selects

the KBC registers. When this bit is 1 (and KRR0 is

1) the CS

input is ignored, and the address pins

A0–9 select the KBC registers (60h or 64h).

Bit 7 KBC clock source select bit. When this bit is 0 the

KBC uses the X1/OSC clock source. When this bit is 1 the KBC uses the SYSCLK clock source. This bit enables the KBC to operate in power-down mode, even when the X1 clock is frozen. It may be modified only when the KBC is disabled via bit 0 of KRR.

2.5.7 Power Management Control Register (PMC, Index

06h)

This register controls the TRI-STATE and input pins. The PMC register is accessed through Index 06h. The PMC Register is cleared to 0 on reset.

Bit 0 IDE TRI-STATE Control bit

0: When this bit is 0, it does not affect the IDE

pins.

1: IDE7 and HCS0,1

are in TRI-STATE, IDEHI and

IDELO

are inactive when either the IDE is dis-

abled or the chip is in power-down mode.

Bit 1 FDC TRI-STATE Control bit.

0: When this bit is 0, it does not affect the FDC

pins.

1: The FDC outputs, except IRQ6, are in

TRI-STATE when either the FDC is disabled or the chip is in power down mode.

Bit 2 UART TRI-STATE Control bit.

0: When this bit is 0, it does not affect the UART’s

pins.

1: The outputs of any UART, except IRQ4 and

IRQ3, are in TRI-STATE when that UART is disabled or the chip is in power-down.

2.0 Configuration Registers (Continued)

Bits 3, 4 Reserved.

Bit 5 Selective Lock bit. Unlike bit 6 of PTR, which

locks all configuration bits, this bit only enables locking of the following:

Bit 5 of PMC, bit 4 of FER, bits 0– 7 of FAR, bits 2, 3 of PTR, bit 1 of FCR, and bit 5 of KRR. Once this bit has been set by software, it can only be cleared by a hardware reset. It should be used instead of bit 6 of PTR if a configration bit should be dynamically modified by software (e.g., PMC bits).

0: No lock, except via bit 6 of PTR.

1: Any write to the above configuration bits is ig-

nored (until a hardware reset, which clears this bit).

Bit 6 Parallel Port TRI-STATE Control bit.

0: When this bit is 0, it does not affect the parallel

port pins.

1: The parallel port outputs, except the config-

ured IRQ line (IRQ5 or IRQ7), are in TRISTATE when either the parallel port is disabled or the chip is in power-down mode.

Bit 7 Reserved.

2.5.8 Tape, UARTs and Parallel Port Configuration Register (TUP, Index

07h)

The TUP Register is cleared to XXXXX0XX on reset.

Bit 1 Reserved.

Bit 2 EPP Timeout Interrupt Enable bit.

When this bit is 0, the EPP timeout interrupt is masked.

When this bit is 1, the EPP timeout interrupt is generated on the selected IRQ line (IRQ5 or IRQ7), according to bits[4:6]of PCR.

Bits 3–7 Reserved.

2.5.9 SuperI/O Identification Register (SID, Index

08h)

The SID Register is accessed, like the other configuration registers, through the Index Register. This read-only register is used to identify the PC87303 chip.

TL/C/12074– 86

2.5.10 Advanced SuperI/O Configuration Register (ASC, Index 09h)

During reset bits 0–2 and bit 5 are initialzed to 0, and bits 6 – 7 are initialized to 1.

Bit 0 IRQ5/DRATE0 select.

0: Pin 16 is IRQ5.

1: Pin 16 is ADRATE0 open drain output.

Selection of parallel port interrupt pin (IRQ5 or IRQ7) via bits 1 and 0 of FAR, and via bit 3 of PTR, is ignored and IRQ7 is used as parallel port interrupt. Unlike IRQ5, ADRATE0 is not controlled by bits 6 and 5 of PCR, it has the same value as DRATE0.

Bit 1 DRVE

/DR23 select.

0: Pin 78 is DRV2.

1: Pin 78 is DR23.

DR23 is asserted when either drive 2 or drive 3 is accessed (except during logical drive exchangeÐsee bit 3 of TDR).

The value of DR23

is undefined when working with four drives encoding (bit 4 of FER is 1). The PC87303 assumes DRV2

is 1 when bit 1 of ASC

is 1.

Bit 2 Enhanced TDR support.

0: TDR read is a function of bit 0 of FCR configu-

ration register. Pin 90 is IOCS16

Pin 87 is IDEHI

/VLD0.

1: Pin 90 is DRID0 input.

The PC87303 assumes IOCS16

is active when bit 2 of ASC is 1. Pin 87 is DRID1/VLD0

input.

Bit 2 of ASC should be set to one before the FDD is accessed, thus preventing contention between IDEHI

and DRID1.

The PC87303 provides full TDR support.

Bit 3 Reserved bit. On ASC writes, this bit must be

written with a 0. On ASC reads, the value is undefined.

Bit 4 Reserved.

Bit 5 The value of this pin is reflected on bit 3 of

CNFGA ECP register.

Bits 6, 7 System Operation Mode. The PC87303 can be

configured to either PC-AT, PS/2 or Model 30 modes.

00: Model 30 mode

01: PS/2 mode

10: Reserved and illegal

11: PC-AT mode

2.5.11 Chip Select 0 Configuration Register 0 (CS0CF0, Index

0Ah)

This register holds the low address bits of the monitored I/O address. See CS0CF1 register for complementary description. Bit 0 holds A0.

2.5.12 Chip Select 0 Configuration Register 1 (CS0CF1, Index

0Bh)

This register controls the behavior of the CS0

pin. CS0 is

asserted on non-DMA PIO cycles, when RD

or WR is as-

serted. CS0

can be asserted three ways: 1) only on reads

2) only on writes or 3) on all PIO cycles. The register is initialized to 0 during reset.

Bits 0–2 High address bits of the monitored I/O address.

Bit 2 holds A10, bit 1 holds A9 and bit 0 holds A8.

Bit 3 Reserved.

Bit 4 Enable CS0

assertion on write cycles.

Bit 5 Enable CS0 assertion on read cycles.

Bit 6 Enable full address-decoding.

0: Decode only address bits A9 – A0. Ignore ad-

dress bit A10.

1: Decode address bits A10 – A0

2.0 Configuration Registers (Continued)

Bit 7 CS0

Select Bit.

0:Pin2isCSinput.

1: Pin 2 is CS0 output. The PC87303 assumes

that CS

input is 1, thus bit 6 of KRR must be 1

to access the KBC.

2.5.13 Chip Select 1 Configuration Register 0 (CS1CF0, Index

0Ch)

This register holds the low address bits of the monitored I/O address. See CS1CF1 register for complementary description. Bit 0 holds A0.

2.5.14 Chip Select 1 Configuration Register 1 (CS1CF1, Index

0Dh)

This register controls the behaviour of the CS1 pin. CS1 is asserted on non-DMA PIO cycles, when RD

or WR is as-

serted. CS1

can be asserted in three ways: 1) only on reads

2) only on writes or 3) on all PIO cycles. The register is initialized to 0 during reset.

Bits 0–2 High address bits of the monitored I/O address.

Bit 2 holds A10, bit 1 holds A9 and bit 0 holds A8.

Bit 3 Reserved.

Bit 4 Enable CS1

assertion on write cycles.

Bit 5 Enable CS1 assertion on read cycles.

Bit 6 Enable full address-decoding.

0: Decode only address bits A9 – A0. Ignore ad-

dress bit A10.

1: Decode address bits A10 – A0

Bit 7 CS1

Select Bit.

0: Pin 23 is SYSCLK.

1: Pin 23 is CS1

output. The PC87303 assumes that SYSCLK input is 1, thus bit 7 of KRR must be 0 to operate the KBC.

2.6 POWER-DOWN OPTIONS

There are various methods for entering the power-down mode. All methods result in one of three possible modes. This section associates the methods of entering powerdown with the resulting mode.

Mode 1: The internal clock stops for a specific function (i.e., UART1 and/or UART2 and/or FDC).

This mode is entered by any of the following actions:

1. Clear the FER bit for the specific function that is powered down. See Section 2.5.1 FER bits 1 – 3.

2. During reset, set certain CFG 0–4 pins. See Table 2-1.

3. Execute the FDC Mode Command with PTR bit 1

(XTAL/CLK). See Section 4.2.6 LOW PWR.

4. Set Data Rate Select Register bit 6, in the FDC, high, with PTR bit 1

0. See Section 3.6 bit 6.

Mode 2: The internal clocks are stopped for all enabled functions.

Note: Clocks to disabled functions are always inactive.

This mode is entered by any of the following actions:

1. Clear all FER bits for any enabled function. See Section

2.5.1 FER bits 1 –3.

2. Clear PTR bits 1 (XTAL/CLK) and 2 (CSOUT/PWDN select). Then assert the PWDN

signal low. See Section

2.5.3 PTR bits 1,2 and Section 1.0 PWDN

pin.

3. Clear PTR bit 1 and then set PTR bit 0 (power-down) high. See Section 2.5.3 PTR bits 0 and 1.

Mode 3: The external crystal is stopped and internal clocks are stopped for all enabled functions.

This mode is entered by any of the following actions:

1. Clear all FER bits that enable the FDC, UART1, and UART2 functions. See Section 2.5.1 FER bits 1–3.

2. Set PTR bit 1 (XTAL/CLK), clear PTR bit 2 (CSOUT/ PWDN select). Then assert the PWDN

signal low. See

Section 2.5.3 PTR bits 1,2 and Section 1.0 PWDN

pin.

3. Set PTR bit 1 and then set PTR bit 0 high. See Section

2.5.3 PTR bits 0 and 1.

4. During reset, pull CFG0 – 4 pins high.

5. Execute the FDC Mode Command with PTR bit 1

See Section 4.2.6 LOW PWR.

6. Set Data Rate Select Register bit 6, in the FDC, high with PTR bit 1

1. See Section 3.6 bit 6.

2.7 POWER-UP PROCEDURE AND CONSIDERATIONS

2.7.1 Crystal Stabilization

If the crystal is stopped by putting either the FDC or the UARTs into low power mode, then a finite amount of time (E8 ms) must be allowed for crystal stabilization during subsequent power-up. The stabilization period can be sensed by reading the Main Status Register in the FDC, if the FDC is being powered up. (The Request for Master bit is not set forE8 ms.) If either one of the UARTs are being powered up, but the FDC is not, then the software must determine theE8 ms crystal stabilization period. Stabilization of the crystal can also be sensed by putting the UART into local loopback mode and sending bytes until they are received correctly.

2.7.2 UART Power-Up

The clock signal to the UARTs is controlled through the Configuration Registers (FER, PTR). In order to restore the clock signal to one or both UARTs the following conditions must exist:

1. The appropriate enable bit (FER 1,2) for the UART(s) must be set

2. and the power-down bit (PTR 0) must not be set

3. and if the PWDN pin option (PTR 2) is used the CSOUT

/PDWN pin must be inactive.

If the crystal has been stopped follow the guidelines in Section 2.7.1 before sending data or signalling that the receiver channel is ready.

2.7.3 FDC Power-Up

The clock signal to the FDC is controlled through the Configuration Registers, the FDC Mode Command and the Data Rate Select Register. In order to restore the clock signal to the FDC the following conditions must exist:

1. The appropriate enable bit (FER 3) must be set

2. and the power-down bit (PTR 0) must not be set

3. and if the PWDN pin option (PTR 2) is used the CSOUT

/PDWN pin must be inactive.

In addition to these conditions, one of the following must be done to initiate the recovery from power-down mode:

1. Read the Main Status Register until the RQM bit (MSR7) is set or

2.0 Configuration Registers (Continued)

2. Write to the Data Rate Select Register and set the Software Reset bit (DSR7) or

3. Write to the Digital Output Register, set and then clear the Reset bit (DOR2) or

4. Read the Data Register and the Main Status Register until the RQM bit is set.

If the crystal has been stopped, read the RQM bit in the Main Status Register until it is set. The RQM bit is not set until the crystal has stabilized.

3.0 FDC Register Description

The floppy disk controller is suitable for all PC-AT, EISA, PS/2, and general purpose applications. The operational mode (PC-AT, PS/2, and Model 30) of the FDC is determined by bits 7, 6 of ASC register. AT mode is the default. DP8473 and N82077 software compatibility is provided. Key features include a 16-byte FIFO, PS/2 diagnostic register support, perpendicular recording mode, CMOS disk interface, and a high performance analog data separator. See

Figure 3-1

The FDC supports the standard PC data rate drives of 250/ 500 kbps, 300/500 kbps, and 1 Mbps in MFM-encoded data mode, but is no longer guaranteed through functional testing to support the older FM encoded data mode. References to the older FM mode remain in this document to clarify the true functional operation of the device.

The 1 Mbps data rate is used by the high performance tape and floppy drives. The FDC supports these floppy drives which utilize high density media, and require the perpendicular recording mode format. When used with the 1 Mbps data rate, this new format allows the use of 4 MB floppy drives which format Extra Density (ED) media to 2.88 MB capacity.

The high performance internal analog data separator needs no external components. It improves on the window margin performance standards of the DP8473, and is compatible with the strict data separator requirements of floppy disk and floppy-tape drives.

The FDC contains write precompensation circuitry that defaults to 125 ns for 250 kbps, 300 kbps, and 500 kbps and to 41.67 ns for 1 Mbps. These values can be overridden in software to disable write precompensatoin or to provide levels of precompensation up to 250 ns.

TL/C/12074– 18

FIGURE 3-1. FDC Functional Block Diagram

3.0 FDC Register Description (Continued)

The FDC has internal 24 mA data bus buffers which allow direct connection to the system bus. The internal 40 mA totem-pole disk interface buffers are compatible with both CMOS drive inputs and 150X resistor terminated disk drive inputs.

3.1 FDC CONTROL REGISTERS

The following FDC registers are mapped into the addresses shown in Table 3-1 and described in the following sections. The base address range is provided by the on-chip address decoder pin. For PC-AT or PS/2 applications, the diskette controller primary address range is 3F0 to 3F7h, and the secondary address range is 370 to 377h. The FDC supports three different register modes: the PC-AT mode, PS/2 mode (Micro Channel systems), and the Model 30 mode (Model 30). See Section 5.2 for more details on how each register mode is enabled. When applicable, the register definition for each mode of operation is given. If no special notes are made, then the register is valid for all three register modes.

TABLE 3-1. Register Description and Addresses

A2 A1 A0 IDENT R/W Register

0 0 0 0 R Status Register A* SRA 0 0 1 0 R Status Register B* SRB 0 1 0 X R/W Digital Output Register DOR 0 1 1 X R/W Tape Drive Register TDR 1 0 0 X R Main Status Register MSR 1 0 0 X W Data Rate Select Register DSR 1 0 1 X R/W Data Register (FIFO) FIFO 1 1 0 X X None (Bus TRI-STATE) 1 1 1 X R Digital Input Register DIR 1 1 1 X W Configuration Control Register CCR

*Note: SRA and SRB are enabled by IDENTe0 during a chip reset only.

3.1.1 Status Register A (SRA) Read Only

This is a read-only diagnostic register that is part of the PS/2 floppy controller register set, and is enabled when in the PS/2 or Model 30 mode. This register monitors the state of the IRQ6 pin and some of the disk interface signals. The SRA can be read at any time when in PS/2 mode. In the PC-AT mode, D7 – D0 are TRI-STATE during a mP read.

SRAÐPS/2 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC IRQ6

DRV2

STEP TRK0 HDSEL INDX WP DIR

PEND

RESET

0 N/A 0 N/A 0 N/A N/A 0

COND

D7 Interrupt Pending: This active high bit reflects the

state of the IRQ6 pin.

D6 2nd Drive Installed

: Active low status of the

DRV2 disk interface input, indicating if a second drive has been installed.

D5 Step: Active high status of the STEP disk interface

output.

D4 Track 0

: Active low status of the TRK0 disk inter-

face input.

D3 Head Select: Active high status of the HDSEL disk

interface output.

D2 Index

: Active low status of the INDEX disk interface

input.

D1 Write Protect

: Active low status of the WP disk in-

terface input.

D0 Direction: Active high status of the DIR disk inter-

face output.

SRAÐModel 30 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC IRQ6

FDRQ STEP TRK0 HDSEL

INDX WP DIR

PEND

RESET

0 0 0 N/A 1 N/A N/A 1

COND

D7 Interrupt Pending: This active high bit reflects that

state of the IRQ6 pin.

D6 DMA Request: Active high status of the FDRQ sig-

nal.

D5 Step: Active high status of the latched STEP disk

interface output. This bit is latched with the STEP output goes active, and is cleared with a read from the DIR, or with a hardware or software reset.

D4 Track 0: Active high status of TRK0 disk interface

input.

D3 Head Select

: Active low status of the HDSEL disk

interface output.

D2 Index: Active high status of the INDEX disk inter-

face input.

D1 Write Protect: Active high status of the WP disk

interface input.

D0 Direction

: Active low status of the DIR disk inter-

face output.

3.1.2 Status Register B (SRB) Read Only

This read-only diagnostic register is part of the PS/2 floppy controller register set, and is enabled when in the PS/2 or Model 30 mode. The SRB can be read at any time when in PS/2 mode. In the PC-AT mode, D7– D0 are TRI-STATE during a mP read.

SRBÐPS/2 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC 1 1 DR0 WDATA RDATA WGATE MTR1 MTR0

RESET

N/A N/A 0 0 0 0 0 0

COND

D7 Reserved: Always 1.

D6 Reserved: Always 1.

D5 Drive Select 0: Reflects the status of the Drive Se-

lect 0 bit in the DOR (address 2, bit 0). It is cleared after a hardware reset, not a software reset.

D4 Write Data: Every inactive edge transition of the

WDATA disk interface output causes this bit to change states.

D3 Read Data: Every inactive edge transition of the

RDATA disk interface output causes this bit to change states.

D2 Write Gate: Active high status of the WGATE disk

interface output.

D1 Motor Enable 1: Active high status of the MTR1

disk interface output. Low after a hardware reset, unaffected by a software reset.

3.0 FDC Register Description (Continued)

D0 Motor Enable 0: Active high status of the MTR0

disk interface output. Low after a hardware reset, unaffected by a software reset.

SRBÐModel 30 Mode

D7 D6 D5 D4 D3 D2 D1 D0

DESC DRV2 DR1 DR0 WDATA RDATA WGATE DR3 DR2

RESET

N/A 1 1 0 0 0 1 1

COND

D7 2nd Drive Installed: Active low status of the

DRV2 disk interface input.

D6 Drive Select 1

: Active low status of the DR1 disk

interface output.

D5 Drive Select 0

: Active low status of the DR0 disk

interface output.

D4 Write Data: Active high status of latched WDATA

signal. This bit is latched by the inactive going edge of WDATA and is cleared by a read from the DIR. This bit is not gated by WGATE.

D3 Read Data: Active high status of latched RDATA

signal. It is latched by the active going edge of RDATA and is cleared by a read from the DIR.

D2 Write Gate: Active high status of latched WGATE

signal. This bit is latched by the active going edge of WGATE and is cleared by a read from the DIR.

D1 Drive Select 3

: Active low status of the DR3 disk

interface output.

Note: The MTR3, MTR2, DRV3, DRV2 pins are only available in

four-drive mode (bit 4 of FER is 1) and require external logic.

D0 Drive Select 2: Active low status of the DR2 disk

interface output.

Note: The MTR3, MTR2, DRV3, DRV2 pins are only available in

four-drive mode (bit 4 of FER is 1) and require external logic.

3.1.3 Digital Output Register (DOR) Read/Write

The DOR controls the drive select and motor enable disk interface outputs, enables the DMA logic, and contains a software reset bit. The contents of the DOR is set to 00 (hex) after a hardware reset, and is unaffected by a software reset. The DOR can be written to at any time.

DOR

D7 D6 D5 D4 D3 D2 D1 D0

DESC MTR3 MTR2 MTR1 MTR0 DMAEN RESET

DRIVE DRIVE

SEL 1 SEL 0

RESET

0000 0 0 0 0

COND

D7 Motor Enable 3: This bit controls the MTR3 disk

interface output.A1inthis bit causes the MTR3 pin to go active.

D6 Motor Enable 2: Same function as D7 except for

MTR2.

D5 Motor Enable 1: Same function as D7 except for

MTR1. (See bit 4 of FCR for further information.)

D4 Motor Enable 0: Same function as D7 except for

MTR0. (See bit 4 of FCR for further information.)

D3 DMA Enable: This bit has two modes of operation.

PC-AT mode or Model 30 mode: Writinga1tothis

bit enables the FDRQ, FDACK

, TC, and IRQ6 pins.

Writinga0tothis bit disables the FDACK

and TC pins and TRI-STATE the FDRQ and the IRQ6 pins. This bit is a 0 after a reset when in these modes.

PS/2 mode: This bit is reserved, and the FDRQ, FDACK

, TC, and IRQ6 pins are always enabled. Dur-

ing a reset, the FDRQ, FDACK

, TC, and IRQ6 lines

remain enabled, and D3 is 0.

D2 Reset Controller: Writinga0tothis bit resets the

controller. It remains in the reset condition until a 1 is written to this bit. A software reset does not affect the DSR, CCR, and other bits of the DOR. A software reset affects the Configure and Mode command bits (see Section 4.0 FDC Command Set Description). The minimum time that this bit must be low is 100 ns. Thus, toggling the Reset Controller bit during consecutive writes to the DOR is an acceptable method of issuing a software reset.

D1, D0 Drive Select: These two bits are binary encoded for

the four drive selects DR0 – DR3, so that only one drive select output is active at a time. (See bit 4 of FCR for further information.)

It is common programming practice to enable both the motor enable and drive select outputs for a particular drive. Table 3-2 below shows the DOR values to enable each of the four drives.

TABLE 3-2. Drive Enable Values

Drive DOR Value

0 1Ch

12D

24E

38F

Note: The MTR3, MTR2, DRV3, DRV2 pins are only available in four-drive

mode (bit 4 of FER is 1) and require external logic.

3.1.4 Tape Drive Register (TDR) Read/Write

The TDR register is the Tape Drive Register and the floppy disk controller media and drive type register. The register has three modes of operation (see Table 3-3):

Compatible PC-AT TDR mode. The register is used to assign a particular drive number to the tape drive support mode of the data separator. All other logical drives can be assigned as floppy drive support. Bits 2 – 7 are TRI-STATE during read.

Automatic Media Sense mode. Bits 5–7 are implemented, in addition to the bits of the Compatible PC-AT TDR mode. Bits 2 – 4 are reserved.

Enhanced mode. This is the PS/2 TDR mode. It uses all the register’s bits for operation with PS/2 floppy drives.

The use of the TDR bits, for each of these modes, is shown in Table 3-3.

3.0 FDC Register Description (Continued)

TABLE 3-3. TDR Operation Modes

Mode

FCR ASC

Bit D7 D6 D5 D4 D3 D2 D1 D0

Bit 0 Bit 2

Compatible PC-AT TDR 1 0

DESC X X X X X X

TAPE TAPE

SEL 1 SEL 0

RESET

N/A N/A N/A N/A N/A N/A 0 0

COND

Automatic Media Sense 0 0

DESC ED HD

VALID

XXX

TAPE TAPE

DATA SEL 1 SEL 0

RESET

N/A N/A N/A N/A N/A N/A 0 0

COND

Enhanced or

DESC ED HD DRID1 DRID0 SWP1 SWP0

TAPE TAPE SEL 1 SEL 0

RESET

N/A N/A N/A N/A 0 0 0 0

COND

D7 Extra Density: When bit 5 is 0, this media id bit is

used with bit 6 to indicate the type of media currently in the active floppy drive. If bit 5 is 1, it is invalid. This bit holds MSEN1 pin value. See Table 3-4 for details regarding bits 5 –7.

D6 High Density: When bit 5 is 0, this media id bit is

used with bit 7 to indicate the type of media currently in the active floppy drive. If bit 5 is 1, it is invalid. This bit holds MSEN0/DRATE0 pin value. See Table 3-4 for details regarding bits 5 – 7.

Note: Bits 6 and 7 of TDR are undefined when DRID0,1 pins are

configured as DRATE0,1.

D5 Valid Data: (For Automatic Media Sense mode)

The state of bit 5 is determined by the state of the VLD0,1

pins during reset. If this bit is 0, there is valid media id sense data in bits 7 and 6 of this register. Bit 5 holds VLD0

when drive 0 is accessed, and

media sense is configurfed. It holds VLD1

when drive 1 is accessed, and media sense is configured. Otherwise, it is set to 1 to indicate that media information is not available. See Table 3-4 for details regarding bits 5 – 7.

D4, 5 Drive ID0,1: (For Enhanced mode)

Bits 4 and 5 are read only bits which hold DRID0,1 pins values.

TABLE 3-4. Media ID Bits Functions

Bit 7 Bit 6 Bit 5 Media Type

X X 1 Invalid Data

0 0 0 5.25

0 1 0 2.88M

1 0 0 1.44M

1 1 0 720k

D3, 2 Bits 3 and 2 are read/write bits that control bits con-

trol logical drive exchange. When working with four drives encoding (bit 4 of FER is 1) the logical drive exchange is not performed.

00: No logical drive exchange.

01: logical drive exchange between drives 0 and 1

as done by bit 4 of FCR.

10: Logical drive exchange between drives 0 and 2.

This bit allows software to exchange the physical floppy-disk control signals, assigned to drive 0 and 2. The DR0

, DR23 and MTR0 pins func-

tion is exchanged as follows:

DR2

internal signal to DR0 pin.

MTR2

internal signal to MTR0 pin.

DR0 internal signal to DR23 pin.

Note: Drive 3 is not exchanged together wth drive 2.

11: Reserved. Unpredictable results when 11 is

configured.

D1, 0 Tape Select 1, 0: These bits assign a logical drive

number to a tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. See Table 3-5 for the tape drive assignment values.

TABLE 3-5. Tape Drive Assignment Values

TAPESEL1 TAPESEL0

Drive

Selected

0 0 None

011

102

113

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