NSC LM2524DN Datasheet
LM2524D/LM3524D
Regulating Pulse Width Modulator
General Description
The LM3524D family is an improved version of the industry
standard LM3524. It has improved specifications and additional featuresyet is pin for pin compatible with existing 3524
families. New features reduce the need for additional external circuitry often required in the original version.
The LM3524D has a
rent carrying capability of the output drive transistors has
been raised to 200 mAwhile reducing V
V
breakdown to 60V. The common mode voltage range of
CE
the error-amp has been raised to 5.5V to eliminate the need
for a resistive divider from the 5V reference.
In the LM3524D the circuit bias line has been isolated from
the shut-down pin. This prevents the oscillator pulse amplitude andfrequency from beingdisturbed by shut-down.Also
at high frequencies (
put has been improved to 44%compared to 35%max. duty
cycle in other 3524s.
In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure
±
1%precision 5V reference. The cur-
and increasing
CEsat
≅
300 kHz) the max. duty cycle per out-
one pulse per period even in noisy environments. The
LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of
the T-flip-flop will change only after the first clock pulse has
arrived. This feature prevents the same output from being
pulsed twice in a row, thus reducing the possibility of core
saturation in push-pull designs.
Features
n Fully interchangeable with standard LM3524 family
±
n
1%precision 5V reference with thermal shut-down
n Output current to 200 mA DC
n 60V output capability
n Wide common mode input range for error-amp
n One pulse per period (noise suppression)
n Improved max. duty cycle at high frequencies
n Double pulse suppression
n Synchronize through pin 3
LM2524D/LM3524D Regulating Pulse Width Modulator
June 1999
Block Diagram
DS008650-1
© 1999 National Semiconductor Corporation DS008650 www.national.com
Absolute Maximum Ratings (Note 5)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 40V
Collector Supply Voltage
(LM2524D) 55V
(LM3524D) 40V
Output Current DC (each) 200 mA
Internal Power Dissipation 1W
Operating Junction Temperature
Range (Note 2)
LM2524D −40˚C to +125˚C
LM3524D 0˚C to +125˚C
Maximum Junction Temperature 150˚
Storage Temperature Range −65˚C to +150˚C
Lead Temperature (Soldering 4 sec.)
M, N Pkg. 260˚C
Oscillator Charging Current (Pin 7) 5 mA
Electrical Characteristics
(Note 1)
Symbol Parameter Conditions Tested Design Tested Design Units
REFERENCE SECTION
V
V
V
REF
RLine
RLoad
Output Voltage 5 4.85 4.80 5 4.75 V
=
Line Regulation V
Load Regulation I
8V to 40V 10 15 30 10 25 50 mV
IN
=
0mAto20mA 10 15 25 10 25 50 mV
L
Ripple Rejection f=120 Hz 66 66 dB
LM2524D LM3524D
Typ Limit Limit Typ Limit Limit
(Note 3) (Note 4) (Note 3) (Note 4)
5.15 5.20 5.25 V
Min
Max
Max
Max
I
OS
Short Circuit V
Current 50 50
N
O
Output Noise 10 Hz ≤ f ≤ 10 kHz 40 100 40 100 µV
Long Term T
Stability
OSCILLATOR SECTION
f
f
OSC
OSC
Max. Freq. R
Initial R
Accuracy (Note 7) 20 20
∆f
OSC
∆f
OSC
Freq. Change V
with V
IN
Freq. Change T
with Temp. at 20 kHz R
V
OSC
Output Amplitude R
(Pin 3) (Note 8)
t
PW
Output Pulse R
Width (Pin 3)
Sawtooth Peak R
Voltage
Sawtooth Valley R
Voltage
ERROR-AMP SECTION
V
IO
Input Offset V
Voltage
I
IB
Input Bias V
=
0 25 25 mA Min
REF
180 200 mA Max
=
125˚C 20 20 mV/kHr
A
=
=
1k, C
T
0.001 µF 550 500 350 kHz
T
(Note 7)
=
T
=
5.6k, C
0.01 µF 17.5 17.5 kHz
T
22.5 22.5 kHz
=
R
T
=
2.7k, C
0.01 µF 34 30 kHz
T
(Note 7) 38 38
42 46 kHz
=
8 to 40V 0.5 1 0.5 1.0
IN
=
−55˚C to +125˚C
A
C
T
T
T
T
T
CM
CM
=
5.6k, 5 5
T
=
0.01 µF
=
=
=
=
=
5.6k, C
0.01 µF 3 2.4 3 2.4 V
T
=
5.6k, C
0.01 µF 0.5 1.5 0.5 1.5 µs
T
=
5.6k, C
0.01 µF 3.4 3.6 3.8 3.8 V
T
=
5.6k, C
0.01 µF 1.1 0.8 0.6 0.6 V
T
=
2.5V 2 8 10 210 mV
=
2.5V 1 8 10 110 µA
rms Max
Max
Max
%
Max
%
Min
Max
Max
Min
Max
Max
Min
Min
Min
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Electrical Characteristics (Continued)
(Note 1)
Symbol Parameter Conditions Tested Design Tested Design Units
ERROR-AMP SECTION
Current
I
IO
Input Offset V
=
2.5V 0.5 1.0 1 0.5 1 µA
CM
Current
I
COSI
Compensation V
IN(I)−VIN(NI)
=
150 mV 65 65 µA
Current (Sink) 95 95
I
COSO
Compensation V
IN(NI)−VIN(I)
=
150 mV −125 −125 µA
Current (Source) −95 −95
=
=
A
VOL
Open Loop Gain R
∞
,V
L
2.5 V 80 74 60 80 70 60 dB
CM
VCMR Common Mode 1.5 1.4 1.5 V
Input Voltage Range 5.5 5.4 5.5 V
CMRR Common Mode 90 80 90 80 dB
Rejection Ratio
G
BW
Unity Gain A
VOL
=
0 dB, V
=
2.5V 3 2 MHz
CM
Bandwidth
=
V
O
Output Voltage R
∞
L
Swing 5.5 5.5 V
PSRR Power Supply V
=
8 to 40V 80 70 80 65 db
IN
Rejection Ratio
COMPARATOR SECTION
Minimum Duty Pin 9=0.8V,
Cycle [R
=
T
5.6k, C
T
=
0.01 µF]
Maximum Duty Pin 9=3.9V,
Cycle [R
=
T
5.6k, C
T
=
0.01 µF]
Maximum Duty Pin 9=3.9V,
=
1k, C
=
T
0.001 µF]
V
COMPZ
Cycle [R
T
Input Threshold Zero Duty Cycle 1 1 V
(Pin 9)
V
COMPM
Input Threshold Maximum Duty Cycle 3.5 3.5 V
(Pin 9)
I
IB
Input Bias −1 −1 µA
Current
CURRENT LIMIT SECTION
V
SEN
Sense Voltage V
(Pin 2)−V(Pin 1)
≥ 180 180 mV
150 mV 200 200
TC-V
Sense Voltage T.C. 0.2 0.2 mV/˚C
sense
Common Mode −0.7 −0.7 V
Voltage Range V5−V
=
300 mV 1 1 V
4
SHUT DOWN SECTION
V
SD
High Input V
(Pin 2)−V(Pin 1)
≥ 1 0.5 1 0.5 V
Voltage 150 mV 1.5 1.5 V
I
SD
High Input I
(pin 10)
Current
OUTPUT SECTION (EACH OUTPUT)
V
CES
Collector Emitter IC≤ 100 µA 55 40 V
Voltage Breakdown
LM2524D LM3524D
Typ Limit Limit Typ Limit Limit
(Note 3) (Note 4) (Note 3) (Note 4)
125 125 µA
−65 −65 µA
0.5 0.5 V
00 0 0
49 45 49 45
44 35 44 35
220 220 mV
11 mA
Max
Min
Max
Min
Max
Min
Min
Max
Min
Min
Max
Min
%
Max
%
Min
%
Min
Min
Max
Min
Max
Min
Max
Min
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Electrical Characteristics (Continued)
(Note 1)
Symbol Parameter Conditions Tested Design Tested Design Units
OUTPUT SECTION (EACH OUTPUT)
I
CES
V
V
CESAT
EO
Collector Leakage V
Current V
Saturation I
Voltage I
Emitter Output I
=
60V
CE
=
55V 0.1 50 µA
CE
=
V
40V 0.1 50
CE
=
20 mA 0.2 0.5 0.2 0.7 V
E
=
200 mA 1.5 2.2 1.5 2.5
E
=
50 mA 18 17 18 17 V
E
Voltage
t
R
t
F
Rise Time V
Fall Time R
=
20V,
IN
=
−250 µA 200 200 ns
I
E
=
2k
R
C
=
2k 100 100 ns
C
SUPPLY CHARACTERISTICS SECTION
V
IN
Input Voltage After Turn-on 8 8 V
Range 40 40 V
T Thermal Shutdown (Note 2) 160 160 ˚C
Temp.
=
20V and f
=
40V (Note 6) 5 10 5 10 mA
IN
=
20 kHz.
OSC
=
=
T
25˚C. Boldface numbers applyover the rated temperaturerange: LM2524D is −40˚to85˚C
A
J
I
IN
Note 1: Unless otherwise stated, thesespecificationsapply for T
and LM3524D is 0˚C to 70˚C. V
Note 2: For operation at elevated temperatures,devices in the N package must be derated based on a thermal resistance of 86˚C/W, junction to ambient. Devices
in the M package must be derated at 125˚C/W, junction to ambient.
Note 3: Tested limits are guaranteed and 100%tested in production.
Note 4: Design limits are guaranteed (but not 100%production tested) over the indicated temperature and supply voltage range. These limits are not used to cal-
culate outgoing quality level.
Note 5: Absolute maximum ratings indicate limitsbeyond which damage to the device mayoccur. DC andAC electrical specifications do notapply when operating
the device beyond its rated operating conditions.
Note 6: Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2=2V.All other inputs and outputs open.
Note 7: The value of a C
in this test. NPO ceramic or polypropylene can also be used.
Note 8: OSC amplitude is measured open circuit. Available current is limited to 1 mAso care must be exercised to limit capacitive loading of fast pulses.
Stand By Current V
IN
capacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation. Polystyrene was used
t
LM2524D LM3524D
Typ Limit Limit Typ Limit Limit
(Note 3) (Note 4) (Note 3) (Note 4)
Max
Max
Min
Min
Max
Typical Performance Characteristics
Switching Transistor
Peak Output Current
vs Temperature
DS008650-28
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Maximum Average Power
Dissipation (N, M Packages)
Maximum & Minimum
Duty Cycle Threshold
Voltage
DS008650-29
DS008650-30
Typical Performance Characteristics (Continued)
Output Transistor
Saturation Voltage
Standby Current
vs Voltage
DS008650-31
DS008650-34
Output Transistor Emitter
Voltage
Standby Current
vs Temperature
DS008650-32
DS008650-35
Reference Transistor
Peak Output Current
DS008650-33
Current Limit Sense Voltage
DS008650-36
Test Circuit
DS008650-4
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Functional Description
INTERNAL VOLTAGE REGULATOR
The LM3524D has an on-chip 5V, 50 mA, short circuit protected voltage regulator. This voltage regulator provides a
supply for all internal circuitry ofthe device and can be used
as an external reference.
For input voltages of less than 8V the 5V output should be
shorted to pin 15, V
these pins shorted the input voltage must be limited to a
maximum of6V. If input voltages of 6V–8V are to be used, a
pre-regulator, as shown in
, which disables the 5V regulator. With
IN
Figure 1
, must be added.
DS008650-5
FIGURE 2.
*Minimum COof 10 µF required for stability.
DS008650-10
FIGURE 1.
OSCILLATOR
The LM3524D provides a stable on-board oscillator. Its frequency isset by an external resistor, R
graph of R
The oscillator’s output provides the signals for triggering an
vs oscillator frequency is shown is
T,CT
and capacitor, CT.A
T
Figure 2
internal flip-flop, which directs the PWM information to the
outputs, and a blanking pulse to turn off both outputs during
transitions to ensure that cross conduction does not occur.
The width of the blanking pulse, or dead time, is controlled
by thevalue of C
values of R
0.1 µF.
, asshown in
T
are 1.8 kΩ to 100 kΩ, and for CT, 0.001 µF to
T
Figure 3
. The recommended
If two or more LM3524D’s must be synchronized together,
the easiest method is to interconnect all pin 3 terminals, tie
all pin 7’s (together)to asingle C
except one which is connected to a single R
works well unless the LM3524D’s are more than 6" apart.
, and leave allpin 6’sopen
T
. This method
T
A second synchronization method is appropriate for any circuit layout.One LM3524D,designated asmaster, must have
its R
LM3524D(s) should each have an R
period. All pin 3’s must then be interconnected to allow the
set for the correct period. The other slave
TCT
set for a 10%longer
TCT
master to properly reset the slave units.
The oscillator may be synchronized to an external clock
source by setting the internal free-running oscillator frequency 10%slower than the external clock and driving pin 3
with a pulse train (approx. 3V) from the clock. Pulse width
should be greater than 50 ns to insure full synchronization.
.
FIGURE 3.
ERROR AMPLIFIER
The error amplifier is a differential input, transconductance
amplifier. Its gain, nominally 86dB, is set by either feedback
or output loading. This output loading can be done with either purely resistive or a combination of resistive and reactive components. A graph of the amplifier’s gain vs output
load resistance is shown in
Figure 4
.
DS008650-6
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DS008650-7
FIGURE 4.
The output of the amplifier, or input to the pulse width modulator, can be overridden easily as its output impedance is
very high (Z
≅
5MΩ). For this reason a DC voltage can be
O
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