NSC LM1247AAG-NA Datasheet

December 2002

LM1247 150 MHz I

C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs

n I

General Description

The LM1247 pre-amp is an integrated CMOS CRT preamp. It has an I the parameters necessary to directly setup and adjust the gain and contrast in the CRT display. Brightness and bias can be controlled through the DAC outputs which are well matched to the LM2479 and LM2480 integrated bias clamp ICs. The LM1247 preamp is also designed to be compatible with the LM246x high gain driver family.

Black level clamping of the video signal is carried out directly on the AC coupled input signal into the high impedance preamplifier input, thus eliminating the need for additional clamp capacitors. Horizontal and vertical blanking of the outputs is provided. Vertical blanking is optional and its duration is register programmable.

The IC is packaged in an industry standard 24 lead DIP molded plastic package.

C compatible interface which allows control of all

C compatible microcontroller interface

n OSD override allows OSD messages to override video

and the use of burn-in screens with no video input

n 4 DAC outputs (8-bit resolution) for bus controlled CRT

bias and brightness

n Spot killer which blanks the video outputs when V

falls below the specified threshold

n Suitable for use with discrete or integrated clamp, with

software configurable brightness mixer

n Horizontal blanking and OSD synchronization directly

from deflection signals. The blanking can be disabled, if desired

n Vertical blanking and OSD synchronization directly from

deflection signals. The blanking width is register programmable and can be disabled, if desired

n Power Saving Mode with 65% power reduction n Matched to LM246x driver and LM2479/80 bias IC’s

Character RAM and 4 DACs

LM1247 150 MHz I

C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512

Features

n Internal 512 character OSD ROM usable as either (a)

384 2-color plus 128 4-color characters, (b) 640 2-color characters, or (c) some combination in between

n Internal 512 character RAM, which can be displayed as

one single or two independent windows

Internal Block Diagram

Applications

n Low end 15" and 17" bus controlled monitors with OSD n 1024x768 displays up to 85 Hz requiring OSD capability n Very low cost systems with LM246x driver

20048401

FIGURE 1. Order Number LM1247AAG/NA

See NS Package Number N24D

Absolute Maximum Ratings (Notes 1, 3)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

LM1247

Distributors for availability and specifications.

Supply Voltage V

, Pins 10 and 18 6.0V

Peak Video DC Output Source Current

(Any One Amp) Pins 19, 20 or 21 1.5 mA

Voltage at Any Input Pin (V

Video Inputs (pk-pk) 0.0 ≤ V

Thermal Resistance to Ambient (θ

Power Dissipation (P

)VCC+0.5 ≥ VIN≥ −0.5V

) 51˚C/W

)

(Above 25˚C Derate Based

and TJ) 2.4W

on θ

Thermal Resistance to case (θ

Junction Temperature (T

) 32˚C/W

) 150˚C

≤ 1.2V

ESD Susceptibility (Note 4) 3.0 kV

ESD Machine Model (Note 13) 350V

Storage Temperature −65˚C to +150˚C

Lead Temperature (Soldering, 10 sec.) 265˚C

Operating Ratings (Note 2)

Temperature Range 0˚C to +70˚C

Supply Voltage V

Video Inputs (pk-pk) 0.0V ≤ V

4.75V ≤ VCC≤ 5.25V

≤ 1.0V

Video Signal Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.70 V

P-P,VABL=VCC,CL

numbers refer to the definitions in Table 1. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.

Symbol Parameter Conditions Min Typ Max Units

Supply Current Test Setting 1, both supplies, no

output loading. See (Note 8).

S-PS

O BLK

O BLK STEP

Supply Current, Power Save

Mode

Active Video Black Level Output

Voltage

Active Video Black Level Step

Test Setting 1, both supplies, no output loading. See (Note 8).

Test Setting 4, no AC input signal, DC offset (register 0x8438 set to 0xd5).

Test Setting 4, no AC input signal.

Size

Max Maximum Video Output Voltage Test Setting 3, Video in = 0.70 V

LE Linearity Error Test Setting 4, staircase input signal

(see (Note 9)).

Video Rise Time (Note 5), 10% to 90%, Test Setting 4,

AC input signal.

Rising Edge Overshoot (Note 5), Test Setting 4, AC input

signal.

Video Fall Time (Note 5), 90% to 10%, Test Setting 4,

AC input signal.

Falling Edge Overshoot (Note 5), Test Setting 4, AC input

signal.

BW Channel bandwidth (−3 dB) (Note 5), Test Setting 4, AC input

signal.

10 kHz Video Amplifier 10 kHz Isolation (Note 14), Test Setting 8. −60 dB

SEP

10 MHz Video Amplifier 10 MHz Isolation (Note 14), Test Setting 8. −50 dB

SEP

Max Maximum Voltage Gain Test Setting 8, AC input signal. 3.8 4.1 V/V

C-50% Contrast Attenuation@50% Test Setting 5, AC input signal. −5.2 dB

Min/AVMax Maximum Contrast Attenuation

Test Setting 2, AC input signal.

(dB)

AVG-50% Gain Attenuation@50% Test Setting 6, AC input signal. −4.0 dB

G-Min Maximum Gain Attenuation Test Setting 7, AC input signal. −11 dB

Match Maximum Gain Match between

Test Setting 3, AC input signal.

channels

Track Gain Change between channels Tracking when changing from Test

Setting 8 to Test Setting 5. See (Note

11).

= 8 pF, Video Outputs = 2.0 V

195 250 mA

55 85 mA

1.2 VDC

100 mVDC

P-P

4.0 4.3 V

3.1 ns

2.9 ns

150 MHz

−20 dB

0.5

0.5 dB

. Setting

P-P

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Video Signal Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.70 V

P-P,VABL=VCC,CL

numbers refer to the definitions in Table 1. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.

Symbol Parameter Conditions Min Typ Max Units

TH ABL Control Range upper limit (Note 12), Test Setting 4, AC input

ABL

signal.

Range ABL Gain Reduction Range (Note 12), Test Setting 4, AC input

ABL

signal.

V 3.5/AV Max

V 2.0/AV Max

Active ABL Input bias current during

ABL

Max ABL input current sink capability (Note 12), Test Setting 4, AC input

ABL

ABL Gain Reduction at 3.5V (Note 12), Test Setting 4, AC input

signal. V

ABL

= 3.5V

ABL Gain Reduction at 2.0V (Note 12), Test Setting 4, AC input

signal. V

ABL

= 2.0V

(Note 12), Test Setting 4, AC input

ABL

signal. V

ABL=VABL

MIN GAIN

signal.

Max Maximum ABL Input voltage

ABL

during clamping

ABL Track ABL Gain Tracking Error (Note 9), Test Setting 4, 0.7 V

(Note 12), Test Setting 4, AC input signal. I

ABL=IABL

MAX

input signal, ABL voltage set to 4.5V and 2.5V.

Minimum Input resistance (pins 5,

Test Setting 4.

6, 7)

= 8 pF, Video Outputs = 2.0 V

4.8 V

2.8 V

−2 dB

−12 dB

P-P

20 MΩ

P-P

10 µA

1.0 mA

0.1

4.5 %

. Setting

LM1247

OSD Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.

Symbol Parameter Conditions Min Typ Max Units

OSDHIGH

∆V

max Maximum OSD Level with OSD

Contrast 11

10 Maximum OSD Level with OSD

Contrast 10

01 Maximum OSD Level with OSD

Contrast 01

00 Maximum OSD Level with OSD

Contrast 00

(Black) Difference between OSD Black

OSD

Level and Video Black Level (same channel)

(White) Output Match between Channels Palette Set at 111, OSD Contrast =

OSD

Palette Set at 111, OSD Contrast = 11, Test Setting 3

Palette Set at 111, OSD Contrast = 10, Test Setting 3

Palette Set at 111, OSD Contrast = 01, Test Setting 3

Palette Set at 111, OSD Contrast = 00, Test Setting 3

11, Maximum difference between R,

4.5 V

3.9 V

3.2 V

2.4 V

20 mV

G and B

(Track) Output Variation between Channels OSD contrast varied from max to

OSD-out

min

DAC Output Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

Min DAC

Max DAC

Mode 00

Max DAC

Mode 01

Min output voltage of DAC Register Value = 0x00 0.5 0.7 V

Max output voltage of DAC Register Value = 0xFF,

DCF[1:0] = 00b

Max output voltage of DAC in DCF mode 01

= 8 pF, Video Outputs = 2.0 V

3.7 4.2 V

1.85 2.35 V

. See (Note 7)

P-P

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DAC Output Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

LM1247

for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.

ABL=VCC,CL

Symbol Parameter Conditions Min Typ Max Units

∆V

Max DAC

(Temp)

∆V

Max DAC(VCC

Variation in voltage of DAC with temperature

) DAC output voltage variation with

<T<

70˚C ambient

VCCvaried from 4.75V to 5.25V, DAC register set to mid-range (0x7F)

Linearity Linearity of DAC over its range 5 %

Monotonicity Monotonicity of the DAC

Excluding dead zones

MAX

Max Load Current −1.0 1.0 mA

= 8 pF, Video Outputs = 2.0 V

0.5 mV/˚C

50 mV

0.5 LSB

. See (Note 7)

P-P

System Interface Signal Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

VTH+

VFLYBACK positive switching

Vertical Blanking triggered

guarantee

SPOT

Ref

(SCL, SDA) Logic Low Input Voltage −0.5 1.5 V

(SCL, SDA) Logic High Input Voltage

(SCL, SDA) Logic Low Input Current SDA or SCL, Input Voltage = 0.4V

(SCL, SDA) Logic High Input Voltage SDA or SCL, Input Voltage = 4.5V

(SCL, SDA) Logic Low Output Voltage IO= 3 mA 0.5 V

Min Minimum Horizontal Frequency PLL & OSD Operational; PLL Range

Spot Killer Voltage (Note 17), VCCAdjusted to Activate 3.4 3.9 4.3 V

Output Voltage (pin 2) 1.25 1.45 1.65 V

Ref

Max Maximum Horizontal Frequency PLL & OSD Operational; PLL Range

Max Horizontal Flyback Input Current Absolute Maximum During

HFB IN

Flyback

HFB OUT

OUT

IN THRESHOLD

H-BLANK ON

Max Horizontal Flyback Input Current Absolute Maximum During Scan −700 µA

Peak Current during flyback Design Value 4 mA

Peak Current during Scan Not exact - Duty Cycle Dependent −550 µA

IINH-Blank Detection Threshold 0 µA

H-Blank Time Delay - On + Zero crossing of I

output blanking start. I

H-BLANK OFF

H-Blank Time Delay - Off − Zero crossing of I

output blanking end. I

Max Maximum Video Blanking Level Test Setting 4, AC input signal 0 0.25 V

BLANK

FREERUN

Free Run H Frequency, including H Blank

PW CLAMP

CLAMP MAX

Minimum Clamp Pulse Width See (Note 15) 200 ns

Maximum Low Level Clamp

Video Clamp Functioning

Pulse Voltage

CLAMP MIN

Minimum High Level Clamp

Video Clamp Functioning

Pulse Voltage

Low Clamp Gate Low Input Current V23= 2V −0.4 µA

CLAMP

High Clamp Gate High Input Current V23= 3V 0.4 µA

CLAMP

CLAMP-VIDEO

Time from End of Clamp Pulse to Start of Video

Referenced to Blue, Red and Green inputs

= 8 pF, Video Outputs = 2.0 V

to 50% of

HFB

= +1.5mA

to 50% of

HFB

= −100µA

. See (Note 7)

P-P

2.0 V

3.0

± ±

VCC+

0.5

10 µA

25 kHz

110 kHz

5mA

45 ns

85 ns

42 kHz

2.0 V

3.0 V

50 ns

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System Interface Signal Characteristics (Continued)

Note 1: Limits of Absolute Maximum Ratings indicate below which damage to the device must not occur.

Note 2: Operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.

Note 3: All voltages are measured with respect to GND, unless otherwise specified.

Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

Note 5: Input from signal generator: t

Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.

Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. The guaranteed specifications apply only for the test conditions

listed. Some performance characteristics may change when the device is not operated under the listed test conditions.

Note 8: The supply current specified is the quiescent current for V therefore all the supply current is used by the pre-amp.

Note 9: Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 V with each at least 100 ns in duration.

Note 10: dt/dV

Note 11: ∆A

gain change between any two amplifiers with the contrast set to A amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to A gain change of 10.0 dB with a tracking change of

Note 12: The ABL input provides smooth decrease in gain over the operational range of 0 dB to −5 dB: ∆A V

ABL MIN GAIN

Note 13: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).

Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at f

Note 15: A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer clamp pulse may be required.

Note 16: Adjust input frequency from 10 MHz (A

Note 17: Once the spot killer has been activated, the LM1247 remains in the off state until V

= 200*(t

track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in

). Beyond −5 dB the gain characteristics, linearity and pulse response may depart from normal values.

5.5V–t4.5V

r,tf

)/ ((t

1 ns.

and 5V Dig with RL=∞. Load resistors are not required and are not used in the test circuit,

5.5V+t4.5V

)) %/V, where: t

0.2 dB.

= 10 MHz for V

max reference level) to the −3 dB corner frequency (f

is the rise or fall time at VCC= 5.5V, and t

5.5V

C−50% and measured relative to the AVmax condition. For example, at AVmax the three

10 MHz.

SEP

level at the input. All 16 steps equal,

P-P

is the rise or fall time at VCC= 4.5V.

4.5V

C−50%. This yields a typical

= A(V

ABL

−3 dB

is cycled (reduced below 0.5V and then restored to 5V).

ABL=VABL MAX GAIN

)–A(V

ABL

LM1247

Hexadecimal and Binary Notation

Hexadecimal numbers appear frequently throughout this document, representing slave and register addresses, and register values. These appear in the format “0x...”. For example, the slave address for writing the registers of the LM1247 is hexadecimal BA, written as 0xBA. On the other hand, binary values, where the individual bit values are shown, are indicated by a trailing “b”. For example, 0xBA is equal to 10111010b. A subset of bits within a register is referred to by the bit numbers in brackets following the

TABLE 1. Test Settings

Control No. of Bits

Contrast 7 0x7F

B, R, G

7 0x7F

Gain

DC Offset 3 0x00

1234 5678

(Max)

0x00

Min

0x7F

(Max)

0x7F

(Max)

0x7F

(Max)

0x05 0x07

(Min)

(Max)

register value. For example, the OSD contrast bits are the fourth and fifth bits of register 0x8438. Since the first bit is bit 0, the OSD contrast register is 0x8438[4:3].

Register Test Settings

Table 1 shows the definitions of the Test Settings 1–8 referred to in the specifications sections. Each test setting is a combination of five hexadecimal register values, Contrast, Gain (Blue, Red, Green) and DC offset.

Test Settings

0x7F

(Max)

Set V

P-P

0x05 0x05 0x05 0x05 0x05

0x40

(50.4%)

0x7F

(Max)

0x7F

(Max)

0x40

(50.4%)

0x7F

(Max)

0x00 (Min)

0x7F

(Max)

0x7F

(Max)

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LM1253A and LM1237 Compatibility

In order to maintain register compatibility with the LM1253A

LM1247

and LM1237 preamplifier datasheet assignments for bias and brightness, the color assignments are recommended as

TABLE 2. LM1253A/LM1237 Compatibility

LM1247 Pin: DAC 1 DAC 2 DAC 3 DAC 4

Assignment: Blue Green Red Brightness

shown in Table 2. If datasheet compatibility is not required, then the DAC assignments can be arbitrary.

DAC Bias Outputs

OSD vs Video Intensity

The OSD amplitude has been increased over the LM1237 level. During monitor alignment, the three gain registers are used to achieve the desired front of screen color balance. This also causes the OSD channels to be adjusted accordingly, since these are inserted into the video channels prior to the gain attenuators. This provides the means to fine tune the intensity of the OSD relative to the video as follows. If a typical starting point for the alignment is to have the gains at maximum (0x7F) and the contrast at 0x55, the resultant OSD intensity will be higher than if the starting point is with the gains at 0x55 and the contrast at maximum (0x7F). This tradeoff allows fine tuning the final OSD intensity relative to the video. In addition, the OSD contrast register, 0x8438 [4:3], provides 4 major increments of intensity. Together, these allow setting the OSD intensity to the most pleasing level.

ESD Protection

The LM1247 features a 3.0 KV ESD protection level (see (Notes 4, 13)). This is provided by special internal circuitry which activates when the voltage at any pin goes beyond the supply rails by a preset amount. At that time the protection is applied to all pins, including SDA and SCL. If any signal other than these two is applied to the LM1247 while the V is near zero, such as horizontal and vertical deflection pulses of sufficient amplitude, this protection will activate and prevent any communication on the I LM1247, until the other signal or signals are removed. Normally, with all other pins unenergized, the LM1247 will not

C communication when it is powered down.

affect I

C bus common to the

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LM1247

Typical Performance Characteristics V

20048402

FIGURE 2. Logic Horizontal Blanking

= 5V, TA= 25˚C unless otherwise specified

FIGURE 5. Deflection Vertical Blanking

20048405

FIGURE 3. Logic Vertical Blanking

FIGURE 4. Deflection Horizonal Blanking

20048403

20048404

20048406

FIGURE 6. Logic Clamp Pulse

20048407

FIGURE 7. Red Cathode Response

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Typical Performance Characteristics V

= 5V, TA= 25˚C unless otherwise specified (Continued)

LM1247

20048408

FIGURE 8. ABL Gain Reduction Curve

SYSTEM INTERFACE SIGNALS

The Horizontal and Vertical Blanking and the Clamping input signals are important for proper functionality of the LM1247. Both blanking inputs must be present for OSD synchronization. In addition, the Horizontal blanking input also assists in setting the proper cathode black level, along with the Clamping pulse. The Vertical blanking input initiates a blanking level at the LM1247 outputs which is programmable from 3 to 127 lines (we recommend at least 10). Both horizontal and vertical blanking can be individually disabled, if desired.

Figure 2 and Figure 3 show the case where the Horizontal and Vertical inputs are logic levels. Figure 2 shows the smaller pin 24 voltage superimposed on the horizontal blanking pulse input to the neck board with R voltage at pin 24 is clamped to about 1 volt when the pin is sinking current. Figure 3 shows the smaller pin 1 voltage superimposed on the vertical blanking input to the neck board with C

jumpered and RV= 4.7k. These component values

correspond to the application circuit of Figure 9. Figure 4 and Figure 5 show the case where the horizontal and vertical inputs are from deflection. Figure 4 shows the pin 24

voltage which is derived from a horizontal flyback pulse of 35V peak to peak with R the pin 1 voltage which is derived from a vertical flyback pulse of 55V peak to peak with C

Figure 6 shows the pin 23 clamp input voltage superimposed on the neck board clamp logic input pulse. R chosen to limit the pin 23 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9.

= 4.7k and C17= 0.1 µF. Note where the

= 8.2K and C17jumpered. Figure 5 shows

= 1500 pF and RV= 120k.

= 1k and should be

CATHODE RESPONSE

Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video risetime is 1.5 ns. The resulting leading edge has a 7.1 ns risetime and a 7.6% overshoot, while the trailing edge has a 7.1 ns risetime and a 6.9% overshoot with an LM2467 driver.

ABL GAIN REDUCTION

The ABL function reduces the contrast level of the LM1247 as the voltage on pin 22 is lowered from V shows the amount of gain reduction as the voltage is lowered from V

(5.0V) to 2V. The gain reduction is small until V22reaches

to around 2V. Figure 8

the knee anound 3.7V, where the slope increases. Many system designs will require about 3 dB to 5 dB of gain reduction in full beam limiting. Additional attenuation is possible, and can be used in special circumstances. However, in this case, video performance such as video linearity and tracking between channels will tend to depart from normal specifications.

OSD PHASE LOCKED LOOP

Table 3 shows the recommended horizontal scan rate ranges (in kHz) for each combination of PLL register setting, 0x843E [1:0], and the pixels per line register setting, 0x8401 [7:5]. These ranges are recommended for chip ambient temperatures of 25

C. While the OSD PLL will lock for other register combinations and at scan rates outside these ranges, the performance of the

70 loop will be improved if these recommendations are followed. NR means the combination of PLL and PPL is not recommended for any scan rate.

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Cto

LM1247

Typical Performance Characteristics V

=5V,TA= 25˚C unless otherwise specified (Continued)

TABLE 3. OSD Register recommendations

PPL=0 PPL=1 PPL=2 PPL=3 PPL=4 PPL=5 PPL=6 PPL=7

PLL=1 25 - 61 25 - 53 25 - 48 25 - 43 25 - 40 25 - 36 25 - 34 25 - 31

PLL=2 NR NR 48 - 98 43 - 88 40 - 81 36 - 74 34 - 69 31 - 64

PLL=3 NR NR NR 88 - 110 81 - 110 74 - 110 69 - 110 64 - 110

Pin Descriptions and Application Information

Pin No.

Pin Name Schematic Description

1 V Flyback

Required for OSD synchronization and is also used for vertical blanking of the video outputs. The actual switching threshold is about 35% of

. For logic level inputs C4can be a jumper,

but for flyback inputs, an AC coupled differentiator is recommended, where R enough to prevent the voltage at pin 1 from exceeding V

be small enough to flatten the vertical rate ramp

REF

at pin 1. C

Bypass Provides filtering for the internal voltage which

sets the internal bias current in conjunction with

. A minimum of 0.1 µF is recommended for

EXT

proper filtering. This capacitor should be placed as close to pin 2 and the pin 4 ground return as possible.

or going below GND. C4should

may be needed to reduce noise.

is large

REF

4 Analog Input

Ground

Blue Video In

Red Video In

Green Video In

External resistor, 10k 1%, sets the internal bias current level for optimum performance of the LM1247. This resistor should be placed as close to pin 3 and the pin 4 ground return as possible.

This is the ground for the input analog portions of the LM1247 internal circuitry.

These video inputs must be AC coupled with a .0047 µF cap. Internal DC restoration is done at these inputs. A series resistor of about 33Ω and external ESD protection diodes should also be used for protection from ESD damage.

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Pin Descriptions and Application Information (Continued)

LM1247

No.

Pin Name Schematic Description

810Digital Ground

PLL V

9 PLL Filter

The ground pin should be connected to the rest of the circuit ground by a short but independent PCB trace to prevent contamination by extraneous signals. The V isolated from the rest of the V

pin should be

line by a ferrite

bead and bypassed to pin 8 with an electrolytic capacitor and a high frequency ceramic.

Recommended topology and values are shown to the left. It is recommended that both filter branches be bypassed to the independent ground as close to pin 8 as possible. Great care should be taken to prevent external signals from

coupling into this filter from video, I

C, etc.

11 SDA

12 SCL

DAC 4 Output

DAC 2 Output

DAC 3 Output

DAC 1 Output

The I2C compatible data line. A pull-up resistor of about 2 kΩ should be connected between this pin and V

. A resistor of at least 100Ω should

be connected in series with the data line for additional ESD protection.

The I2C compatible clock line. A pull-up resistor of about 2 kΩ should be connected between this pin and V

. A resistor of at least 100Ω should

be connected in series with the clock line for additional ESD protection.

DAC outputs for cathode cut-off adjustments and brightness control. DAC 4 can be set to change the outputs of the other three DACs, acting as a brightness control. The DAC values and the

special DAC 4 function are set through the I

C compatible bus. A resistor of at least 100Ω should be connected in series with these outputs for additional ESD protection.

17 18

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Ground

Ground pin for the output analog portion of the LM1247 circuitry, and power supply pin for all the analog of the LM1247. Note the recommended charge storage and high frequency capacitors which should be as close to pins 17 and 18 as possible.

Pin Descriptions and Application Information (Continued)

LM1247

Pin No.

19 20 21

Pin Name Schematic Description

Green Output

Red Output

Blue Output

22 ABL

23 CLAMP

These are the three video output pins. They are intended to drive the LM246x family of cathode drivers. Nominally, about 2V peak to peak will produce 40V peak to peak of cathode drive.

The Automatic Beam Limiter input is biased to the desired beam current limit by R and normally keeps D

forward biased. When

INT

ABL

and V

the current resupplying the CRT capacitance (averaged by C

) exceeds this limit, then D

ABL

INT

begins to turn off and the voltage at pin 22 begins to drop. The LM1247 then lowers the gain of the three video channels until the beam current reaches an equilibrium value.

This pin accepts either TTL or CMOS logic levels. The internal switching threshold is approximately one-half of V series resistor, R

, of about 1K is

. An external

recommended to avoid overdriving the input devices. In any event, R

must be large

EXT

enough to prevent the voltage at pin 23 from going higher than V

or below GND.

24 H Flyback

Proper operation requires current reversal. R

should be large enough to limit the peak current at pin 24 to about +4 ma during blanking, and

−500 µA during scan. C

is usually needed for

logic level inputs and should be large enough to make the time constant, R larger than the horizontal period. R

HC17

significantly

and C8are

typically 300Ω and 330 pF when the flyback waveform has ringing and needs filtering. C

may be needed to filter extraneous noise and can be up to 100 pF.

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Schematic Diagram

LM1247

FIGURE 9. LM123x/LM124x-LM246x Demo Board Schematic

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20048424

Schematic Diagram

LM1247

FIGURE 10. LM123x/LM124x-LM246x Demo Board Schematic (continued)

20048425

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PCB Layout

LM1247

FIGURE 11. LM123x/LM124x-LM246x Demo Board Layout

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OSD Generator Operation

LM1247

FIGURE 12. OSD Generator Block Diagram

PAGE OPERATION

Figure 12 shows the block diagram of the OSD generator. OSD screens are created using any of the 512 predefined characters stored in the mask programmed ROM. The OSD image is composed of up to 512 characters stored in page RAM, where each character has a unique 8-bit address. This means only half of the 512 ROM characters can be displayed at any one time. Since a 9 bit address is needed to select from 512 ROM addresses, a bank select register is used to convert the upper 2 bits of the character code into a 3 bit bank address which is combined with the other 6 bits to produce the necessary 9 bits. Also, since the lower 6 bits can address 64 characters, this gives a bank size of 64. Therefore, the ROM consists of 8 banks of 64 characters each, where 4 of these 8 banks are displayed by loading the 4 bank address registers with the appropriate 3 bit code. This allows the programmer to switch between two different OSD images, by simply reprogramming the bank addresses.

OSD ROM CONFIGURATION

The OSD ROM is equivalent to two 256 character ROMs of the type used in the LM1253A and LM1237. Because of the bank select method described earlier, each can be considered as a group of 3 banks (192) two-color characters followed by 1 bank (64) four-color characters. Physically, the combined ROM is then 192x2 + 64x4 + 192x2 + 64x4. This is shown in Figure 12.

BANK ADDRESSING

A pictorial view of this addressing method is shown in Figure

13. On the left side is a section of the Page RAM with four

different addresses in successive locations, which have been chosen to demonstrate accessing 4 of the 8 ROM banks using the Bank Select Registers. The first has 10b for

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the two most significant bits, so the OSD generator looks in B2AD[2:0], located in Bank Select Register B, for its ROM bank address. SInce B2AD[2:0] contains 101b, the character font is read from Bank 5. The complete font address is composed of this bank address, plus the lower six bits of the original byte in Page RAM, giving a ROM address of 101101110b. The remaining addresses demonstrate that the four selected banks can be displayed in any order.

END-OF-LINE AND END-OF-SCREEN CODES

There are two special character addresses used in the page RAM, 0x00 (End-of-Screen) and 0x01 (End-of-Line). The first must be used to terminate a window and the second to terminate a line. The LM1247 is different from the LM1253A and LM1237 in that these are now not actually encoded into ROM, but are instead detected by the logic as the OSD image is read from page RAM. This means that the two lowest locations in the bank which is currently selected by Bank Select Register 0, 0x8427[2:0], cannot be displayed in an OSD image. However, these two characters can be masked in the ROM, and if this bank is selected by Bank Select Registers 1, 2 or 3, then these two characters are usable on screen. The consequences of this is that only 254 ROM characters are displayable at one time.

DISPLAYING AN OSD IMAGE

Consecutive lines of characters make up the displayed window. These characters are stored in the page RAM through

C compatible bus. Each line can contain any number of

the I characters up to the limit of the displayable line length (dependent on the pixels per line register), although some restrictions concerning the enhanced features apply on character lines longer than 32 characters. The number of characters across the width and height of the page can be

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