NSC LM12458CIVF, LM12458CIV, LM12454CIV Datasheet
LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with
Self-Calibration
July 1999
LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with Self-Calibration
General Description
The LM12454, LM12458, and LM12H458 are highly integrated Data Acquisition Systems. Operating on just 5V, they
combine a fully-differential self-calibrating (correcting linearity and zero errors) 13-bit (12-bit + sign) analog-to-digital
converter (ADC) and sample-and-hold (S/H) with extensive
analog functions and digital functionality. Up to 32 consecutive conversions, using two’s complement format, can be
stored in an internal 32-word (16-bit wide) FIFO data buffer.
An internal 8-word RAM can store the conversion sequence
for up to eight acquisitions through the LM12(H)458’s
eight-input multiplexer. The LM12454 has a four-channel
multiplexer,a differential multiplexer output, and a differential
S/H input. The LM12454 and LM12(H)458 can also operate
with 8-bit + sign resolution and in a supervisory “watchdog”
mode that compares an input signal against two programmable limits.
Programmable acquisition times and conversion rates are
possible through the use of internal clock-driven timers. The
reference voltage input can be externally generated for absolute or ratiometric operation or can be derived using the internal 2.5V bandgap reference.
All registers, RAM, and FIFO are directly addressable
through the high speed microprocessor interface to either an
8-bit or 16-bit databus. The LM12454 and LM12(H)458 include a direct memory access (DMA) interface for
high-speed conversion data transfer.
An evaluation/interface board is available. Order number LM12458EVAL.
Additional applications information can be found in applications notes AN-906, AN-947 and AN-949.
Key Specifications
=
(f
5 MHz; 8 MHz, H)
CLK
j
Resolution 12-bit + sign or 8-bit + sign
j
13-bit conversion time 8.8 µs, 5.5 µs (H) (max)
j
9-bit conversion time 4.2 µs, 2.6 µs (H) (max)
j
13-bit Through-put rate 88k samples/s (min),
j
Comparison time
(“watchdog” mode)
j
ILE
j
VINrange GND to V
j
Power dissipation 30 mW, 34 mW (H) (max)
j
Stand-by mode 50 µW (typ)
j
Single supply 3V to 5.5V
140k samples/s (H) (min)
2.2 µs (max),
1.4 µs (H) (max)
±
1 LSB (max)
Features
n Three operating modes: 12-bit + sign, 8-bit + sign, and
“watchdog”
n Single-ended or differential inputs
n Built-in Sample-and-Hold and 2.5V bandgap reference
n Instruction RAM and event sequencer
n 8-channel (LM12(H)458), 4-channel (LM12454)
multiplexer
n 32-word conversion FIFO
n Programmable acquisition times and conversion rates
n Self-calibration and diagnostic mode
n 8- or 16-bit wide databus dmicroprocessor or DSP
interface
+
A
Applications
n Data Logging
n Instrumentation
n Process Control
n Energy Management
n Inertial Guidance
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
®
AT
is a registered trademark of International Business Machines Corporation.
© 1999 National Semiconductor Corporation DS011264 www.national.com
Ordering Information
Guaranteed Guaranteed Order See NS
Clock Freq (min) Linearity Error (max) Part Number Package Number
8 MHz
5 MHz
±
1.0 LSB LM12H458CIV V44A
LM12H458CIVF VGZ44A
LM12H458MEL/883 EL44A
or 5962-9319502MYA
±
1.0 LSB LM12454CIV V44A
LM12458CIV V44A
LM12458CIVF VGZ44A
Connection Diagrams
Order Number LM12458CIVF or LM12H458CIVF
* Pin names in ( ) apply to the LM12454 and LM12H454.
DS011264-2
Order Number LM12454CIV,
LM12458CIV or LM12H458CIV
See NS Package Number V44A
Order Number LM12H458MEL/883 or 5962-9319502MYA
See NS Package Number EL44A
See NS Package Number VGZ44A
DS011264-34
www.national.com 2
Functional Diagrams
LM12454
DS011264-1
LM12(H)458
DS011264-21
www.national.com3
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Input and Output Pins
except IN0–IN3 (LM12454) −0.3V to V
and IN0–IN7 (LM12(H)458)
Voltage at Analog Inputs IN0–IN3 (LM12454)
and IN0–IN7 (LM12(H)458) GND − 5V to V
+−VD+| 300 mV
|V
A
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (T
V Package (Note 4) 875 mW
Storage Temperature −65˚C to +150˚C
Lead Temperature
V Package, Infrared, 15 sec. +300˚C
EL and W Packages,
Solder, 10 sec. +250˚C
+ and VD+) 6.0V
A
+
+ 0.3V
+
±
5mA
±
=
25˚C)
A
20 mA
+5V
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
Operating Ratings (Notes 1, 2)
Temperature Range
≤ TA≤ T
(T
min
LM12454CIV/
LM12(H)458CIV −40˚C ≤ T
LM12458MEL/883 −55˚C ≤ T
Supply Voltage
+, VD+ 3.0V to 5.5V
V
A
+−VD+| ≤100 mV
|V
A
Input Range GND ≤ V
V
IN+
Input Range GND ≤ V
V
IN−
Input Voltage 1V ≤ V
V
REF+
Input Voltage 0V ≤ V
V
REF−
V
REF+−VREF−
Common Mode
V
REF
Range (Note 16) 0.1 V
max
)
A
IN+
IN−
REF+
≤ V
REF−
REF+
1V ≤ V
REF
+
≤ V
A
REFCM
≤ 0.6 V
ESD Susceptibility (Note 5) 1.5 kV
LM12458MEL/883 2.0 kV
Converter Characteristics (Notes 6, 7, 8, 9, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V, V
12-bit + sign conversion mode, f
and V
V
REF+
otherwise specified. Boldface limits apply for T
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
REF−
=
8.0 MHz (LM12H458) or f
CLK
A
=
5.0 MHz (LM12454/8), R
CLK
=
=
to T
T
T
J
MIN
; all other limits T
MAX
S
=
=
T
A
J
Symbol Parameter Conditions Typical Limits Unit
(Note 10) (Note 11) (Limit)
ILE Positive and Negative Integral After Auto-Cal (Notes 12, 17)
±
Linearity Error
TUE Total Unadjusted Error After Auto-Cal (Note 12)
±
Resolution with No Missing Codes After Auto-Cal (Note 12) 13 Bits (max)
DNL Differential Non-Linearity After Auto-Cal
Zero Error After Auto-Cal (Notes 13, 17)
LM12H458
Positive Full-Scale Error After Auto-Cal (Notes 12, 17)
±
±
LM12(H)458MEL
Negative Full-Scale Error After Auto-Cal (Notes 12, 17)
±
LM12(H)458MEL
DC Common Mode Error (Note 14)
±
ILE 8-Bit + Sign and “Watchdog” (Note 12)
Mode Positive and Negative
Integral Linearity Error
TUE 8-Bit + Sign and “Watchdog” Mode After Auto-Zero
±
Total Unadjusted Error
8-Bit + Sign and “Watchdog” Mode 9 Bits (max)
Resolution with No Missing Codes
DNL 8-Bit + Sign and “Watchdog” Mode
Differential Non-Linearity
8-Bit + Sign and “Watchdog” Mode After Auto-Zero
Zero Error
8-Bit + Sign and “Watchdog” Positive
and Negative Full-Scale Error
=
5V, V
REF+
=
25Ω, source impedance for
REF−
25˚C.
1/2
±
1 LSB (max)
1 LSB
3
±
⁄
4
LSB (max)
±
1
1/2
1/2
1/2
2
1/2
±
1.5 LSB (max)
±
2 LSB (max)
±
2.5
±
2 LSB (max)
±
2.5
±
3.5 LSB (max)
±
1/2 LSB (max)
±
3/4 LSB (max)
±
3/4 LSB (max)
±
1/2 LSB (max)
±
1/2 LSB (max)
≤ 85˚C
A
≤ 125˚C
≤ VA+
≤ VA+
≤ VA+
−1V
≤ VA+
=
0V,
+
A
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Converter Characteristics (Notes 6, 7, 8, 9, 19) (Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V, V
12-bit + sign conversion mode, f
and V
V
REF+
otherwise specified. Boldface limits apply for T
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
REF−
=
8.0 MHz (LM12H458) or f
CLK
A
=
5.0 MHz (LM12454/8), R
CLK
=
=
to T
T
T
J
MIN
; all other limits T
MAX
S
=
=
T
A
J
Symbol Parameter Conditions Typical Limits Unit
(Note 10) (Note 11) (Limit)
8-Bit + Sign and “Watchdog” Mode
±
DC Common Mode Error
Multiplexer Channel-to-Channel
±
0.05 LSB
Matching
V
IN+
V
IN−
V
IN+−VIN−
Non-Inverting Input Range GND V (min)
Inverting Input Range GND V (min)
Differential Input Voltage Range −V
Common Mode Input Voltage Range GND V (min)
PSS Power Supply Zero Error V
Sensitivity Full-Scale Error V
(Note 15) Linearity Error
C
REF
C
IN
V
REF+/VREF−
Input Capacitance 85 pF
Selected Multiplexer Channel Input 75 pF
+=VD+=5V±10
A
=
4.5V, V
REF+
REF−
%
=
GND
±
±
±
Capacitance
=
5V, V
REF+
=
25Ω, source impedance for
REF−
25˚C.
1/8 LSB
V
+ V (max)
A
V
+ V (max)
A
+
A
V
+ V (max)
A
V
+ V (max)
A
0.2
0.4
±
1.75 LSB (max)
±
2 LSB (max)
0.2 LSB
=
0V,
V (min)
Converter AC Characteristics (Notes 6, 7, 8, 9, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V, V
12-bit + sign conversion mode, f
and V
V
REF+
otherwise specified. Boldface limits apply for T
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
REF−
=
8.0 MHz (LM12H458) or f
CLK
A
=
5.0 MHz (LM12454/8), R
CLK
=
=
to T
T
T
J
MIN
; all other limits T
MAX
S
=
=
T
A
J
=
5V, V
REF+
=
25Ω, source impedance for
25˚C.
Symbol Parameter Conditions Typical Limits Unit
(Note 10) (Note 11) (Limit)
Clock Duty Cycle 50
40
60
t
C
Conversion Time 13-Bit Resolution, 44 (t
Sequencer State S5 (
Figure 15
)
9-Bit Resolution, 21 (t
Sequencer State S5 (
t
A
Acquisition Time Sequencer State S7 (
Figure 15
Figure 15
)
)9(t
) 44 (t
CLK
) 21 (t
CLK
) 9(t
CLK
)+50ns (max)
CLK
)+50ns (max)
CLK
)+50ns (max)
CLK
Built-in minimum for 13-Bits
Built-in minimum for 9-Bits and 2 (t
) 2(t
CLK
)+50ns (max)
CLK
“Watchdog” mode
t
Z
t
CAL
Auto-Zero Time Sequencer State S2 (
Full Calibration Time Sequencer State S2 (
Figure 15
Figure 15
)76(t
) 4944 (t
CLK
CLK
) 76 (t
) 4944 (t
)+50ns (max)
CLK
)+50ns (max)
CLK
Throughput Rate 89 88 kHz
(Note 18) LM12H458 142 140 (min)
t
WD
“Watchdog” Mode Comparison Sequencer States S6, S4, 11 (t
Time and S5 (
Figure 15
)
) 11 (t
CLK
)+50ns (max)
CLK
REF−
=
0V,
%
(max)
%
(min)
%
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Converter AC Characteristics (Notes 6, 7, 8, 9, 19) (Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V, V
12-bit + sign conversion mode, f
and V
V
REF+
otherwise specified. Boldface limits apply for T
≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
REF−
=
8.0 MHz (LM12H458) or f
CLK
A
=
5.0 MHz (LM12454/8), R
CLK
=
=
to T
T
T
J
MIN
; all other limits T
MAX
S
=
=
T
A
J
=
5V, V
REF+
=
25Ω, source impedance for
25˚C.
Symbol Parameter Conditions Typical Limits Unit
(Note 10) (Note 11) (Limit)
=
±
DSNR Differential Signal-to-Noise Ratio V
SESNR Single-Ended Signal-to-Noise V
Ratio f
DSINAD Differential Signal-to-Noise + V
Distortion Ratio f
SESINAD Single-Ended Signal-to-Noise + V
Distortion Ratio f
DTHD Differential Total Harmonic V
Distortion f
SETHD Single-Ended Total Harmonic V
Distortion f
DENOB Differential Effective Number V
of Bits f
SEENOB Single-Ended Effective Number V
of Bits f
DSFDR Differential Spurious Free V
Dynamic Range f
Multiplexer Channel-to-Channel V
Crosstalk f
5V
IN
=
f
1 kHz 77.5 dB
IN
=
f
20 kHz 75.2 dB
IN
=
f
40 kHz 74.7 dB
IN
=
5V
IN
p-p
=
1 kHz 69.8 dB
IN
=
f
20 kHz 69.2 dB
IN
=
f
40 kHz 66.6 dB
IN
=
±
5V
IN
=
1 kHz 76.9 dB
IN
=
f
20 kHz 73.9 dB
IN
=
f
40 kHz 70.7 dB
IN
=
5V
IN
p-p
=
1 kHz 69.4 dB
IN
=
f
20 kHz 68.3 dB
IN
=
f
40 kHz 65.7 dB
IN
=
±
5V
IN
=
1 kHz −85.8 dB
IN
=
f
20 kHz −79.9 dB
IN
=
f
40 kHz −72.9 dB
IN
=
5V
IN
p-p
=
1 kHz −80.3 dB
IN
=
f
20 kHz −75.6 dB
IN
=
f
40 kHz −72.8 dB
IN
=
±
5V
IN
=
1 kHz 12.6 Bits
IN
=
f
20 kHz 12.2 Bits
IN
=
f
40 kHz 12.1 Bits
IN
=
5V
IN
p-p
=
1 kHz 11.3 Bits
IN
=
f
20 kHz 11.2 Bits
IN
=
f
40 kHz 10.8 Bits
IN
=
±
5V
IN
=
1 kHz 87.2 dB
IN
=
f
20 kHz 78.9 dB
IN
=
f
40 kHz 72.8 dB
IN
=
5V
IN
PP
=
40 kHz
IN
LM12454 MUXOUT Only −76 dB
LM12(H)458 MUX −78 dB
plus Converter
t
PU
t
WU
Power-Up Time 10 ms
Wake-Up Time 10 ms
REF−
=
0V,
www.national.com 6
DC Characteristics (Notes 6, 7, 8, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V, V
=
f
8.0 MHz (LM12H454/8) or f
CLK
face limits apply for T
=
T
A
J
=
5.0 MHz (LM12458), and minimum acquisition time unless otherwise specified. Bold-
CLK
=
to T
T
MIN
; all other limits T
MAX
=
=
T
25˚C.
A
J
REF+
=
5V, V
Symbol Parameter Conditions Typical Limits Unit
(Note 10) (Note 11) (Limit)
+VD+ Supply Current CS=“1”
I
D
LM12454/8 0.55 1.0 mA (max)
LM12H458 0.55 1.2
I
+V
A
+ Supply Current CS=“1”
A
LM12454/8 3.1 5.0 mA (max)
LM12H458 3.1 5.5
I
ST
Stand-By Supply Current (ID++IA+) Power-Down Mode Selected
Clock Stopped 10 µA (max)
8 MHz Clock 40 µA (max)
Multiplexer ON-Channel Leakage Current V
+=5.5V
A
ON-Channel=5.5V 0.3
OFF-Channel=0V 0.1 µA (max)
LM12(H)458MEL 0.5
ON-Channel=0V 0.3
OFF-Channel=5.5V 0.1 µA (max)
LM12(H)458MEL 0.5
Multiplexer OFF-Channel Leakage Current V
+=5.5V
A
ON-Channel=5.5V 0.3
OFF-Channel=0V 0.1 µA (max)
LM12(H)458MEL 0.5
ON-Channel=0V 0.3
OFF-Channel=5.5V 0.1 µA (max)
LM12(H)458MEL 0.5
R
Multiplexer ON-Resistance LM12454
ON
=
V
5V 800 1500 Ω(max)
IN
=
V
2.5V 850 1500 Ω(max)
IN
=
V
0V 760 1500 Ω(max)
IN
Multiplexer Channel-to-Channel LM12454
R
matching V
ON
=
5V
IN
=
V
2.5V
IN
=
V
0V
IN
±
1.0
±
1.0
±
1.0
±
%
%
%
%
3.0
±
%
3.0
±
%
3.0
REF−
=
0V,
(max)
(max)
(max)
Internal Reference Characteristics (Notes 6, 7, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V unless otherwise specified.
Boldface limits apply for T
Symbol Parameter Conditions Typical Limits Unit
V
REFOUT
∆V
Internal Reference Output Voltage 2.5 2.5±4
/∆T Internal Reference Temperature 40 ppm/˚C
REF
Coefficient
∆
/∆ILInternal Reference Load Regulation Sourcing (0<IL≤ +4 mA) 0.2
REF
∆V
I
∆V
SC
Line Regulation 4.5V ≤ VA+ ≤ 5.5V 3 20 mV (max)
REF
Internal Reference Short Circuit Current V
/∆t Long Term Stability 200 ppm/kHr
REF
=
=
to T
T
A
T
J
MIN
; all other limits T
MAX
=
=
T
A
25˚C.
J
(Note 10) (Note 11) (Limit)
%
V (max)
±
LM12(H)458MEL 2.5
Sinking (−1 ≤ I
REFOUT
<
0 mA) 1.2
IL
=
0V 13 25 mA (max)
%
6
%
/mA (max)
%
/mA (max)
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Internal Reference Characteristics (Notes 6, 7, 19) (Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V unless otherwise specified.
Boldface limits apply for T
Symbol Parameter Conditions Typical Limits Unit
t
SU
Internal Reference Start-Up Time VA+=VD+=0V→5V 10 ms
=
=
to T
T
A
T
J
MIN
; all other limits T
MAX
=
=
T
25˚C.
A
J
(Note 10) (Note 11) (Limit)
=
C
100 µF
L
Digital Characteristics (Notes 6, 7, 8, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V, unless otherwise specified. Boldface limits apply for T
Symbol Parameter Conditions Typical Limits Unit
V
V
I
IN(1)
I
IN(0)
C
V
V
I
OUT
IN(1)
IN(0)
IN
OUT(1)
OUT(0)
Logical “1” Input Voltage VA+=VD+=5.5V 2.0 V (min)
Logical “0” Input Voltage VA+=VD+=4.5V 0.8 V (max)
Logical “1” Input Current V
Logical “0” Input Current V
D0–D15 Input Capacitance 6 pF
Logical “1” Output Voltage VA+=VD+=4.5V
Logical “0” Output Voltage VA+=VD+=4.5V 0.4 V (max)
TRI-STATE®Output Leakage Current V
=
=
to T
T
T
A
J
MIN
; all other limits T
MAX
=
=
T
25˚C.
A
J
(Note 10) (Note 11) (Limit)
=
5V 0.005 1.0 µA (max)
IN
LM12(H)458MEL 2.0
=
0V −0.005 −1.0 µA (max)
IN
LM12(H)458MEL −2.0
=
I
−360 µA 2.4 V (min)
OUT
=
I
−10 µA 4.25 V (min)
OUT
=
I
1.6 mA
OUT
=
0V −0.01 −3.0 µA (max)
OUT
=
V
5V 0.01 3.0 µA (max)
OUT
Digital Timing Characteristics (Notes 6, 7, 8, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V, t
100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for T
other limits T
Figures 8, 9, 10
(See
www.national.com 8
=
=
T
25˚C.
A
J
Symbol Parameter Conditions Typical Limits Unit
) (Note 10) (Note 11) (Limit)
1, 3 CS or Address Valid to ALE Low
Set-Up Time
2, 4 CS or Address Valid to ALE Low
Hold Time
5 ALE Pulse Width 45 ns (min)
6 RD High to Next ALE High
7 ALE Low to RD Low
8 RD Pulse Width
9 RD High to Next RD or WR Low
10 ALE Low to WR Low
11 WR Pulse Width
12 WR High to Next ALE High
13 WR High to Next RD or WR Low
14 Data Valid to WR High Set-Up Time
15 Data Valid to WR High Hold Time
16 RD Low to Data Bus Out of TRI-STATE
=
r
A
t
f
=
T
=
3 ns, and C
=
T
J
MIN
to T
MAX
=
L
; all
40 ns (min)
20 ns (min)
35 ns (min)
20 ns (min)
100 ns (min)
100 ns (min)
20 ns (min)
60 ns (min)
75 ns (min)
140 ns (min)
40 ns (min)
30 ns (min)
40 10 ns (min)
70 ns (max)
Digital Timing Characteristics (Notes 6, 7, 8, 19) (Continued)
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+=VD+=5V, t
100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for T
other limits T
=
=
T
25˚C.
A
J
r
A
t
f
=
T
=
3 ns, and C
=
T
J
MIN
Symbol Parameter Conditions Typical Limits Unit
Figures 8, 9, 10
(See
17 RD High to TRI-STATE
) (Note 10) (Note 11) (Limit)
=
R
1kΩ 30 10 ns (min)
L
110 ns (max)
18 RD Low to Data Valid (Access Time)
30 10 ns (min)
80 ns (max)
20 Address Valid or CS Low to RD Low
21 Address Valid or CS Low to WR Low
20 ns (min)
20 ns (min)
19 Address Invalid 10 ns (min)
from RD or WR High
22 INT High from RD Low 30 10 ns (min)
60 ns (max)
23 DMARQ Low from RD Low
30 10 ns (min)
60 ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
to ambient thermal resistance), and T
ber given in the Absolute Maximum Ratings, whichever is lower. For this device, T
LM12(H)458 in the V package, when board mounted, is 47˚C/W, in the W package, when board mounted, is 50˚C/W (θJ
board mounted, is 70˚C/W (θJ
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above V
will not damage the LM12454 or the LM12(H)458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV.As an
example, if V
+ is 4.5 VDC, full-scale input voltage must be ≤4.6 VDCto ensure accurate conversions.
A
) at any pin exceeds the power supply rails (V
IN
(ambient temperature). The maximum allowable power dissipation at any temperature is PD
A
=
3.5˚C/W).
C
<
IN
Jmax
>
GND or V
(VA+orVD+)), the current at that pin should be limited to 5 mA.
IN
(maximum junction temperature), θJA(package junction
Jmax
=
150˚C, and the typical thermal resistance (θ
=
(T
max
Jmax−TA
) of the LM12454 and
=
5.8˚C/W), and in the EL package, when
C
JA
+ or 5V below GND
A
=
L
to T
MAX
)/θJAor the num-
; all
DS011264-3
+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V+pin to assure conversion/
Note 7: V
A
comparison accuracy.
Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between −1 to 0 and 0 to +1 (see
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V.The measured value is referred to the resulting out-
put value when the inputs are driven with a 2.5V signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with V
Note 16: V
(Reference Voltage Common Mode Range) is defined as (V
REFCM
REF(VREF+−VREF−
=
25˚C and represent most likely parametric norm.
A
Figure 8
).
=
5 MHz for the LM12454/8 and f
CLK
) given as +5V, the 12-bit LSB is 1.22 mV and the 8-bit/“Watchdog” LSB is 19.53 mV.
REF++VREF−
=
8 MHz for the LM12H458.
CLK
)/2.
Figure 6 Figure 7
+ and VD+ at the specified extremes.
A
).
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Digital Timing Characteristics (Notes 6, 7, 8, 19) (Continued)
Note 17: The LM12(H)454/8’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result
in a repeatability uncertainty of
Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
clock cycles) are used (see
version. The Throughput Rate is f
Note 19: A military RETS specification is available upon request.
±
0.10 LSB.
Figure 15
). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per con-
(MHz)/N, where N is the number of clock cycles/conversion.
CLK
Electrical Characteristics
=
V
V
REF
REF+−VREF−
=
V
V
IN
IN+−VIN−
GND ≤ V
GND ≤ V
IN+≤VA
IN−≤VA
+
+
FIGURE 1. The General Case of Output Digital Code vs the Operating Input Voltage Range
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DS011264-22
Electrical Characteristics (Continued)
=
V
IN+−VIN−
IN+≤VA
IN−≤VA
=
+
+
4.096V
V
REF+−VREF−
V
IN
GND ≤ V
GND ≤ V
FIGURE 2. Specific Case of Output Digital Code vs the Operating Input Voltage Range for V
DS011264-23
REF
=
4.096V
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Electrical Characteristics (Continued)
V
REF
=
V
REF+−VREF−
FIGURE 3. The General Case of the V
Operating Range
REF
DS011264-24
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Electrical Characteristics (Continued)
=
V
REF
VA+=5V
V
REF+−VREF−
FIGURE 4. The Specific Case of the V
FIGURE 5. Transfer Characteristic
Operating Range for VA+=5V
REF
DS011264-25
DS011264-4
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