NSC LM1238AAD-NA Datasheet

LM1238 110 MHz I

C Compatible RGB Preamplifier with Internal

Simple OSD Generator and 4 DACs

General Description

The LM1238 pre-amp is an integrated, three channel video pre-amp. It has an I2C compatible interface which allows control of all the parameters necessary to directly setup and adjust the gain and contrast in the CRT display. Four I2C compatible DACs are available to control monitor bias and brightness circuits. The LM1238 preamp is designed to be 100% compatible with the LM246x high gain driver family and the LM2479/80 Clamp ICs.

Black level clamping of the video signal is carried out directly on the AC coupled input signal into the high impedance pre-amplifier inputs, eliminating the need for additional clamp capacitors. Horizontal and vertical blanking of the outputs is provided. Vertical blanking is optional and its duration is register programmable.

Features

n I2C compatible microcontroller interface n Internal OSD generator with 16 sets of color icons

n OSD override allows OSD messages to be displayed

while blanking input video

n Internally generated burn-in screen n 4 DAC outputs (8-bit resolution) for bus controlled CRT

bias and brightness

n Spot killer which blanks the video outputs when V

falls below the specified threshold

n Suitable for use with discrete or integrated clamp, with

software configurable brightness mixer

n H and V blanking (V blanking is optional and has

n Power Saving Mode with 65% power reduction n Matched to LM246x driver and 2479/80 clamp

Applications

n Low end 15" and 17" bus controlled monitors with OSD n 1024x768 displays up to 85 Hz requiring OSD capability n Very low cost systems with LM246x driver

Block and Connection Diagram

20038701

FIGURE 1. Order Number LM1238AAC/NA

See NS Package Number N24D

June 2003

LM1238 110 MHz I

C Compatible RGB Preamplifier with Internal Simple OSD Generator 4 DACs

Absolute Maximum Ratings (Notes 1, 3)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage, Pins 15 and 19 6.0V

Peak Video DC Output Source Current

(Any One Amp) Pins 18, 19 or 20 1.5 mA

Voltage at Any Input Pin (V

+0.5>V

−0.5V

Thermal Resistance to Ambient (θ

) 51˚C/W

Power Dissipation (P

) (Above 25˚C Derate Based on θ

and TJ) 2.4W

Thermal Resistance to case (θ

) 32˚C/W

Junction Temperature (T

) 150˚C

ESD Susceptibility (Note 4) 3.5 kV

Video Inputs 0.0V

1.2V

ESD Machine Model (Note 13) 350V

Storage Temperature −65˚C to +150˚C

Lead Temperature (Soldering, 10 sec.) 265˚C

Operating Ratings (Note 2)

Ambient Temperature Range

0˚C to +70˚C

Supply Voltage V

4.75V<V

5.25V

Video Inputs 0

Vin≤ 1.0 V

P-P

Video Signal Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.70 V

P-P,VABL=VCC,CL

= 8 pF, Video Outputs = 2.0 V

P-P

. Setting

numbers refer to the definitions in Table 1. See Note 7 for Min and Max parameters and Note 6 for Typicals.

Symbol Parameter Conditions Min Typ Max Units

Supply Current Test Setting 1, both supplies, no

output loading. See Note 8.

190 245 mA

S-PS

Supply Current, Power Save Mode Test Setting 1, both supplies, no

output loading. See Note 8.

60 82 mA

O BLK

Active Video Black Level Output Voltage

Test Setting 4, no AC input signal, DC offset (register 0x8438 set to 0xd5).

1.2 VDC

O BLK STEP

Active Video Black Level Step Size Test Setting 4, no AC input signal. 100 mVDC

Max Maximum Video Output Voltage Test Setting 3, Video in = 0.70 V

P-P

3.9 4.3 V

LE Linearity Error Test Setting 4, staircase input

signal (see Note 9).

Video Rise Time Note 5, 10% to 90%, Test Setting

4, AC input signal.

3.7 ns

Rising Edge Overshoot Note 5, Test Setting 4, AC input

signal.

Video Fall Time Note 5, 90% to 10%, Test Setting

4, AC input signal.

3.5 ns

Falling Edge Overshoot Note 5, Test Setting 4, AC input

signal.

BW Channel bandwidth (−3 dB) Note 5, Test Setting 4, AC input

signal.

110 MHz

SEP

10 kHz Video Amplifier 10 kHz Isolation Note 14, Test Setting 8. −60 dB

SEP

10 MHz Video Amplifier 10 MHz Isolation Note 14, Test Setting 8. −50 dB

Max Maximum Voltage Gain Test Setting 8, AC input signal. 3.8 4.2 V/V

C-50% Contrast Attenuation@50% Test Setting 5, AC input signal. −5.2 dB

Min/AVMax Maximum Contrast Attenuation indBTest Setting 2, AC input signal.

−20 dB

G-50% Gain Attenuation@50% Test Setting 6, AC input signal. −4.2 dB

G-Min Maximum Gain Attenuation Test Setting 7, AC input signal. −12 dB

Match Maximum Gain Match between

channels

Test Setting 3, AC input signal.

0.5 dB

LM1238

www.national.com 2

Video Signal Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.70 V

P-P,VABL=VCC,CL

= 8 pF, Video Outputs = 2.0 V

P-P

. Setting

numbers refer to the definitions in Table 1. See Note 7 for Min and Max parameters and Note 6 for Typicals.

Symbol Parameter Conditions Min Typ Max Units

Track Gain Change between channels Tracking when changing from Test

Setting 8 to Test Setting 5. See Note 11.

0.5 dB

ABL

TH ABL Control Range upper limit Note 12, Test Setting 4, AC input

signal.

4.8 V

ABL

Range ABL Gain Reduction Range Note 12, Test Setting 4, AC input

signal.

2.8 V

V 3.25/AV Max

ABL Gain Reduction at 3.25V Note 12, Test Setting 4, AC input

signal. V

ABL

= 3.25V

−3 dB

ABL

Active ABL Input bias current during ABL Note 12, Test Setting 4, AC input

signal. V

ABL=VABL

MIN GAIN

10 µA

ABL

Max ABL input current sink capability Note 12, Test Setting 4, AC input

signal.

1.0 mA

ABL

Max Maximum ABL Input voltage during

clamping

Note 12, Test Setting 4, AC input signal. I

ABL=IABL

MAX

0.1

Minimum Input resistance pins 5, 6,7.Test Setting 4.

20 MΩ

OSD Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V. See Note 7 for Min and Max parameters and Note 6 for Typicals.

Symbol Parameter Conditions Min Typ Max Units

OSDHIGH

max Maximum OSD Level with OSD

Contrast 11

Palette Set at 111, OSD Contrast = 11, Test Setting 3

4.3 V

OSDHIGH

10 Maximum OSD Level with OSD

Contrast 10

Palette Set at 111, OSD Contrast = 10, Test Setting 3

3.8 V

OSDHIGH

01 Maximum OSD Level with OSD

Contrast 01

Palette Set at 111, OSD Contrast = 01, Test Setting 3

3.0 V

OSDHIGH

00 Maximum OSD Level with OSD

Contrast 00

Palette Set at 111, OSD Contrast = 00, Test Setting 3

2.3 V

∆V

OSD

(Black) Difference between OSD Black

Level and Video Black Level (same channel)

20 mV

∆V

OSD

(White) Output Match between Channels Palette Set at 111, OSD Contrast =

11, Maximum difference between R, G and B

OSD-out

(Track) Output Variation between Channels OSD contrast varied from max to

min

DAC Output Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

= 8 pF, Video Outputs = 2.0 V

P-P

. See Note 7

for Min and Max parameters and Note 6 for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

Min DAC

Min output voltage of DAC Register Value = 0x00 0.5 0.7 V

Max DAC

Mode 00

Max output voltage of DAC Register Value = 0xFF,

DCF[1:0] = 00b

3.5 4.2 V

Max DAC

Mode 01

Max output voltage of DAC in DCF mode 01

1.85 2.35 V

∆V

Max DAC

(Temp)

Variation in voltage of DAC with temperature

<T<

70˚C ambient

0.5 mV/˚C

LM1238

www.national.com3

DAC Output Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

= 8 pF, Video Outputs = 2.0 V

P-P

. See Note 7

for Min and Max parameters and Note 6 for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

∆V

Max DAC(VCC

) Variation in voltage of DAC with

4.75<V

5.25V

50 mV/V

Linearity Linearity of DAC over its range 5 %

Monotonicity Monotonicity of the DAC Excluding dead zones

0.5 LSB

MAX

Max Load Current −1.0 1.0 mA

System Interface Signal Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

= 8 pF, Video Outputs = 2.0 V

P-P

. See Note 7

for Min and Max parameters and Note 6 for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

VTH+

VFLYBACK positive switching guarantee.

Vertical Blanking triggered

2.0 V

SPOT

Spot Killer Voltage Note 17, VCCAdjusted to Activate 3.4 3.9 4.3 V

Ref

Output Voltage 1.25 1.45 1.65 V

(SCL, SDA) Logic Low Input Voltage −0.5 1.5 V

(SCL, SDA) Logic High Input Voltage

3.0

VCC+

0.5

(SCL, SDA) Logic Low Input Current SDA or SCL, Input Voltage = 0.4V

10 µA

(SCL, SDA) Logic High Input Voltage SDA or SCL, Input Voltage = 4.5V

10 µA

(SCL, SDA) Logic Low Output Voltage IO= 3 mA 0.5 V

Min Minimum Horizontal Frequency PLL & OSD Operational; PLL

Range = 0

25 kHz

Max Maximum Horizontal Frequency PLL & OSD Operational; PLL

Range = 3

100 110 kHz

HFB IN

Max Horizontal Flyback Input Current Absolute Maximum During Flyback 5 mA

Peak Current during flyback Design Value 4 mA

HFB OUT

Max Horizontal Flyback Input Current Absolute Maximum During Scan −700 µA

OUT

Peak Current during Scan Design Value −550 µA

IN THRESHOLD

IINH-Blank Detection Threshold 0 µA

H-BLANK ON

H-Blank Time Delay - On + Zero crossing of I

HFB

to 50% of

output blanking start. I

= +1.5mA

45 ns

H-BLANK OFF

H-Blank Time Delay - Off − Zero crossing of I

HFB

to 50% of

output blanking end. I

= −100µA

85 ns

BLANK

Max Maximum Video Blanking Level Test Setting 4, AC input signal. 0 0.25 V

FREERUN

Free Run H Frequency, including H Blank

42 kHz

PW CLAMP

Minimum Clamp Pulse Width See Note 15 200 ns

CLAMP MAX

Maximum Low Level Clamp Pulse Voltage

Video Clamp Functioning

2.0 V

CLAMP MIN

Minimum High Level Clamp Pulse Voltage

Video Clamp Functioning

3.0 V

CLAMP

Low Clamp Gate Low Input Current V23= 2V −0.4 µA

CLAMP

High Clamp Gate High Input Current V23= 3V 0.4 µA

CLAMP-VIDEO

Time from End of Clamp Pulse to Start of Video

Referenced to Blue, Red and Green inputs

50 ns

Note 1: Limits of Absolute Maximum Ratings indicate below which damage to the device must not occur.

Note 2: Limits of operating ratings indicate required boundaries of conditions for which the device is functional, but may not meet specific performance limits.

Note 3: All voltages are measured with respect to GND, unless otherwise specified.

Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

LM1238

www.national.com 4

System Interface Signal Characteristics (Continued)

Note 5: Input from signal generator: tr,t

1 ns.

Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.

Note 7: Tested limits are guaranteed to National’s AOQL; (Average Outgoing Quality Level).

Note 8: The supply current specified is the quiescent current for V

and 5V Dig with RL=∞. Load resistors are not required and are not used in the test circuit,

therefore all the supply current is used by the pre-amp.

Note 9: Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 V

P-P

level at the input. All 16 steps equal,

with each at least 100 ns in duration.

Note 10: dt/dV

= 200*(t5.5V–t4.5V)/ ((t5.5V + t4.5V)) %/V, where:

t5.5V is the rise or fall time at V

= 5.5V, and t4.5V is the rise or fall time at VCC= 4.5V.

Note 11: ∆A

track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in

gain change between any two amplifiers with the contrast set to A

C−50% and measured relative to the AVmax condition. For example, at AVmax the three

amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to A

C−50%. This yields a typical

gain change of 10.0 dB with a tracking change of

0.2 dB.

Note 12: ABL should provide smooth decrease in gain over the operational range of 0 dB to −5 dB

∆A

ABL

= A(V

ABL=VABL MAX GAIN

)–A(V

ABL=VABL MIN GAIN

)

Beyond −5 dB the gain characteristics, linearity and pulse response may depart from normal values.

Note 13: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).

Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at f

= 10 MHz for V

SEP 10 MHZ

Note 15: A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer clamp pulse may be required.

Note 16: Adjust input frequency from 10 MHz (A

max reference level) to the −3 dB corner frequency (f

−3 dB

Note 17: Once the spot killer has been activated, the LM1238 remains in the off state until V

is cycled (reduced below 0.5V and then restored to 5V).

Hexadecimal and Binary Notation

Hexadecimal numbers appear frequently throughout this document, representing slave and register addresses, and register values. These appear in the format “0x...”. For example, the slave address for writing the registers of the LM1238 is hexadecimal BA, written as 0xBA. On the other hand, binary values, where the individual bit values are shown, are indicated by a trailing “b”. For example, 0xBA is equal to 10111010b. A subset of bits within a register is referred to by the bit numbers in brackets following the

register value. For example, the OSD contrast bits are the fourth and fifth bits of register 0x0818. Since the first bit is bit 0, the OSD contrast register is 0x0818[4:3].

Table 1 shows the definitions of the Test Settings 1–8 referred to in the specifications sections. Each test setting is a combination of five hexadecimal register values, Contrast, Gain (Blue, Red, Green) and DC offset.

TABLE 1. Test Setting Definitions

Control No. of Bits

Test Settings

1234 5678

Contrast 7 0x7F

(Max)

0x00

Min

0x7F

(Max)

0x7F

(Max)

0x40

(50.4%)

0x7F

(Max)

0x7F

(Max)

0x7F

(Max)

B, R, G

Gain

7 0x7F

(Max)

0x7F

(Max)

0x7F

(Max)

Set V

P-P

0x7F

(Max)

0x40

(50%)

0x00 (Min)

0x7F

(Max)

DC Offset 3 0x00

(Min)

0x05 0x07

(Max)

0x05 0x05 0x05 0x05 0x05

LM1238

www.national.com5

Typical Performance Characteristics

VCC= 5V, TA= 25˚C unless otherwise specified

SYSTEM INTERFACE SIGNALS

The Horizontal and Vertical Blanking and the Clamping input signals are important for proper functionality of the LM1238. Both blanking inputs must be present for OSD synchronization. In addition, the Horizontal blanking input also assists in setting the proper cathode black level, along with the Clamping pulse. The Vertical blanking input initiates a blanking level at the LM1238 outputs which is programmable from 3 to 127 lines (we recommend at least 10). This can be optionally disabled so there is no vertical blanking.

20038754

FIGURE 2. Logic Horizontal Blanking

20038755

FIGURE 3. Logic Vertical Blanking

20038756

FIGURE 4. Deflection Horizonal Blanking

20038757

FIGURE 5. Deflection Vertical Blanking

20038758

FIGURE 6. Logic Clamp Pulse

LM1238

www.national.com 6

Typical Performance Characteristics

VCC= 5V, TA= 25˚C unless

otherwise specified (Continued)

Figure 2 and Figure 3 show the case where the Horizontal and Vertical inputs are logic levels. Figure 2 shows the smaller pin 24 voltage superimposed on the horizontal blanking pulse input to the neck board with R

= 4.7K and

= 0.1µF. Note where the voltage at pin 24 is clamped to

about 1 volt when the pin is sinking current. Figure 3 shows the smaller pin 1 voltage superimposed on the vertical blanking input to the neck board with C

jumpered and RV= 4.7K.

Figure 4 and Figure 5 show the case where the horizontal and vertical inputs are from deflection. Figure 4 shows the pin 24 voltage which is derived from a horizontal flyback pulse of 35 volts peak to peak with R

= 8.2K and C

jumpered. Figure 5 shows the pin 1 voltage which is derived from a vertical flyback pulse of 55 volts peak to peak with C

= 1500pF and RV= 120K.

Figure 6 shows the pin 23 clamp input voltage superimposed on the neck board clamp logic input pulse. R

= 1K and should be chosen to limit the pin 23 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9.

CATHODE RESPONSE

Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video risetime is

1.5 nanoseconds. The resulting leading edge has a 10.1 nanosecond risetime and a 8% overshoot, while the trailing edge has a 8.3 nanosecond risetime and a 2% overshoot with an LM2469 driver.

ABL GAIN REDUCTION

The ABL function reduces the contrast level of the LM1238 as the voltage on pin 22 is lowered from V

to around 2 volts. Figure 8 shows the amount of gain reduction as the voltage is lowered from V

(5.0V) to 2V. The gain reduction

is small until V

reaches the knee anound 3.7V, where the slope increases. Many system designs will require about 3 to 5 dB of gain reduction in full beam limiting. Additional attenuation is possible, and can be used in special circumstances. However, in this case, video performance such as video linearity and tracking between channels will tend to depart from normal specifications.

OSD PHASE LOCKED LOOP

Table 2 shows the recommended horizontal scan rate ranges (in kHz) for each combination of PLL register setting, 0x081E [1:0], and the pixels per line register setting, 0x0802 [7:6]. While the OSD PLL may lock for other combinations, the performance of the loop will be improved if these recommendations are followed. NR means the combination of PLL and PPL is not recommended for any scan rate.

TABLE 2. OSD Register Recommendations

Pixels per Line

PLL Range 130 176 240 352

1 30-45 30-41 30-40 30-41

2 45-89 41-82 40-79 41-82

3 89-100 82-100 79-100 82-100

20038759

FIGURE 7. Red Cathode Response

20038760

FIGURE 8. ABL Gain Reduction Curve

LM1238

www.national.com7

Pin Descriptions and Application Information

No.

Pin Name Schematic Description

1 V Flyback

Required for OSD synchronization and is also used for vertical blanking of the video outputs. The actual switching threshold is about 35% of V

. For logic level inputs C4can be a jumper, but for flyback inputs, an AC coupled differentiator is recommended, where R

is large enough to prevent the voltage at pin 1 from exceeding V

or going below GND. C4should be small enough to flatten the vertical rate ramp at pin 1. C

may be needed to reduce noise.

REF

Bypass Provides filtering for the internal voltage which

sets the internal bias current in conjunction with R

EXT

. A minimum of 0.1 µF is recommended for proper filtering. This capacitor should be placed as close to pin 2 and the pin 4 ground return as possible.

REF

Current Set External resistor, 10k 1%, sets the internal bias

current level for optimum performance of the LM1238. This resistor should be placed as close to pin 3 and the pin 4 ground return as possible.

4 Analog Ground

This is the ground for the analog portions of the LM1238 internal circuitry.

5 6 7

Blue Video In

Red Video In

Green Video In

These video inputs must be AC coupled with a .0047 µF cap. Internal DC restoration is done at these inputs. A series resistor of about 33Ω and external ESD protection diodes should also be used for protection from ESD damage.

PLL Ground

PLL V

The ground pin should be connected to the rest of the circuit ground by a short but independent PCB trace to prevent contamination by extraneous signals. The V

pin should be

isolated from the rest of the V

line by a ferrite bead and bypassed to pin 8 with an electrolytic capacitor and a high frequency ceramic.

LM1238

www.national.com 8

+ 16 hidden pages