NSC LM1237AAF-NA Datasheet

LM1237 150 MHz I

C Compatible RGB Preamplifier with Internal

254 Character OSD and 4 DACs

General Description

The LM1237 pre-amp is an integrated CMOS CRT preamp. It has an I the parameters necessary to directly setup and adjust the gain and contrast in the CRT display. Brightness and bias can be controlled through the DAC outputs which are well matched to the LM2479 and LM2480 integrated bias clamp ICs. The LM1237 preamp is also designed to be compatible with the LM246x high gain driver family.

Black level clamping of the video signal is carried out directly on the AC coupled input signal into the high impedance preamplifier input, thus eliminating the need for additional clamp capacitors. Horizontal and vertical blanking of the outputs is provided. Vertical blanking is optional and its duration is register programmable.

The IC is packaged in an industry standard 24 lead DIP molded plastic package.

C compatible interface which allows control of all

Features

n I2C compatible microcontroller interface

n Internal 254 character OSD usable as either (a) 190

2-color plus 64 4-color characters, (b) 318 2-color characters, or (c) some combination in between.

n OSD override allows OSD messages to override video

and the use of burn-in screens with no video input

n 4 DAC outputs (8-bit resolution) for bus controlled CRT

bias and brightness

n Spot killer which blanks the video outputs when V

falls below the specified threshold

n Suitable for use with discrete or integrated clamp, with

software configurable brightness mixer

n H and V blanking (V blanking is optional and has

n Power Saving Mode with 80% power reduction n Matched to LM246x driver and LM2479/80 drivers

Applications

n Low end 15" and 17" bus controlled monitors with OSD n 1024x768 displays up to 85 Hz requiring OSD capability n Very low cost systems with LM246x driver

September 2002

LM1237 150 MHz I

C Compatible RGB Preamplifier with Internal 254 Character OSD and 4 DACs

Block and Connection Diagram

FIGURE 1. Order Number LM1237AAF/NA

See NS Package Number N24D

20023401

Absolute Maximum Ratings (Notes 1, 3)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

LM1237

Distributors for availability and specifications.

Supply Voltage, Pins 15 and 19 6.0V

Peak Video DC Output Source Current

(Any One Amp) Pins 18, 19 or 20 1.5 mA

Voltage at Any Input Pin (V

)

+0.5>V

Video Inputs (pk-pk) 0.0<V

Thermal Resistance to Ambient (θ

Power Dissipation (P

)

) 51˚C/W

−0.5V

1.2V

(Above 25˚C Derate Based

and TJ) 2.4W

on θ

Thermal Resistance to case (θ

Junction Temperature (T

) 32˚C/W

) 150˚C

ESD Susceptibility (Note 4) 3.5 kV

ESD Machine Model (Note 13) 350V

Storage Temperature −65˚C to +150˚C

Lead Temperature (Soldering, 10 sec.) 265˚C

Operating Ratings (Note 2)

Temperature Range 0˚C to +70˚C

Supply Voltage V

4.75V<V

Video Inputs (pk-pk) 0.0V

Video Signal Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.70 V

P-P,VABL=VCC,CL

numbers refer to the definitions in Table 1. See Note 7 for Min and Max parameters and Note 6 for Typicals.

Symbol Parameter Conditions Min Typ Max Units

Supply Current Test Setting 1, both supplies, no

output loading. See Note 8.

S-PS

Supply Current, Power Save Mode Test Setting 1, both supplies, no

output loading. See Note 8.

O BLK

Active Video Black Level Output Voltage

Test Setting 4, no AC input signal, DC offset (register 0x8438 set to 0xd5).

O BLK STEP

Max Maximum Video Output Voltage Test Setting 3, Video in = 0.70 V

Active Video Black Level Step Size Test Setting 4, no AC input signal. 100 mVDC

LE Linearity Error Test Setting 4, staircase input

signal (see Note 9).

Video Rise Time Note 5, 10% to 90%, Test Setting

4, AC input signal.

Rising Edge Overshoot Note 5, Test Setting 4, AC input

signal.

Video Fall Time Note 5, 90% to 10%, Test Setting

4, AC input signal.

Falling Edge Overshoot Note 5, Test Setting 4, AC input

signal.

BW Channel bandwidth (−3 dB) Note 5, Test Setting 4, AC input

signal.

10 kHz Video Amplifier 10 kHz Isolation Note 14, Test Setting 8. −60 dB

SEP

10 MHz Video Amplifier 10 MHz Isolation Note 14, Test Setting 8. −50 dB

SEP

Max Maximum Voltage Gain Test Setting 8, AC input signal. 3.8 4.2 V/V

C-50% Contrast Attenuation@50% Test Setting 5, AC input signal. −5.2 dB

Min/AVMax Maximum Contrast Attenuation indBTest Setting 2, AC input signal.

= 8 pF, Video Outputs = 2.0 V

170 225 mA

60 82 mA

1.2 VDC

4.0 4.4 V

P-P

3.1 ns

2.9 ns

150 MHz

−20 dB

. Setting

P-P

5.25V

1.0V

AVG-50% Gain Attenuation@50% Test Setting 6, AC input signal. −3.6 dB

G-Min Maximum Gain Attenuation Test Setting 7, AC input signal. −10 dB

Match Maximum Gain Match between

Test Setting 3, AC input signal.

0.5

channels

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Video Signal Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.70 V

P-P,VABL=VCC,CL

numbers refer to the definitions in Table 1. See Note 7 for Min and Max parameters and Note 6 for Typicals.

Symbol Parameter Conditions Min Typ Max Units

Track Gain Change between channels Tracking when changing from Test

Setting 8 to Test Setting 5. See Note 11.

TH ABL Control Range upper limit Note 12, Test Setting 4, AC input

ABL

signal.

Range ABL Gain Reduction Range Note 12, Test Setting 4, AC input

ABL

signal.

V 3.5/AV Max

V 2.0/AV Max

Active ABL Input bias current during ABL Note 12, Test Setting 4, AC input

ABL

Max ABL input current sink capability Note 12, Test Setting 4, AC input

ABL

ABL Gain Reduction at 3.5V Note 12, Test Setting 4, AC input

signal. V

ABL

= 3.5V

ABL Gain Reduction at 2.0V Note 12, Test Setting 4, AC input

signal. V

= 2.0V

ABL

ABL=VABL

MIN GAIN

signal.

Max Maximum ABL Input voltage during

ABL

clamping

Note 12, Test Setting 4, AC input signal. I

ABL=IABL

MAX

AVABL Track ABL Gain Tracking Error Note 9, Test Setting 4, 0.7 V

input signal, ABL voltage set to

4.5V and 2.5V.

Minimum Input resistance pins 5, 6,7.Test Setting 4.

= 8 pF, Video Outputs = 2.0 V

0.5

4.8 V

2.8 V

−3 dB

−11 dB

P-P

20 MΩ

P-P

10 µA

1.0 mA

0.1

4.5 %

. Setting

LM1237

OSD Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V. See Note 7 for Min and Max parameters and Note 6 for Typicals.

Symbol Parameter Conditions Min Typ Max Units

OSDHIGH

∆V

max Maximum OSD Level with OSD

Contrast 11

10 Maximum OSD Level with OSD

Contrast 10

01 Maximum OSD Level with OSD

Contrast 01

00 Maximum OSD Level with OSD

Contrast 00

(Black) Difference between OSD Black

OSD

Level and Video Black Level (same channel)

(White) Output Match between Channels Palette Set at 111, OSD Contrast =

OSD

Palette Set at 111, OSD Contrast = 11, Test Setting 3

Palette Set at 111, OSD Contrast = 10, Test Setting 3

Palette Set at 111, OSD Contrast = 01, Test Setting 3

Palette Set at 111, OSD Contrast = 00, Test Setting 3

11, Maximum difference between R,

3.8 V

3.1 V

2.4 V

1.7 V

20 mV

G and B

(Track) Output Variation between Channels OSD contrast varied from max to

OSD-out

min

DAC Output Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

for Min and Max parameters and Note 6 for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

Min DAC

Min output voltage of DAC Register Value = 0x00 0.5 0.7 V

= 8 pF, Video Outputs = 2.0 V

. See Note 7

P-P

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DAC Output Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

LM1237

for Min and Max parameters and Note 6 for Typicals. DAC parameters apply to all 4 DACs.

ABL=VCC,CL

Symbol Parameter Conditions Min Typ Max Units

Max DAC

Mode 00

Max DAC

Mode 01

∆V

Max DAC

(Temp)

∆V

Max DAC(VCC

Max output voltage of DAC Register Value = 0xFF,

DCF[1:0] = 00b

Max output voltage of DAC in DCF mode 01

Variation in voltage of DAC with

<T<

70˚C ambient

temperature

) Variation in voltage of DAC with

4.75<V

5.25V

Linearity Linearity of DAC over its range 5 %

Monotonicity Monotonicity of the DAC Excluding dead zones

MAX

Max Load Current −1.0 1.0 mA

= 8 pF, Video Outputs = 2.0 V

3.7 4.2 V

1.85 2.35 V

0.5 mV/˚C

50 mV/V

0.5 LSB

. See Note 7

P-P

System Interface Signal Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

for Min and Max parameters and Note 6 for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

VTH+

VFLYBACK positive switching

Vertical Blanking triggered

guarantee.

SPOT

Ref

(SCL, SDA) Logic Low Input Voltage −0.5 1.5 V

(SCL, SDA) Logic High Input Voltage

(SCL, SDA) Logic Low Input Current SDA or SCL, Input Voltage = 0.4V

(SCL, SDA) Logic High Input Voltage SDA or SCL, Input Voltage = 4.5V

(SCL, SDA) Logic Low Output Voltage IO= 3 mA 0.5 V

Min Minimum Horizontal Frequency PLL & OSD Operational; PLL

Spot Killer Voltage Note 17, VCCAdjusted to Activate 3.4 3.9 4.25 V

Output Voltage 1.25 1.45 1.65 V

Ref

Range = 0

fHMax Maximum Horizontal Frequency PLL & OSD Operational; PLL

Range = 3

Max Horizontal Flyback Input Current Absolute Maximum During Flyback 5 mA

HFB IN

HFB OUT

OUT

IN THRESHOLD

H-BLANK ON

Max Horizontal Flyback Input Current Absolute Maximum During Scan −700 µA

Peak Current during flyback Design Value 4 mA

Peak Current during Scan Design Value −550 µA

IINH-Blank Detection Threshold 0 µA

H-Blank Time Delay - On + Zero crossing of I

output blanking start. I

H-BLANK OFF

H-Blank Time Delay - Off − Zero crossing of I

output blanking end. I

Max Maximum Video Blanking Level Test Setting 4, AC input signal. 0 0.25 V

BLANK

FREERUN

Free Run H Frequency, including H Blank

PW CLAMP

CLAMP MAX

Minimum Clamp Pulse Width See Note 15 200 ns

Maximum Low Level Clamp Pulse

Video Clamp Functioning

Voltage

CLAMP MIN

Minimum High Level Clamp Pulse

Video Clamp Functioning

Voltage

Low Clamp Gate Low Input Current V23= 2V −0.4 µA

CLAMP

High Clamp Gate High Input Current V23= 3V 0.4 µA

CLAMP

= 8 pF, Video Outputs = 2.0 V

2.0 V

3.0

to 50% of

HFB

= +1.5mA

to 50% of

HFB

= −100µA

3.0 V

. See Note 7

P-P

VCC+

0.5

10 µA

25 kHz

110 kHz

45 ns

85 ns

42 kHz

2.0 V

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System Interface Signal Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

for Min and Max parameters and Note 6 for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

CLAMP-VIDEO

Time from End of Clamp Pulse to Start of Video

Note 1: Limits of Absolute Maximum Ratings indicate below which damage to the device must not occur.

Note 2: Limits of operating ratings indicate required boundaries of conditions for which the device is functional, but may not meet specific performance limits.

Note 3: All voltages are measured with respect to GND, unless otherwise specified.

Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

Note 5: Input from signal generator: t

Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.

Note 7: Tested limits are guaranteed to National’s AOQL; (Average Outgoing Quality Level).

Note 8: The supply current specified is the quiescent current for V

therefore all the supply current is used by the pre-amp.

Note 9: Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 V with each at least 100 ns in duration.

Note 10: dt/dV

t5.5V is the rise or fall time at V

Note 11: ∆A gain change between any two amplifiers with the contrast set to A amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to A gain change of 10.0 dB with a tracking change of

Note 12: ABL should provide smooth decrease in gain over the operational range of 0 dB to −5 dB

= A(V

∆A

ABL

Beyond −5 dB the gain characteristics, linearity and pulse response may depart from normal values.

Note 13: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).

Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at f

Note 15: A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer clamp pulse may be required.

Note 16: Adjust input frequency from 10 MHz (A

Note 17: Once the spot killer has been activated, the LM1237 remains in the off state until V

= 200*(t5.5V–t4.5V)/ ((t5.5V + t4.5V)) %/V, where:

track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in

ABL=VABL MAX GAIN

)–A(V

1 ns.

r,tf

= 5.5V, and t4.5V is the rise or fall time at VCC= 4.5V.

0.2 dB.

ABL=VABL MIN GAIN

= 10 MHz for V

max reference level) to the −3 dB corner frequency (f

Referenced to Blue, Red and Green inputs

and 5V Dig with RL=∞. Load resistors are not required and are not used in the test circuit,

C−50% and measured relative to the AVmax condition. For example, at AVmax the three

)

SEP 10 MHZ

= 8 pF, Video Outputs = 2.0 V

P-P

50 ns

level at the input. All 16 steps equal,

P-P

C−50%. This yields a typical

−3 dB

is cycled (reduced below 0.5V andthen restored to 5V).

. See Note 7

LM1237

Hexadecimal and Binary Notation

Hexadecimal numbers appear frequently throughout this document, representing slave and register addresses, and register values. These appear in the format “0x...”. For example, the slave address for writing the registers of the LM1237 is hexadecimal BA, written as 0xBA. On the other hand, binary values, where the individual bit values are shown, are indicated by a trailing “b”. For example, 0xBA is equal to 10111010b. A subset of bits within a register is referred to by the bit numbers in brackets following the register value. For example, the OSD contrast bits are the fourth and fifth bits of register 0x8438. Since the first bit is bit 0, the OSD contrast register is 0x8438[4:3].

Register Test Settings

Table 1 shows the definitions of the Test Settings 1–8 referred to in the specifications sections. Each test setting is a combination of five hexadecimal register values, Contrast, Gain (Blue, Red, Green) and DC offset.

TABLE 1. Test Setting Definitions

Control No. of Bits

1234 5678

Contrast 7 0x7F

(Max)

B, R, G

Gain

7 0x7F

(Max)

DC Offset 3 0x00

(Min)

0x00

Min

0x7F

(Max)

0x7F

(Max)

0x7F

(Max)

0x05 0x07

(Max)

Test Settings

0x7F

(Max)

Set V

P-P

0x40

(50.4%)

0x7F

(Max)

0x7F

(Max)

0x40

(50%)

0x7F

(Max)

0x00 (Min)

0x05 0x05 0x05 0x05 0x05

0x7F

(Max)

0x7F

(Max)

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LM1253A Compatibility

In order to maintain register compatibility with the LM1253A preamplifier datasheet assignments for bias and brightness, the color

LM1237

assignments are recommended as shown in Table 2. If datasheet compatibility is not required, then the DAC assignments can be arbitrary.

TABLE 2. LM1253A Compatibility

DAC Bias Outputs

LM1237 Pin: DAC 1 DAC 2 DAC 3 DAC 4

Assignment: Blue Green Red Brightness

OSD vs Video Intensity

The OSD amplitude has been increased over the LM1253A level. During monitor alignment, the three gain registers are used to achieve the desired front of screen color balance. This also causes the OSD channels to be adjusted accordingly, since these are inserted into the video channels prior to the gain attenuators. This provides the means to fine tune the intensity of the OSD relative to the video as follows. If a typical starting point for the alignment is to have the gains at maximum (0x7F) and the contrast at 0x55, the resultant OSD intensity will be higher than if the starting point is with the gains at 0x55 and the contrast at maximum (0x7F). This tradeoff allows fine tuning the final OSD intensity relative to the video. In addition, the OSD contrast register, 0x8438 [4:3], provides 4 major increments of intensity. Together, these allow setting the OSD intensity to the most pleasing level.

Typical Performance Characteristics V

= 5V, TA= 25˚C unless otherwise specified

System Interface Signals

The Horizontal and Vertical Blanking and the Clamping input signals are important for proper functionality of the LM1237. Both blanking inputs must be present for OSD synchronization. In addition, the Horizontal blanking input also assists in setting the proper cathode black level, along with the Clamping pulse. The Vertical blanking input initiates a blanking level at the LM1237 outputs which is programmable from 3 to 127 lines (we recommend at least 10). This can be optionally disabled so there is no vertical blanking.

20023454

20023455

FIGURE 2. Logic Horizontal Blanking

FIGURE 3. Logic Vertical Blanking

Figure 2 and Figure 3 show the case where the Horizontal and Vertical inputs are logic levels. Figure 2 shows the smaller pin 24 voltage superimposed on the horizontal blanking pulse input to the neck board with R

= 4.7K and C17= 0.1µF. Note where the

voltage at pin 24 is clamped to about 1 volt when the pin is sinking current. Figure 3 shows the smaller pin 1 voltage superimposed on the vertical blanking input to the neck board with C

jumpered and RV= 4.7K. These component values

correspond to the application circuit of Figure 15.

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LM1237

Typical Performance Characteristics V

=5V,TA= 25˚C unless otherwise specified (Continued)

Figure 4 and Figure 5 show the case where the horizontal and vertical inputs are from deflection. Figure 4 shows the pin 24 voltage which is derived from a horizontal flyback pulse of 35 volts peak to peak with R shows the pin 1 voltage which is derived from a vertical flyback pulse of 55 volts peak to peak with C

20023456

FIGURE 4. Deflection Horizonal Blanking

FIGURE 5. Deflection Vertical Blanking

= 8.2K and C17jumpered. Figure 5

= 1500pF and RV= 120K.

20023457

Figure 6 shows the pin 23 clamp input voltage superimposed on the neck board clamp logic input pulse. R

= 1K and should be

chosen to limit the pin 23 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9.

Cathode Response

Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video risetime is 1.5 nanoseconds. The resulting leading edge has a 7.1 nanosecond risetime and a 7.6% overshoot, while the trailing edge has a 7.1 nanosecond risetime and a 6.9% overshoot with an LM2467 driver.

20023458

20023459

FIGURE 6. Logic Clamp Pulse

FIGURE 7. Red Cathode Response

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Typical Performance Characteristics V

ABL Gain Reduction

LM1237

The ABL function reduces the contrast level of the LM1237 as the voltage on pin 22 is lowered from V 8 shows the amount of gain reduction as the voltage is lowered from V

= 5V, TA= 25˚C unless otherwise specified (Continued)

to around 2 volts. Figure

(5.0V) to 2V. The gain reduction is small until V

reaches the knee anound 3.7V, where the slope increases. Many system designs will require about 3 to 5 dB of gain reduction in full beam limiting. Additional attenuation is possible, and can be used in special circumstances. However, in this case, video performance such as video linearity and tracking between channels will tend to depart from normal specifications.

20023460

FIGURE 8. ABL Gain Reduction Curve

OSD Phase Locked Loop

Table 3 shows the recommended horizontal scan rate ranges (in kHz) for each combination of PLL register setting, 0x843E [1:0], and the pixels per line register setting, 0x8401 [7:5]. These ranges are recommended for chip ambient temperatures of 50

C. While the OSD PLL will lock for other register combinations and at scan rates outside these ranges, the performance of the

Cto

loop will be improved if these recommendations are followed. NR means the combination of PLL and PPL is not recommended for any scan rate.

TABLE 3. OSD Register recommendations

PPL=0 PPL=1 PPL=2 PPL=3 PPL=4 PPL=5 PPL=6 PPL=7

PLL=1 27 - 57 26 - 49 25 - 45 25 - 41 25 - 37 25 - 34 25 - 32 25 - 30

PLL=2 NR NR 45 - 89 41 - 82 37 - 75 34 - 69 32 - 64 30 - 60

PLL=3 NR NR NR 82 - 110 75 - 110 69 - 110 64 - 110 60 - 110

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Pin Descriptions and Application Information

LM1237

Pin No.

Pin Name Schematic Description

1 V Flyback

Bypass Provides filtering for the internal voltage which

REF

Current Set External resistor, 10k 1%, sets the internal bias

REF

Required for OSD synchronization and is also used for vertical blanking of the video outputs. The actual switching threshold is about 35% of

. For logic level inputs C4can be a jumper,

but for flyback inputs, an AC coupled differentiator is recommended, where R

is large

enough to prevent the voltage at pin 1 from exceeding V

or going below GND. C4should

be small enough to flatten the vertical rate ramp at pin 1. C

may be needed to reduce noise.

sets the internal bias current in conjunction with

. A minimum of 0.1 µF is recommended for

EXT

proper filtering. This capacitor should be placed as close to pin 2 and the pin 4 ground return as possible.

current level for optimum performance of the LM1237. This resistor should be placed as close to pin 3 and the pin 4 ground return as possible.

4 Analog Ground

Blue Video In

Red Video In

Green Video In

810Digital Ground

PLL V

This is the ground for the input analog portions of the LM1237 internal circuitry.

These video inputs must be AC coupled with a .0047 µF cap. Internal DC restoration is done at these inputs. A series resistor of about 33Ω and external ESD protection diodes should also be used for protection from ESD damage.

The ground pin should be connected to the rest of the circuit ground by a short but independent PCB trace to prevent contamination by extraneous signals. The V isolated from the rest of the V

pin should be

line by a ferrite

bead and bypassed to pin 8 with an electrolytic capacitor and a high frequency ceramic.

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Pin Descriptions and Application Information (Continued)

LM1237

No.

Pin Name Schematic Description

9 PLL Filter Recommended topology and values are shown

to the left. It is recommended that both filter branches be bypassed to the independent ground as close to pin 8 as possible. Great care should be taken to prevent external signals from

coupling into this filter from video, I

C, etc.

11 SDA

12 SCL

DAC 4 Output

DAC 2 Output

DAC 3 Output

DAC 1 Output

17 18

Ground

The I2C compatible data line. A pull-up resistor of about 2 Kohms should be connected between this pin and V

. A resistor of at least 100Ω

should be connected in series with the data line for additional ESD protection.

The I2C compatible clock line. A pull-up resistor of about 2 kΩ should be connected between this pin and V

. A resistor of at least 100Ω should

be connected in series with the clock line for additional ESD protection.

DAC outputs for cathode cut-off adjustments and brightness control. DAC 4 can be set to change the outputs of the other three DACs, acting as a brightness control. The DAC values and the

special DAC 4 function are set through the I

C compatible bus. A resistor of at least 100Ω should be connected in series with these outputs for additional ESD protection.

Ground pin for the output analog portion of the LM1237 circuitry, and power supply pin for both analog and digital sections of the LM1237. Note the recommended charge storage and high frequency capacitors which should be as close to pins 17 and 18 as possible.

Green Output

Red Output

Blue Output

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These are the three video output pins. They are intended to drive the LM246x family of cathode drivers. Nominally, about 2V peak to peak will produce 40V peak to peak of cathode drive.

Pin Descriptions and Application Information (Continued)

LM1237

Pin No.

Pin Name Schematic Description

22 ABL The Automatic Beam Limiter input is biased to

the desired beam current limit by R and normally keeps D

forward biased. When

INT

ABL

and V

the current resupplying the CRT capacitance (averaged by C

) exceeds this limit, then D

ABL

begins to turn off and the voltage at pin 22 begins to drop. The LM1237 then lowers the gain of the three video channels until the beam current reaches an equilibrium value.

23 CLAMP

This pin accepts either TTL or CMOS logic levels. The internal switching threshold is approximately one-half of V series resistor, R

, of about 1k is recommended

. An external

to avoid overdriving the input devices. In any event, R voltage at pin 23 from going higher than V

must be large enough to prevent the

EXT

below GND.

24 H Flyback

Proper operation requires current reversal. R should be large enough to limit the peak current at pin 24 to about +4 ma during blanking, and

−500 µA during scan. C

is usually needed for

logic level inputs and should be large enough to make the time constant, R larger than the horizontal period. R

HC17

significantly

and C8are

typically 300 ohms and 330 pf when the flyback waveform has ringing and needs filtering. C may be needed to filter extraneous noise and can be up to 100 pF.

INT

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Schematic Diagram

LM1237

FIGURE 9. LM123x-LM246x Demo Board Schematic

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20023416

Schematic Diagram

LM1237

FIGURE 10. LM123x-LM246x Demo Board Schematic (continued)

20023417

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