NSC DS90CF364MTDX, DS90CF364MTD, DS90CF364AMDC Datasheet

DS90C363/DS90CF364
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link—65 MHz, +3.3V LVDS Receiver
18-Bit Flat Panel Display (FPD) Link—65 MHz

General Description

The DS90C363 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF364 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDSdata channel. Using a 65 MHz clock, the data through­puts is 170 Mbytes/sec. The Transmitter is offered with pro­grammable edge data strobes for convenient interface with a
variety of graphics controllers. The Transmitter can be pro­grammed for Rising edge strobe or Falling edge strobe
through a dedicated pin. A Rising edge Transmitter will inter­operate with a Falling edge Receiver (DS90CF364) without
any translation logic.

This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.

Features

n 20 to 65 MHz shift clock support
n Programmable Transmitter (DS90C363) strobe select

(Rising or Falling edge strobe)

n Single 3.3V supply
n Chipset (Tx + Rx) power consumption

<

250 mW (typ)

n Power-down mode (

<

0.5 mW total)

n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 170 Megabyte/sec bandwidth
n Up to 1.3 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Falling edge data strobe Receiver
n Compatible with TIA/EIA-644 LVDS standard
n ESD rating

>

7kV

n Operating Temperature: −40˚C to +85˚C

Block Diagrams

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Application

DS012886-14

September 1999

DS90C363/DS90CF364 +3.3V Programmable LVDS 18-Bit-Color Flat Panel Display (FPD)

Link— 65 MHz

© 1999 National Semiconductor Corporation DS012886 www.national.com

Block Diagrams (Continued)

DS90C363

DS012886-1

Order Number DS90C363MTD

See NS Package Number MTD48

DS90CF364

DS012886-24

Order Number DS90CF364MTD

See NS Package Number MTD48

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

CC

) −0.3V to +4V

CMOS/TTL Input Voltage −0.3V to (V

CC

+ 0.3V)

CMOS/TTL Output Voltage −0.3V to (V

CC

+ 0.3V)

LVDS Receiver Input Voltage −0.3V to (V

CC

+ 0.3V)

LVDS Driver Output Voltage −0.3V to (V

CC

+ 0.3V)

LVDS Output Short Circuit

Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature

(Soldering, 4 sec) +260˚C

Maximum Package Power Dissipation Capacity 25˚C

MTD48 (TSSOP) Package:

DS90C363 1.98 W
DS90CF364 1.89 W

Package Derating:

DS90C363 16 mW/˚C above +25˚C
DS90CF364 15 mW/˚C above +25˚C

ESD Rating

(HBM, 1.5 kΩ, 100 pF)

>

7kV

Recommended Operating
Conditions

Min Nom Max Units

Supply Voltage (V

CC

) 3.0 3.3 3.6 V

Operating Free Air

Temperature (T

A

) −40 +25 +85 ˚C
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V

CC

) 100 mV

PP

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

V

IH

High Level Input Voltage 2.0 V

CC

V

V

IL

Low Level Input Voltage GND 0.8 V

V

OH

High Level Output Voltage IOH= −0.4 mA 2.7 3.3 V

V

OL

Low Level Output Voltage IOL= 2 mA 0.06 0.3 V

V

CL

Input Clamp Voltage ICL= −18 mA −0.79 −1.5 V

I

IN

Input Current VIN=VCC, GND, 2.5V or 0.4V

±

5.1±10 µA

I

OS

Output Short Circuit Current V

OUT

= 0V −60 −120 mA

LVDS DC SPECIFICATIONS

V

OD

Differential Output Voltage RL= 100Ω 250 345 450 mV

∆V

OD

Change in VODbetween 35 mV
complimentary output states

V

OS

Offset Voltage (Note 4) 1.125 1.25 1.375 V

∆V

OS

Change in VOSbetween 35 mV
complimentary output states

I

OS

Output Short Circuit Current V

OUT

= 0V, RL= 100Ω −3.5 −5 mA

I

OZ

Output TRI-STATE®Current PWR DWN = 0V,

±1±

10 µA

V

OUT

=0VorV

CC

V

TH

Differential Input High Threshold VCM= +1.2V +100 mV

V

TL

Differential Input Low Threshold −100 mV

I

IN

Input Current VIN= +2.4V, VCC= 3.6V

±

10 µA

V

IN

= 0V, VCC= 3.6V

±

10 µA

TRANSMITTER SUPPLY CURRENT

ICCTW Transmitter Supply Current, Worst

Case

R

L

= 100Ω,

C

L

= 5 pF, Worst

Case Pattern

(Figures

1, 3 )

,TA= −40˚C to

+85˚C

f = 32.5 MHz 31 45 mA

f = 37.5 MHz 32 50 mA
f = 65 MHz 42 55 mA

ICCTG Transmitter Supply Current, 16

Grayscale

R

L

= 100Ω,

C

L

= 5 pF, 16

Grayscale Pattern

(Figures 2, 3 )

,TA=

−40˚C to +85˚C

f = 32.5 MHz 23 35 mA

f = 37.5 MHz 28 40 mA
f = 65 MHz 31 45 mA

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Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

TRANSMITTER SUPPLY CURRENT

ICCTZ Transmitter Supply Current PWR DWN = Low

10 55 µA

Power Down Driver Outputs in TRI-STATE

®

under

Power Down Mode

RECEIVER SUPPLY CURRENT

ICCRW Receiver Supply Current, Worst

Case

C

L

= 8 pF, Worst

Case Pattern

(Figures

1,4)

,TA= −40˚C to

+85˚C

f = 32.5 MHz 49 65 mA

f = 37.5 MHz 53 70 mA
f = 65 MHz 78 105 mA

ICCRG Receiver Supply Current, 16

Grayscale

C

L

= 8 pF, 16

Grayscale Pattern

(Figures 2, 4 )

,TA=

−40˚C to +85˚C

f = 32.5 MHz 28 45 mA

f = 37.5 MHz 30 47 mA
f = 65 MHz 43 60 mA

ICCRZ Receiver Supply Current PWR DWN = Low

10 55 µA

Power Down Receiver Outputs Stay Low during

Power Down Mode

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V

CC

= 3.3V and TA= +25C.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci­fied (except V

OD

and ∆VOD).

Note 4: V

OS

previously referred as VCM.

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Transmitter Switching Characteristics

Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

LLHT LVDS Low-to-High Transition Time

(Figure 3 )

0.75 1.5 ns

LHLT LVDS High-to-Low Transition Time

(Figure 3 )

0.75 1.5 ns

TCIT TxCLK IN Transition Time

(Figure 5 )

5ns

TCCS TxOUT Channel-to-Channel Skew

(Figure 6 )

250 ps

TPPos0 Transmitter Output Pulse Position for Bit 0

(Figure 17 )

f = 65 MHz −0.4 0 0.3 ns

TPPos1 Transmitter Output Pulse Position for Bit 1 1.8 2.2 2.5 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 4.0 4.4 4.7 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 6.2 6.6 6.9 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.4 8.8 9.1 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.6 11.0 11.3 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.8 13.2 13.5 ns
TCIP TxCLK IN Period

(Figure 7)

15 T 50 ns

TCIH TxCLK IN High Time

(Figure 7)

0.35T 0.5T 0.65T ns

TCIL TxCLK IN Low Time

(Figure 7)

0.35T 0.5T 0.65T ns

TSTC TxIN Setup to TxCLK IN

(Figure 7 )

f = 65 MHz 2.5 ns

THTC TxIN Hold to TxCLK IN

(Figure 7 )

0ns

TCCD TxCLK IN to TxCLK OUT Delay 25˚C, V

CC

= 3.3V

(Figure 9 )

3.0 3.7 5.5 ns

TPLLS Transmitter Phase Lock Loop Set

(Figure 11 )

10 ms

TPDD Transmitter Power Down Delay

(Figure 15 )

100 ns

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