NSC DP8432V-33 Datasheet

DP8430V/31V/32V-33 microCMOS Programmable
256k/1M/4M Dynamic RAM Controller/Drivers

General Description

The DP8430V/31V/32V dynamic RAM controllers provide a
low cost, single chip interface between dynamic RAM and
all 8-, 16- and 32-bit systems. The DP8430V/31V/32V gen­erate all the required access control signal timing for
DRAMs. An on-chip refresh request clock is used to auto­matically refresh the DRAM array. Refreshes and accesses
are arbitrated on chip. If necessary, a WAIT
put inserts wait states into system access cycles, including
burst mode accesses. RAS
RAS

precharge time after refreshes and back to back ac-

low time during refreshes and

cesses are guaranteed through the insertion of wait states.
Separate on-chip precharge counters for each RAS
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge. An additional fea­ture of the DP8432V is two access ports to simplify dual
accessing. Arbitration among these ports and refresh is
done on chip.

Ý

Control

of Pins

(PLCC) Outputs

DP8430V 68 9 256 kbit 4 Mbytes Single Access Port

DP8431V 68 10 1 Mbit 16 Mbytes Single Access Port

DP8432V 84 11 4 Mbit 64 Mbytes Dual Access Ports (A and B)

Ý

of Address

or DTACK out-

output

Features

Y

On chip high precision delay line to guarantee critical
DRAM access timing parameters

Y

microCMOS process for low power

Y

High capacitance drivers for RAS, CAS,WEand DRAM
address on chip

Y

On chip support for nibble, page and static column
DRAMs

Y

Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic

Y

Can use a single clock source. Up to 33 MHz operating
frequency

Y

On board Port A/Port B (DP8432V only)/refresh arbitra­tion logic

Y

Direct interface to all major microprocessors

Y

4 RAS and 4 CAS drivers (the RAS and CAS configura­tion is programmable)

Largest Direct Drive Access

DRAM Memory Ports

Possible Capacity Available

July 1993

DP8430V/31V/32V-33 microCMOS Programmable

256k/1M/4M Dynamic RAM Controller/Drivers

Block Diagram

DP8430V/31V/32V DRAM Controller

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
Staggered Refresh

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TM

is a trademark of National Semiconductor Corporation.

TL/F/11118

FIGURE 1

TL/F/11118– 1

Table of Contents

1.0 INTRODUCTION

2.0 SIGNAL DESCRIPTIONS

2.1 Address, R/W and Programming Signals

2.2 DRAM Control Signals

2.3 Refresh Signals

2.4 Port A Access Signals

2.5 Port B Access Signals (DP8432V)

2.6 Common Dual Port Signals (DP8432V)

2.7 Power Signals and Capacitor Input

2.8 Clock Inputs

3.0 PROGRAMMING AND RESETTING

3.1 Reset

3.2 Programming Methods

3.2.1 Mode Load Only Programming

3.2.2 Chip Selected Access Programming

3.3 Internal Programming Modes

4.0 PORT A ACCESS MODES

4.1 Access Mode 0

4.2 Access Mode 1

4.3 Extending CAS with Either Access Mode

4.4 Read-Modify-Write Cycles with Either Access Mode

4.5 Additional Access Support Features

4.5.1 Address Latches and Column Increment

4.5.2 Address Pipelining

4.5.3 Delay CAS

5.0 REFRESH OPTIONS

5.1 Refresh Control Modes

5.1.1 Automatic Internal Refresh

5.1.2 Externally Controlled Refresh

During Write Accesses

5.2 Refresh Cycle Types

5.2.1 Conventional Refresh

5.2.2 Staggered Refresh

TM

5.2.3 Error Scrubbing Refresh

5.3 Extending Refresh

6.0 PORT A WAIT STATE SUPPORT

6.1 WAIT

6.2 DTACK

Type Output

Type Output

6.3 Dynamically Increasing the Number of Wait States

6.4 Guaranteeing RAS

Low Time and RAS Precharge

Time

7.0 RAS

AND CAS CONFIGURATION MODES

7.1 Byte Writing

7.2 Memory Interleaving

7.3 Address Pipelining

7.4 Error Scrubbing

7.5 Page/Burst Mode

8.0 TEST MODE

9.0 DRAM CRITICAL TIMING PARAMETERS

9.1 Programmable Values of t

9.2 Calculation of t

RAH

and t

RAH

ASC

and t

ASC

10.0 DUAL ACCESSING (DP8432V)

10.1 Port B Access Mode

10.2 Port B Wait State Support

10.3 Common Port A and Port B Dual Port Functions

10.3.1 GRANTB Output

10.3.2 LOCK

Input

11.0 ABSOLUTE MAXIMUM RATINGS

12.0 DC ELECTRICAL CHARACTERISTICS

13.0 AC TIMING PARAMETERS

14.0 DP8430V/31V/32V USER HINTS

2

1.0 Introduction

The DP8430V/31V/32V DRAM controllers are the latest
devices based upon the DP8420A/21A/22A predecessors.
The DP8430V/31V/32V implement changes which do not
allow them to be pin compatible with any of the DP842XA or
the DP842XV DRAM controllers. Two changes have been
made: The limits for the input frequency to DELCLK have
been increased making possible the use of a single clock
source. A RESET input is now available making the reset
procedure easier. These changes, although minimal, facili­tate the use of the controllers and make them even more
attractive for high performance applications. The controllers
incorporate address latches, refresh counter, row/column/
refresh address multiplexer, delay line, refresh/access/pre­charge arbitration logic and high capacitive drivers. The
DP8430V/31V/32V DRAM controllers allow any manufac­turer’s CPU or bus to directly interface to DRAM arrays up to
64 Mbytes in size.

Reset:

The user must reset the controller before programming it.
Reset is achieved by asserting the RESET
16 positive edges of clock.

Programming:

After reset, the user can program the controller by either
one of two methods: Mode Load Only Programming or Chip
Select Access Programming. The chip is programmed
through the address bus.

Initialization Period:

Once the DP8430V/31V/32V has been programmed for the
first time, a 60 ms initialization period is entered. During this
time the DRC performs refreshes to the DRAM array so
further warm up cycles are unnecessary. The initialization
period is entered only after the first programming after a
reset.

Accessing Modes:

After resetting and programming the chip, the DP8430V/
31V/32V is ready to access the DRAM. There are two
modes of accessing with these controllers. Mode 0, which
indicates RAS
RAS

asynchronously.

Refresh Modes:

Two refresh modes can be programmed. The user can
choose Automatic Internal Refresh or Externally Controlled
Refresh. With any refresh mode the user can perform burst
refreshes.

Refresh Types:

There are three types of refreshing available: Conventional,
Staggered and Error Scrubbing. Any refresh control mode
can be used with any type of refresh.

Wait Support:

The DP8430V/31V/32V have wait support available as
DTACK
Transfer ACKnowledge, is useful for processors whose wait
signal is active high. WAIT
whose wait signal is active low. The user can choose either
at programming. These signals are used by the on chip arbi­ter to insert wait states to guarantee the arbitration between
accesses, refreshes and precharge. Both signals are inde­pendent of the access mode chosen and both signals can
be dynamically delayed further through the WAITIN
the DP8430V/31V/32V.

synchronously and Mode 1, which indicates

or WAIT. Both are programmable. DTACK, Data

is useful for those processors

input for at least

signal to

Sequential Accesses (Static Column/Page Mode):

The DP8430V/31V/32V have address latches, used to
latch the bank, row and column address inputs. Once the
address is latched, a COLumn INCrement (COLINC) feature
can be used to increment the column address. The address
latches can also be programmed to be fall through. COLINC
can be used for Sequential Accesses of Static Column
DRAMs. Also, COLINC in conjunction with ECAS
be used for Sequential Accesses to Page Mode DRAMs.

RAS

and CAS Configuration (Byte Writing):

The RAS and CAS drivers can be configured to drive a one,
two or four bank memory array up to 32 bits in width. The
ECAS

signals can then be used to select one of four CAS

drivers for Byte Writing with no extra logic.

Memory Interleaving:

When configuring the DP8430V/31V/32V for more than
one bank, Memory Interleaving can be used. By tying the
low order address bits to the bank select lines B0 and B1,
sequential back to back accesses will not be delayed since
these controllers have separate precharge counters per
bank.

Address Pipelining:

The DP8430V/31V/32V are capable of performing Address
Pipelining. In address pipelining, the DRC will guarantee the
column address hold time and switch the internal multiple­xor to place the row address on the address bus. At this
time, another memory access to another bank can be initiat­ed.

Dual Accessing:

Finally, the DP8432V has all the features previously men­tioned and unlike the DP8430V/31V, the DP8432V has a
second port to allow a second CPU to access the same
memory array. The DP8432V has four signals to support
Dual Accessing, these signals are AREQB
and GRANTB. All arbitration for the two ports and refresh is
done on chip by the controller through the insertion of wait
states. Since the DP8432V has only one input address bus,
the address lines must be multiplexed externally. The signal
GRANTB can be used for this purpose.

Terminology:

The following explains the terminology used in this data
sheet. The terms negated and asserted are used. Asserted
refers to a ‘‘true’’ signal. Thus, ‘‘ECAS0
the ECAS0
ed’’ means the COLINC input is at a logic 1. The term negat­ed refers to a ‘‘false’’ signal. Thus, ‘‘ECAS0
means the ECAS0
negated’’ means the input COLINC is at a logic 0. The table
shown below clarifies this terminology.

input is at a logic 0. The term ‘‘COLINC assert-

input is at a logic 1. The term ‘‘COLINC

Signal Action Logic Level

Active High Asserted High

Active High Negated Low

Active Low Asserted Low

Active Low Negated High

inputs can

, ATACKB, LOCK

asserted’’ means

negated’’

3

Connection Diagrams

Top View

FIGURE 2

Order Number DP8430V-33

See NS Package Number V68A

TL/F/11118– 2

Top View

FIGURE 4

Order Number DP8432V-33

See NS Package Number V84A

Top View

TL/F/11118– 3

FIGURE 3

Order Number DP8431V-33

See NS Package Number V68A

TL/F/11118– 4

4

2.0 Signal Descriptions

Pin Device (If not Input/

Name Applicable to All) Output

2.1 ADDRESS, R/W AND PROGRAMMING SIGNALS

R0–10 DP8432V I ROW ADDRESS: These inputs are used to specify the row address during an access
R0–9 DP8430V/31V I

C0–10 DP8432V I COLUMN ADDRESS: These inputs are used to specify the column address during an
C0–9 DP8430V/31V I

B0, B1 I BANK SELECT: Depending on programming, these inputs are used to select a group

ECAS0–3 I ENABLE CAS: These inputs are used to enable a single or group of CAS outputs

RESET I RESET: At power up, this input is used to reset the DRAM controller. The user must

WIN I WRITE ENABLE IN: This input is used to signify a write operation to the DRAM. If

COLINC I COLUMN INCREMENT: When the address latches are used, and RFIP is negated,
(EXTNDRF) I

ML I MODE LOAD: This input signal, when low, enables the internal programming register

2.2 DRAM CONTROL SIGNALS

Q0–10 DP8432V O DRAM ADDRESS: These outputs are the multiplexed output of the R0 –9, 10 and
Q0–9 DP8431V O
Q0–8 DP8430V O

RAS0–3 O ROW ADDRESS STROBES: These outputs are asserted to latch the row address

CAS0–3 O COLUMN ADDRESS STROBES: These outputs are asserted to latch the column

WE O WRITE ENABLE or REFRESH REQUEST: This output asserted specifies a write
(RFRQ

)O

to the DRAM. They are also used to program the chip when ML
R10).

access to the DRAM. They are also used to program the chip when ML
(except C10).

of RAS and CAS outputs to assert during an access. They are also used to program
the chip when ML

when asserted. In combination with the B0, B1 and the programming bits, these
inputs select which CAS
ECAS

signals can also be used to toggle a group of CAS outputs for page/nibble
mode accesses. They also can be used for byte write operations. If ECAS
negated during programming, continuing to assert the ECAS
or AREQB during an access, will cause the CAS outputs to be extended while the
RAS

outputs are negated (the ECASn inputs have no effect during scrubbing

refreshes).

keep RESET
must remain negated (high) to avoid an unwanted reset.

ECAS0 is asserted during programming, the WE output will follow this input. This
input asserted will also cause CAS
bit C9 is asserted during programming.

this input functions as COLINC. Asserting this signal causes the column address to
be incremented by one. When RFIP
refresh cycle by any number of periods of CLK until it is negated.

that stores the programming information.

C0–9, 10 and form the DRAM address bus. These outputs contain the refresh
address whenever RFIP
series damping resistors.

contained on the outputs Q0–8, 9, 10 into the DRAM. When RFIP
RAS

outputs are used to latch the refresh row address contained on the Q0–8, 9, 10
outputs in the DRAM. These outputs contain high capacitive drivers with 20X series
damping resistors.

address contained on the outputs Q0–8, 9, 10 into the DRAM. These outputs have
high capacitive drivers with 20X series damping resistors.

operation to the DRAM. When negated, this output specifies a read operation to the
DRAM. When the DP8430V/31V/32V is programmed in address pipelining mode or
when ECAS0 is negated during programming, this output will function as RFRQ.
RFRQ

asserted, specifies that 13 msor15ms have passed. RFRQ can be used to
externally request a refresh through the input RFSH
capacitive driver and a 20X series damping resistor.

is asserted.

output or CAS outputs will assert during an access. The

low for at least 16 positive edges of clock. After programming this input

is asserted. They contain high capacitive drivers with 20X

Description

is asserted (except

is asserted

0is

0 while negating AREQ

to delay to the next positive clock edge if address

is asserted, this signal is used to extend the

is asserted, the

. This output has a high

5

2.0 Signal Descriptions (Continued)

Pin Device (If not Input/

Name Applicable to All) Output

2.3 REFRESH SIGNALS

RFIP O REFRESH IN PROGRESS: This output is asserted prior to a refresh cycle and is

RFSH I REFRESH: This input asserted will request a refresh. If this input is continually

2.4 PORT A ACCESS SIGNALS

ADS I ADDRESS STROBE or ADDRESS LATCH ENABLE: Depending on programming,
(ALE) I

CS I CHIP SELECT: This input signal must be asserted to enable a Port A access.

AREQ I ACCESS REQUEST: This input signal in Mode 0 must be asserted some time after

WAIT O WAIT or DTACK: This output can be programmed to insert wait states into a CPU
(DTACK

)O

WAITIN I WAIT INCREASE: This input can be used to dynamically increase the number of

2.5 PORT B ACCESS SIGNALS

AREQB DP8432V I PORT B ACCESS REQUEST: This input asserted will latch the row, column and bank

ATACKB DP8432V O ADVANCED TRANSFER ACKNOWLEDGE PORT B: This output is asserted when

only

only

negated when all the RAS

asserted, the DP8430V/31V/32V will perform refresh cycles in a burst refresh
fashion until the input is negated.

this input can function as ADS
when asserted along with CS
an access will start from the positive clock edge of CLK as soon as possible. In Mode
1, the input functions as ADS
RAS

to assert if no other event is taking place. If an event is taking place, RAS will be
asserted from the positive edge of CLK as soon as possible. In both cases, the low
going edge of this signal latches the bank, row and column address if programmed to
do so.

the first positive clock edge after ALE has been asserted. When this signal is
negated, RAS
before ADS
access.

access cycle. With R7 negated during programming, the output will function as a
WAIT
With R7 asserted during programming, the output will function as DTACK
case, the output will be negated to signify a wait condition and will be asserted to
signify the access has taken place. Each of these signals can be delayed by a
number of positive clock edges or negative clock levels of CLK to increase the
microprocessor’s access cycle through the insertion of wait states.

positive clock edges of CLK until DTACK
during a DRAM access.

address if programmed, and requests an access to take place for Port B. If the
access can take place, RAS
RAS

the access RAS
the appropriate DTACK

is negated for the access. In Mode 1, this signal must be asserted

can be negated. When this signal is negated, RAS is negated for the

type output. In this case, the output will be active low to signal a wait condition.

will assert as soon as possible from a positive edge of CLK.

is asserted for a Port B access. This signal can be used to generate

or WAIT type signal for Port B’s CPU or bus.

Description

outputs are negated for that refresh.

or ALE. In mode 0, the input functions as ALE and

causes an internal latch to be set. Once this latch is set

and when asserted along with CS, causes the access

. In this

will be asserted or WAIT will be negated

will assert immediately. If the access has to be delayed,

6

2.0 Signal Descriptions (Continued)

Pin Device (If not Input/

Name Applicable to All) Output

2.6 COMMON DUAL PORT SIGNALS

GRANTB DP8432V O GRANT B: This output indicates which port is currently granted access to the DRAM

LOCK DP8432V I LOCK: This input can be used by the currently granted port to ‘‘lock out’’ the other

2.7 POWER SIGNALS AND CAPACITOR INPUT

V

CC

GND I GROUND: Supply Voltage Reference.

CAP I CAPACITOR: This input is used by the internal PLL for stabilization. The value of the

2.8 CLOCK INPUTS

There are two clock inputs to the DP8430V/31V/32V, CLK and DELCLK. These two clocks may both be tied to the same clock
input, or they may be two separate clocks, running at different frequencies, asynchronous to each other.

CLK I SYSTEM CLOCK: This input may be in the range of 0 Hz up to 25 MHz. This input is

DELCLK I DELAY LINE CLOCK: The input frequency to DELCLK should be in the range of

only

only

array. When GRANTB is asserted, Port B has access to the array. When GRANTB is
negated, Port A has access to the DRAM array. This signal is used to multiplex the
signals R0–8, 9, 10; C0 –8, 9, 10; B0 – 1; WIN
when using dual accessing.

port from the DRAM array by inserting wait states into the locked out port’s access
cycle until LOCK is negated.

I POWER: Supply Voltage.

ceramic capacitor should be 0.1 mF and should be connected between this input and
ground.

generally a constant frequency but it may be controlled externally to change
frequencies or perhaps be stopped for some arbitrary period of time.

This input provides the clock to the internal state machine that arbitrates between
accesses and refreshes. This clock’s positive edges and negative levels are used to
extend the WAIT
RAS

precharge time and RAS low time during refresh.

All Port A and Port B accesses are assumed to be synchronous to the system clock
CLK.

12 MHz to 40 MHz. This frequency will be internally divided by choosing a divisor
when programming the part. The result of the division should be a frequency of
2 MHz. This is because the Phase Lock Loop that generates the delay line assumes
an input clock frequency of 2 MHz. If after dividing DELCLK by one of the internal
divisors (6, 8, 10, 12, 14, 16, 18 or 20) the resulting frequency is not 2 MHz, the delay
line will suffer.

For example, if the DELCLK frequency is 18 MHz and a divide by 8 is chosen,
programming bits C0–2, the resulting frequency will be 2.25 which is 12.5% off of
2 MHz. Therefore, the DP8430V/31V/32V will produce delays that are shorter (faster
delays) than what is intended. On the other hand, if divide by 10 was chosen, the
resulting frequency will be 1.8 MHz, this frequency will produce delays that are longer
(slower delays) than intended.

This clock is also divided to create the internal refresh clock.

(DTACK) signals. Ths clock is also used as the reference for the

Description

; LOCK and ECAS0–3 to the DP8432V

7

3.0 Programming and Resetting

The DP8430V/31V/32V must be reset before it can be pro­grammed. After reset, the DRAM controller is programmed
through the address bus by either one of two methods;
Mode Load Only Programming or Chip Select Access Pro­gramming. After the first programming after a reset, the chip
enters a 60 ms initialization period. During this period the
controller performs refreshes every 13 msor15ms, this
makes further DRAM warm up cycles unnecessary. After
this stage the DRAM controller can be programmed as
many times as the user wishes and the 60 ms initialization
period will not be entered into unless the chip is reset and
programmed again. During the 60 ms initialization period,
RFIP

is asserted and RAS toggles every 13 msor15ms
depending on the programming bit for refresh (C3). CAS
be negated and the Q outputs will count from 0 to 2047
refreshing the entire DRAM array. The initialization time pe­riod is given by the following formula. T

e

4096 * (Clock

Divisor Select) * (Refresh Clock Fine Tune)/(DELCLK Frq.)

3.1 RESET

The DP8430V/31V/32V have a RESET

input pin which fa­cilitates the reset procedure required for proper operation.
Reset is accomplished by asserting the RESET
least 16 positive edges of clock as shown in

Figure 5

The DRC may be programmed anytime on the fly, but the
user must make sure that no access or refresh is in prog­ress. RESET

is asynchronous.

will

input for at

.

3.2 PROGRAMMING METHODS

3.2.1 Mode Load Only Programming

To use this method the user asserts ML
nal programming register. After ML

enabling the inter-

is asserted, a valid pro­gramming selection is placed on the address bus, B0, B1
and ECAS0

inputs, then ML is negated. When ML is negat­ed the programming bits are latched into the internal pro­gramming register and the DP8430V/31V/32V is pro­grammed, see
controller must not be refreshing, RFIP

Figure 6

. When programming the chip, the

must be high (1) to

have a successful programming.

3.2.2 Chip Selected Access Programming

The chip can also be programmed by performing a chip
selected access. To program the chip using this method,
ML

is asserted, then CS is asserted and a valid program­ming selection is placed on the address bus. When AREQ
asserted, the programming bits affecting the wait logic be­come effective immediately, then DTACK
ing the access to terminate. After the access, ML

is asserted allow-

is negated

and the rest of the programming bits take effect.

is

FIGURE 5. Reset

FIGURE 6. ML Only Programming

FIGURE 7. CS Access Programming

TL/F/11118– 5

TL/F/11118– 6

TL/F/11118– 7

8

3.0 Programming and Resetting (Continued)

3.3 PROGRAMMING BIT DEFINITIONS

Symbol Description

ECAS0 Extend CAS/Refresh Request Select

0 The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB, DP8432V only) is negated.

1 The CASn outputs will be negated, during an acccess (Port A (or Port B, DP8432V only)) when their

B1 Access Mode Select

0 ACCESS MODE 0: ALE pulsing high sets an internal latch. On the next positive edge of CLK, the access (RAS

1 ACCESS MODE 1: ADS

B0 Address Latch Mode

0 ADS or ALE asserted for Port A or AREQB asserted for Port B with the appropriate GRANT latch the input row,

1 The row, column and bank latches are fall through.

C9 Delay CAS during WRITE Accesses

0 CAS is treated the same for both READ and WRITE accesses.

1 During WRITE accesses, CAS will be asserted by the event that occurs last: CAS asserted by the internal delay

C8 Row Address Hold Time

0 Row Address Hold Timee25 ns minimum

1 Row Address Hold Timee15 ns minimum

C7 Column Address Setup Time

0 Column Address Setup Timee10 ns miniumum

1 Column Address Setup Timee0 ns minimum

C6, C5, C4 RAS and CAS Configuration Modes/Error Scrubbing during Refresh

0, 0, 0 RAS0 – 3 and CAS0–3 are all selected during an access. ECASn must be asserted for CASn to be asserted.

0, 0, 1 RAS

0, 1, 0 RAS and CAS singles are selected during an access by B0 – 1. ECAS

0, 1, 1 RAS

1, 0, 0 RAS pairs are selected by B1. CAS0 – 3 are all selected. ECASn must be asserted for CASn to be asserted.

The WE

output pin will function as write enable. Automatic Internal Refresh selected.

corresponding ECAS
outputs negating. Scrubbing refreshes are NOT affected. During scrubbing refreshes the CAS outputs will negate
along with the RAS

Externally Controlled Refresh selected, WE will function as ReFresh ReQuest (RFRQ).

will start. AREQ

column and bank address.

line or CAS

B0 and B1 are not used during an access. Error scrubbing during refresh.

and CAS pairs are selected during an access by B1. ECASn must be asserted for CAS

e

B1

0 during an access selects RAS0–1 and CAS0–1.
B1e1 during an access selects RAS2–3 and CAS2–3.
B0 is not used during an Access.
Error scrubbing during refresh.

e

B1

0, B0e0 during an access selects RAS0 and CAS0.

e

B1

0, B0e1 during an access selects RAS1 and CAS1.

e

B1

1, B0e0 during an access selects RAS2 and CAS2.
B1e1, B0e1 during an access selects RAS3 and CAS3.
Error scrubbing during refresh.

0–3 and CAS0 –3 are all selected during an access. ECASn must be asserted for CASn to be asserted.
B1, B0 are not used during an access.
No error scrubbing. (RAS

e

B1

0 during an access selects RAS0–1 and CAS0–3.
B1e1 during an access selects RAS2–3 and CAS0–3.
B0 is not used during an access.
No error scrubbing.

n inputs are negated. This feature allows the CAS outputs to be extended beyond the RAS

outputs regardless of the state of the ECAS inputs.

will terminate the access.

asserted starts the access (RAS) immediately. AREQ will terminate the access.

asserted on the positive edge of CLK after RAS is asserted.

n to be asserted.

n must be asserted for CASn to be asserted.

only refreshing)

)

9

3.0 Programming and Resetting (Continued)

3.3 PROGRAMMING BIT DEFINITIONS (Continued)

Symbol Description

C6, C5, C4 RAS and CAS Configuration Modes (Continued)

1, 0, 1 RAS and CAS pairs are selected by B1. ECASn must be asserted for CASn to be asserted.

1, 1, 0 RAS singles are selected by B0 –1. CAS0 – 3 are all selected. ECASn must be asserted for CASntobe

1, 1, 1 RAS and CAS singles are selected by B0, 1. ECASn must be asserted for CASn to be asserted.

C3 Refresh Clock Fine Tune Divisor

0 Divide delay line/refresh clock further by 30 (If DELCLK/Refresh Clock Clock Divisore2 MHze15 ms

1 Divide delay line/refresh clock further by 26 (If DELCLK/Refresh Clock Clock Divisor

C2, C1, C0 Delay Line/Refresh Clock Divisor Select

0, 0, 0 Divide DELCLK by 20 to get as close to 2 MHz as possible.
0, 0, 1 Divide DELCLK by 18 to get as close to 2 MHz as possible.
0, 1, 0 Divide DELCLK by 16 to get as close to 2 MHz as possible.
0, 1, 1 Divide DELCLK by 14 to get as close to 2 MHz as possible.
1, 0, 0 Divide DELCLK by 12 to get as close to 2 MHz as possible.
1, 0, 1 Divide DELCLK by 10 to get as close to 2 MHz as possible.
1, 1, 0 Divide DELCLK by 8 to get as close to 2 MHz as possible.
1, 1, 1 Divide DELCLK by 6 to get as close to 2 MHz as possible.

R9 Refresh Mode Select

0 RAS0 – 3 will all assert and negate at the same time during a refresh.
1 Staggered Refresh. RAS

R8 Address Pipelining Select

0 Address pipelining is selected. The DRAM controller will switch the DRAM column address back to the row

1 Non-address pipelining is selected. The DRAM controller will hold the column address on the DRAM address

R7 WAIT or DTACK Select

0 WAIT type output is selected.
1 DTACK

R6 Add Wait States to the Current Access if WAITIN is Low

0 WAIT or DTACK will be delayed by one additional positive edge of CLK.
1 WAIT

e

B1

0 during an access selects RAS0–1 and CAS0–1.

e

B1

1 during an access selects RAS2–3 and CAS2–3.
B0 is not used during an access.
No error scrubbing.

asserted.

e

B1

0, B0e0 during an access selects RAS0 and CAS0–3.

e

B1

0, B0e1 during an access selects RAS1 and CAS0–3.

e

B1

1, B0e0 during an access selects RAS2 and CAS0–3.

e

B1

1, B0e1 during an access selects RAS3 and CAS0–3.
No error scrubbing.

e

B1

0, B0e0 during an access selects RAS0 and CAS0.

e

B1

0, B0e1 during an access selects RAS1 and CAS1.

e

B1

1, B0e0 during an access selects RAS2 and CAS2.

e

B1

1, B0e1 during an access selects RAS3 and CAS3.
No error scrubbing.

refresh period).

refresh period).

outputs during refresh are separated by one positive clock edge. Depending on the

configuration mode chosen, either one or two RAS

s will be asserted.

address after guaranteeing the column address hold time.

bus until the access RAS

s are negated.

(Data Transfer ACKnowledge) type output is selected.

or DTACK will be delayed by two additional positive edges of CLK.

e

2 MHze13 ms

10

3.0 Programming and Resetting (Continued)

3.3 PROGRAMMING BIT DEFINITIONS (Continued)

Symbol Description

R5, R4 WAIT/DTACK during Burst (See Section 5.1.2 or 5.2.2)

0, 0 NO WAIT STATES; If R7e0 during programming, WAIT will remain negated during burst portion of access.

0, 1 1T; If R7e0 during programming, WAIT will assert when the ECAS inputs are negated with AREQ asserted.

1, 0 (/2T; If R7e0 during programming, WAIT will assert when the ECAS inputs are negated with AREQ asserted.

1, 1 0T; If R7e0 during programming, WAIT will assert when the ECAS inputs are negated. WAIT will negate when

R3, R2 WAIT/DTACK Delay Times (See Section 5.1.1 or 5.2.1)

0, 0 NO WAIT STATES; If R7e0 during programming, WAIT will remain high during non-delayed accesses. WAIT

0, 1 (/2T; If R7e0 during programming, WAIT will negate on the negative level of CLK, after the access RAS.

1, 0 NO WAIT STATES, (/2T; If R7e0 during programming, WAIT will remain high during non-delayed accesses.

1, 1 1T; If R7

R1, R0 RAS Low and RAS Precharge Time

0, 0 RAS asserted during refreshe2 positive edges of CLK.

0, 1 RAS asserted during refreshe3 positive edges of CLK.

1, 0 RAS asserted during refreshe2 positive edges of CLK.

1, 1 RAS

e

If R7

1 programming, DTACK will remain asserted during burst portion of access.

WAIT

will negate from the positive edge of CLK after the ECASs have been asserted.

If R7e1 during programming, DTACK will negate when the ECAS inputs are negated with AREQ asserted.
DTACK

will assert from the positive edge of CLK after the ECASs have been asserted.

WAIT

will negate on the negative level of CLK after the ECASs have been asserted.

e

If R7

1 during programming, DTACK will negate when the ECAS inputs are negated with AREQ asserted.

DTACK

will assert from the negative level of CLK after the ECASs have been asserted.

the ECAS
If R7e1 during programming, DTACK will negate when the ECAS inputs are negated. DTACK will assert when

the ECAS

will negate when RAS is negated during delayed accesses.
NO WAIT STATES; If R7

1T; If R7e1 during programming, DTACK will be asserted on the positive edge of CLK after the access RAS.

WAIT
(/2T; If R7

1(/2T; If R7
of CLK after the access RAS

RAS
RAS

RAS
RAS

RAS
RAS

RAS
RAS

inputs are asserted.

inputs are asserted.

e

1 during programming, DTACK will be asserted when RAS is asserted.

will negate on the negative level of CLK, after the access RAS, during delayed accesses.

e

1 during programming, DTACK will be asserted on the negative level of CLK after the access RAS.

e

0 during programming, WAIT will negate on the positive edge of CLK after the access RAS.

e

1 during programming, DTACK will be asserted on the negative level of CLK after the positive edge

precharge timee1 positive edge of CLK.
will start from the first positive edge of CLK after GRANTB transitions (DP8432V).

precharge timee2 positive edges of CLK.
will start from the second positive edge of CLK after GRANTB transitions (DP8432V).

precharge timee2 positive edges of CLK.
will start from the first positive edge of CLK after GRANTB transitions (DP8432V).

asserted during refreshe4 positive edges of CLK.
precharge timee3 positive edges of CLK.
will start from the second positive edge of CLK after GRANTB transitions (DP8432V).

.

11

4.0 Port A Access Modes

The DP8430V/31V/32V have two general purpose access
modes. Mode 0 RAS
chronous. One of these modes is selected at programming
through the B1 input. A Port A access to DRAM is initiated
by two input signals: ADS
ways terminated by one signal: AREQ
should be synchronous to the input clock.

4.1 ACCESS MODE 0

Mode 0, synchronous access, is selected by negating the
input B1 during programming (B1
access, ALE is pulse high and CS
time was met, a refresh of DRAM or a Port B access was
not in progress, the RAS

synchronous and Mode 1 RAS asyn-

(ALE) and CS. The access is al-

(RASs) would be asserted on the

. These input signals

e

0). To initiate a Mode 0

is asserted. If precharge

first rising edge of clock. If a refresh or a Port B access is in
progress or precharge time is required, the controller will
wait until these events have taken place and assert RAS
(RASs) on the next positive edge of clock.

Sometime after the first positive edge of clock after ALE and
CS

have been asserted, the input AREQ must be asserted.
In single port applications, once AREQ
be negated. On the other hand, ALE can stay asserted sev­eral periods of clock; however, ALE must be negated before
or during the period of CLK in which AREQ

The controller samples AREQ on the every rising edge of
clock after DTACK
AREQ

is sampled negated.

is asserted. The access will end when

is asserted, CS can

is negated.

FIGURE 8a. Access Mode 0

12

TL/F/11118– 8

4.0 Port A Access Modes (Continued)

4.2 ACCESS MODE 1

Mode 1, asynchronous access, is selected by asserting the
input B1 during programming (B1
cesses to start immediately from the access request input,
ADS

. To initiate a Mode 1 access, CS is asserted followed

by ADS

asserted. If precharge time was met, a refresh of
the DRAM or a Port B access was not in progress, the RAS
(RASs) would be asserted from ADS being asserted. If a
refresh or Port B access is in progress or precharge time is
required, the controller will wait until these events have tak-

e

1). This mode allows ac-

en place and assert RAS
of clock.

When ADS
asserted. At this time, ADS
continue the access. Also, ADS
after AREQ
new access will not start until ADS
again. When address pipelining is not implemented, ADS
and AREQ can be tied together.

The access will end when AREQ is negated.

is asserted or sometime after, AREQ must be

has been asserted and negated; however, a

(RASs) from the next rising edge

can be negated and AREQ will

can continue to be asserted

is negated and asserted

FIGURE 8b. Access Mode 1

13

TL/F/11118– 9

4.0 Port A Access Modes (Continued)

4.3 EXTENDING CAS WITH EITHER ACCESS MODE

In both access modes, once AREQ
DTACK

if programmed will be negated. If ECAS0 was as-

serted (0) during programming, CAS

is negated, RAS and

(CASs) will be negated

with AREQ
CAS
been negated, given that the appropriate ECAS

. If ECAS0 was negated (1) during programming,

(CASs) will continue to be asserted after RAS has

inputs are
asserted. This allows a DRAM to have data present on the
data out bus while gaining RAS

precharge time.

FIGURE 9a. Access Mode 0 Extending CAS

FIGURE 9b. Access Mode 1 Extending CAS

TL/F/11118– 10

TL/F/11118– 11

14

4.0 Port A Access Modes (Continued)

4.4 READ-MODIFY-WRITE CYCLES WITH EITHER ACCESS MODE

There are 2 methods by which this chip can be used to do
read-modify-write access cycles. The first method involves
doing a late write access where the WIN
some delay after CAS
volves doing a page mode read access followed by a page
mode write access with RAS

CASn must be toggled using the ECASn inputs and WIN has
to be changed from negated to asserted (read to write)
while CAS

is negated. This method is better than changing

is asserted. The second method in-

held low (see

input is asserted

Figure 9c

).

WIN

from negated to asserted in a late write access be­cause here a problem may arise with DATA IN and DATA
OUT being valid at the same time. This may result in a data
line trying to drive two different levels simultaneously. The
page mode method of a read-modify-write access allows
the user to have transceivers in the system because the
data in (read data) is guaranteed to be high impedance dur­ing the time the data out (write data) is valid.

*There may be idle states inserted here by the CPU.

TL/F/11118– 12

FIGURE 9c. Read-Modify-Write Access Cycle

15

4.0 Port A Access Modes (Continued)

4.5 ADDITIONAL ACCESS SUPPORT FEATURES

To support the different modes of accessing, the DP8430V/
31V/32V offer other access features. These additional fea­tures include: Address Latches and Column Increment (for
page/burst mode support), Address Pipelining, and Delay
CAS

(to allow the user with a multiplexed bus to ensure

valid data is present before CAS

4.5.1 Address Latches and Column Increment

The Address Latches can be programmed, through pro­gramming bit B0. They can be programmed to either latch
the address or remain in a fall-through mode. If the address
latches are used to latch the address, the controller will
function as follows:

In Mode 0, the rising edge of ALE places the latches in fall­through, once ALE is negated, the address present in the
row, column and bank input is latched.

is asserted).

In Mode 1, the address latches are in fall through mode until
ADS

is asserted. ADS asserted latches the address.

Once the address is latched, the column address can be
incremented with the input COLINC. COLINC can be used
for sequential accesses of static column DRAMs. COLINC
can also be used with the ECAS
tial accesses to page mode DRAMs as shown in
COLINC should only be asserted when the signal RFIP
negated during an access since this input functions as ex­tended refresh when RFIP
negated (0) when the address is being latched (ADS
edge in Mode 1). If COLINC is asserted with all of the bits of
the column address asserted (ones), the column address
will return to zero.

inputs to support sequen-

Figure 10

is asserted. COLINC must be

falling

.

is

FIGURE 10. Column Increment

The address latches function differently with the DP8432V.
The DP8432V will latch the address of the currently granted
port. If Port A is currently granted, the address will be
latched as described in Section 4.5.1. If Port A is not grant­ed, and requests an access, the address will be latched on
the first or second positive edge of CLK after GRANTB has
been negated depending on the programming bits R0, R1.

For Port B, if GRANTB is asserted, the address will be
latched with AREQB
address will latch on the first or second positive edge of
CLK after GRANTB is asserted depending on the program­ming bits R0, R1.

16

asserted. If GRANTB is negated, the

TL/F/11118– 13

4.0 Port A Access Modes (Continued)

4.5.2 Address Pipelining

Address pipelining is the overlapping of accesses to differ­ent banks of DRAM. If the majority of successive accesses
are to a different bank, the accesses can be overlapped.
Because of this overlapping, the cycle time of the DRAM
accesses are greatly reduced. The DP8430V/31V/32V can
be programmed to allow a new row address to be placed on
the DRAM address bus after the column address hold time
has been met. At this time, a new access can be initiated
with ADS
AREQ
supports address pipelining for Port A only. This mode can­not be used with page, static column or nibble modes of
operations because the DRAM column address is switched
back to the row address after CAS
programmed through address bit R8 (see

11b

or ALE, depending on the access mode, while

is used to sustain the current access. The DP8432V

is asserted. This mode is

Figures 11a

).

and

During address pipelining in Mode 0, shown in
ALE cannot be pulsed high to start another access until
AREQ

has been asserted for the previous access for at
least one period of CLK. DTACK
negated once AREQ
insert wait states, will be asserted once ALE and CS
asserted.

In Mode 1, shown in
AREQ

is asserted. After meeting the minimum negated
pulse width for ADS
new access. DTACK
AREQ

is negated. WAIT, if programmed, will be asserted
once ADS

In either mode with either type of wait programmed, the
DP8430V/31V/32V will still delay the access for precharge
if sequential accesses are to the same bank or if a refresh
takes place.

is asserted.

is negated. WAIT, if programmed to

Figure 11d

, ADS can again be asserted to start a

, if programmed, will be negated once

, if programmed, will be

, ADS can be negated once

Figure 11c

are

,

FIGURE 11a. Non-Address Pipelined Mode

FIGURE 11b. Address Pipelined Mode

TL/F/11118– 14

TL/F/11118– 15

17