NSC COPCLH988N, COPCLH984N, COPCL988V, COPCL988N, COPCL984WM Datasheet
...
TL/DD/9766
COP688CL/COP684CL, COP888CL/COP884CL,
COP988CL/COP984CL 8-Bit Microcontroller
September 1996
COP688CL/COP684CL, COP888CL/COP884CL,
COP988CL/COP984CL 8-Bit Microcontroller
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor’s M
2
CMOSTMprocess technology. The COP888CL is a
member of this expandable 8-bit core processor family of
microcontrollers. (Continued)
Key Features
Y
Two 16-bit timers, each with two 16-bit registers
supporting:
Ð Processor Independent PWM mode
Ð External Event counter mode
Ð Input Capture mode
Y
4 kbytes of on-chip ROM
Y
128 bytes of on-chip RAM
Additional Peripheral Features
Y
Idle Timer
Y
Multi-input Wake Up (MIWU) with optional interrupts (8)
Y
WATCHDOGTMand Clock Monitor logic
Y
MICROWIRE/PLUSTMserial I/O
I/O Features
Y
Memory mapped I/O
Y
Software selectable I/O options (TRI-STATEÉOutput,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
Y
High current outputs
Y
Schmitt trigger inputs on port G
Y
Packages:
Ð 44 PLCC with 40 I/O pins
Ð 40 DIP with 36 I/O pins
Ð 28 DIP with 24 I/O pins
Ð 28 SO with 24 I/O pins
CPU/Instruction Set Feature
Y
1 ms instruction cycle time
Y
Ten multi-source vectored interrupts servicing
Ð External Interrupt with selectable edge
Ð Idle Timer T0
Ð Timers (Each with 2 interrupts)
Ð MICROWIRE/PLUS
Ð Multi-Input Wake Up
Ð Software Trap
Ð Default VIS (default interrupt)
Y
Versatile and easy to use instruction set
Y
8-bit Stack Pointer (SP)Ðstack in RAM
Y
Two 8-bit Register Indirect Data Memory Pointers (B, X)
Fully Static CMOS
Y
Low current drain (typicallyk1 mA)
Y
Single supply operation: 2.5V to 6.0V
Y
Temperature ranges: 0§Ctoa70§C,b40§Ctoa85§C,
b
55§Ctoa125§C
Development Support
Y
Emulation and OTP devices
Y
Real time emulation and full program debug offered by
MetaLink Development System
Block Diagram
TL/DD/9766– 1
FIGURE 1. Block Diagram
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
TM
,M2CMOSTM, COPSTMmicrocontrollers, WATCHDOGTMand MICROWIRETMare trademarks of National Semiconductor Corporation.
iceMASTER
TM
is a trademark of MetaLink Corporation.
C
1996 National Semiconductor Corporation RRD-B30M96/Printed in U. S. A.
http://www.national.com
General Description (Continued)
It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, two 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), and two power savings modes (HALT and IDLE), both with a multi-
sourced wakeup/interrupt capability. This multi-sourced interrupt capability may also be used independent of the
HALT or IDLE modes. Each I/O pin has software selectable
configurations. The device operates over a voltage range of
2.5V to 6V. High throughput is achieved with an efficient,
regular instruction set operating at a maximum of 1 ms per
instruction rate.
Connection Diagrams
Plastic Chip Carrier
TL/DD/9766– 2
Top View
Order Number COP688CL-XXX/V, COP888CL-XXX/V,
COP988CL-XXX/V or COP988CLH-XXX/V
See NS Plastic Chip Package Number V44A
Dual-In-Line Package
TL/DD/9766– 4
Top View
Order Number COP688CL-XXX/N, COP888CL-XXX/N,
COP988CL-XXX/N or COP988CLH-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
TL/DD/9766– 5
Top View
Order Number COP688CL-XXX/N, COP884CL-XXX/N,
COP984CL-XXX/N or COP984CLH-XXX/N
See NS Molded Package Number N28B
Order Number COP684CL-XXX/WM,
COP884CL-XXX/WM, COP984CL-XXX/WM,
or COP984CLHXXX/WM
See NS Surface Mount Package Number M28B
FIGURE 2. Connection Diagrams
http://www.national.com 2
Connection Diagrams (Continued)
Pinouts for 28-, 40- and 44-Pin Packages
Port Type Alt. Fun Alt. Fun
28-Pin 40-Pin 44-Pin
Pack. Pack. Pack.
L0 I/O MIWU 11 17 17
L1 I/O MIWU 12 18 18
L2 I/O MIWU 13 19 19
L3 I/O MIWU 14 20 20
L4 I/O MIWU T2A 15 21 25
L5 I/O MIWU T2B 16 22 26
L6 I/O MIWU 17 23 27
L7 I/O MIWU 18 24 28
G0 I/O INT 25 35 39
G1 WDOUT 26 36 40
G2 I/O T1B 27 37 41
G3 I/O T1A 28 38 42
G4 I/O SO 1 3 3
G5 I/O SK 2 4 4
G6 I SI 355
G7 I/CKO HALT 4 6 6
RESTART
D0 O 192529
D1 O 202630
D2 O 212731
D3 O 222832
I0 I 799
I1 I 8 10 10
I2 I 11 11
I3 I 12 12
I4 I 9 13 13
I5 I 101414
I6 I 15
I7 I 16
D4 O 29 33
D5 O 30 34
D6 O 31 35
D7 O 32 36
C0 I/O 39 43
C1 I/O 40 44
C2 I/O 1 1
C3 I/O 2 2
C4 I/O 21
C5 I/O 22
C6 I/O 23
C7 I/O 24
Unused* 16
Unused* 15
V
CC
688
GND 23 33 37
CKI 5 7 7
RESET
24 34 38
*eOn the 40-pin package Pins 15 and 16 must be connected to GND.
http://www.national.com3
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)7V
Voltage at Any Pin
b
0.3V to V
CC
a
0.3V
Total Current into V
CC
Pin (Source) 100 mA
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range
b
65§Ctoa140§C
Note:
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP98XCL: 0
§
CsT
A
s
a
70§C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage
COP98XCL 2.5 4.0 V
COP98XCLH 4.0 6.0 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 V
CC
V
Supply Current (Note 2)
CKIe10 MHz V
CC
e
6V, t
c
e
1 ms 12.5 mA
CKI
e
4 MHz V
CC
e
4V, t
c
e
2.5 ms 2.5 mA
HALT Current (Note 3) V
CC
e
6V, CKIe0 MHz
k
0.7 8 mA
V
CC
e
4V, CKIe0 MHz
k
0.4 5 mA
IDLE Current
CKI
e
10 MHz V
CC
e
6V, t
c
e
1 ms 3.5 mA
Input Levels
RESET
Logic High 0.8 V
CC
V
Logic Low 0.2 V
CC
V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
All Other Inputs
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
Hi-Z Input Leakage V
CC
e
6V
b
1
a
1 mA
Input Pullup Current V
CC
e
6V, V
IN
e
0V
b
40
b
250 mA
G and L Port Input Hysteresis 0.35 V
CC
V
Output Current Levels
D Outputs
Source V
CC
e
4V, V
OH
e
3.3V
b
0.4 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
0.2 mA
Sink V
CC
e
4V, V
OL
e
1V 10 mA
V
CC
e
2.5V, V
OL
e
0.4V 2.0 mA
All Others
Source (Weak Pull-Up Mode) V
CC
e
4V, V
OH
e
2.7V
b
10
b
100 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
2.5
b
33 mA
Source (Push-Pull Mode) V
CC
e
4V, V
OH
e
3.3V
b
0.4 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
0.2 mA
Sink (Push-Pull Mode) V
CC
e
4V, V
OL
e
0.4V 1.6 mA
V
CC
e
2.5V, V
OL
e
0.4V 0.7 mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
CC
, L and G0– G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.
http://www.national.com 4
DC Electrical Characteristics 0
§
CsT
A
s
a
70§C unless otherwise specified (Continued)
Parameter Conditions Min Typ Max Units
TRI-STATE Leakage V
CC
e
6.0V
b
1
a
1 mA
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current T
A
e
25§C
g
100 mA
without Latchup (Note 4)
RAM Retention Voltage, V
r
500 ns Rise
2V
and Fall Time (Min)
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
AC Electrical Characteristics 0
§
CsT
A
s
a
70§C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc)
Crystal or Resonator 4V
s
V
CC
s
6V 1 DC ms
2.5V
s
V
CC
k
4V 2.5 DC ms
R/C Oscillator 4V
s
V
CC
s
6V 3 DC ms
2.5V
s
V
CC
k
4V 7.5 DC ms
Inputs
t
SETUP
4VsV
CC
s
6V 200 ns
2.5V
s
V
CC
k
4V 500 ns
t
HOLD
4VsV
CC
s
6V 60 ns
2.5V
s
V
CC
k
4V 150 ns
Output Propagation Delay (Note 5) R
L
e
2.2k, C
L
e
100 pF
t
PD1,tPD0
SO, SK 4VsV
CC
s
6V 0.7 ms
2.5V
s
V
CC
k
4V 1.75 ms
All Others 4V
s
V
CC
s
6V 1 ms
2.5V
s
V
CC
k
4V 2.5 ms
MICROWIRETMSetup Time (t
UWS
)20ns
MICROWIRE Hold Time (t
UWH
)56ns
MICROWIRE Output Propagation Delay (t
UPD
) 220 ns
Input Pulse Width
Interrupt Input High Time 1 t
c
Interrupt Input Low Time 1 t
c
Timer Input High Time 1 t
c
Timer Input Low Time 1 t
c
Reset Pulse Width 1 ms
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCCand the pins will
have sink current to V
CC
when biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective
resistance to V
CC
is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
http://www.national.com5
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)7V
Voltage at Any Pin
b
0.3V to V
CC
a
0.3V
Total Current into V
CC
Pin (Source) 100 mA
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range
b
65§Ctoa140§C
Note:
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP88XCL:
b
40§CsT
A
s
a
85§C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage 2.5 6 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 V
CC
V
Supply Current (Note 2)
CKI
e
10 MHz V
CC
e
6V, t
c
e
1 ms 12.5 mA
CKI
e
4 MHz V
CC
e
4V, t
c
e
2.5 ms 2.5 mA
HALT Current (Note 3) V
CC
e
6V, CKIe0 MHz
k
110 mA
IDLE Current
CKI
e
10 MHz V
CC
e
6V, t
c
e
1 ms 3.5 mA
Input Levels
RESET
Logic High 0.8 V
CC
V
Logic Low 0.2 V
CC
V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
All Other Inputs
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
Hi-Z Input Leakage V
CC
e
6V
b
1
a
1 mA
Input Pullup Current V
CC
e
6V, V
IN
e
0V
b
40
b
250 mA
G and L Port Input Hysteresis 0.35 V
CC
V
Output Current Levels
D Outputs
Source V
CC
e
4V, V
OH
e
3.3V
b
0.4 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
0.2 mA
Sink V
CC
e
4V, V
OL
e
1V 10 mA
V
CC
e
2.5V, V
OL
e
0.4V 2.0 mA
All Others
Source (Weak Pull-Up Mode) V
CC
e
4V, V
OH
e
2.7V
b
10
b
100 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
2.5
b
33 mA
Source (Push-Pull Mode) V
CC
e
4V, V
OH
e
3.3V
b
0.4 mA
V
CC
e
2.5V, V
OH
e
1.8V
b
0.2 mA
Sink (Push-Pull Mode) V
CC
e
4V, V
OL
e
0.4V 1.6 mA
V
CC
e
2.5V, V
OL
e
0.4V 0.7 mA
TRI-STATE Leakage V
CC
e
6.0V
b
2
a
2 mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
CC
, L and G0– G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.
http://www.national.com 6
DC Electrical Characteristics
b
40§CsT
A
s
a
85§C unless otherwise specified (Continued)
Parameter Conditions Min Typ Max Units
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current T
A
e
25§C
g
100 mA
without Latchup (Note 4)
RAM Retention Voltage, V
r
500 ns Rise
2V
and Fall Time (Min)
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
AC Electrical Characteristics
b
40§CsT
A
s
a
85§C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc)
Crystal or Resonator 4V
s
V
CC
s
6V 1 DC ms
2.5V
s
V
CC
k
4V 2.5 DC ms
R/C Oscillator 4V
s
V
CC
s
6V 3 DC ms
2.5V
s
V
CC
k
4V 7.5 DC ms
Inputs
t
SETUP
4VsV
CC
s
6V 200 ns
2.5V
s
V
CC
k
4V 500 ns
t
HOLD
4VsV
CC
s
6V 60 ns
2.5V
s
V
CC
k
4V 150 ns
Output Propagation Delay (Note 5) R
L
e
2.2k, C
L
e
100 pF
t
PD1,tPD0
SO, SK 4VsV
CC
s
6V 0.7 ms
2.5V
s
V
CC
k
4V 1.75 ms
All Others 4V
s
V
CC
s
6V 1 ms
2.5V
s
V
CC
k
4V 2.5 ms
MICROWIRE Setup Time (t
UWS
)20ns
MICROWIRE Hold Time (t
UWH
)56ns
MICROWIRE Output Propagation Delay (t
UPD
) 220 ns
Input Pulse Width
Interrupt Input High Time 1 t
c
Interrupt Input Low Time 1 t
c
Timer Input High Time 1 t
c
Timer Input Low Time 1 t
c
Reset Pulse Width 1 ms
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCCand the pins will
have sink current to V
CC
when biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective
resistance to V
CC
is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
http://www.national.com7
Electrical Specifications
DC ELECTRICAL SPECIFICATIONS
COP688CL Absolute Specifications
Supply Voltage (V
CC
)7V
Voltage at Any Pin
b
0.3V to V
CC
a
0.3V
Total Current into VCCPin (Source) 90 mA
Total Current out of GND Pin (Sink) 100 mA
Storage Temperature Range
b
65§Ctoa150§C
Note:
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP68XCL:
b
55§CsT
A
s
a
125§C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage 4.5 5.5 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 V
CC
V
Supply Current (Note 2)
CKI
e
10 MHz V
CC
e
5.5V, t
c
e
1 ms 12.5 mA
CKI
e
4 MHz V
CC
e
5.5V, t
c
e
2.5 ms 5.5 mA
HALT Current (Note 3) V
CC
e
5.5V, CKIe0 MHz
k
10 30 mA
IDLE Current
CKI
e
10 MHz V
CC
e
5.5V, t
c
e
1 ms 3.5 mA
CKI
e
4 MHz V
CC
e
5.5V, t
c
e
2.5 ms 2.5 mA
Input Levels
RESET
Logic High 0.8 V
CC
V
Logic Low 0.2 V
CC
V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
All Other Inputs
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
Hi-Z Input Leakage V
CC
e
5.5V
b
5
a
5 mA
Input Pullup Current V
CC
e
5.5V, V
IN
e
0V
b
35
b
400 mA
G and L Port Input Hysteresis 0.35 V
CC
V
Output Current Levels
D Outputs
Source V
CC
e
4.5V, V
OH
e
3.8V
b
0.4 mA
Sink V
CC
e
4.5V, V
OL
e
1.0V 9 mA
All Others
Source (Weak Pull-Up Mode) V
CC
e
4.5V, V
OH
e
3.8V
b
9.0
b
140 mA
Source (Push-Pull Mode) V
CC
e
4.5V, V
OH
e
3.8V
b
0.4 mA
Sink (Push-Pull Mode) V
CC
e
4.5V, V
OL
e
0.4V 1.4 mA
TRI-STATE Leakage V
CC
e
5.5V
b
5.0
a
5.0 mA
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
CC
, L and G0– G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.
http://www.national.com 8
DC Electrical Characteristics
b
55§CsT
A
s
a
25§C unless otherwise specified (Continued)
Parameter Conditions Min Typ Max Units
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 12 mA
All others 2.5 mA
Maximum Input Current
150 mA
without Latchup (Note 4)
RAM Retention Voltage, V
r
500 ns Rise
2.0 V
and Fall Time (Min)
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
CC
, L and G ports in the TRI-
STATE mode and tied to ground, all outputs low and tied to ground. The Clock Monitor and the comparators are disabled.
AC Specifications for COP688CL
AC Electrical Characteristics
b
55§CsT
A
s
a
125§C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc)
Crystal, Resonator, or V
CC
t
4.5V
1DCms
External Oscillator
R/C Oscillator (div-by 10) V
CC
t
4.5V 3 DC ms
Inputs
t
SETUP
V
CC
t
4.5V 200 ns
t
HOLD
V
CC
t
4.5V 60 ns
Output Propagation Delay (Note 5) R
L
e
2.2k, C
L
e
100 pF
t
PD1,tPD0
SO, SK V
CC
t
4.5V 0.7 ms
All Others V
CC
t
4.5V 1 ms
MICROWIRE Setup Time (t
UWS
)20ns
MICROWIRE Hold Time(t
UWH
)56ns
MICROWIRE Output Propagation Delay (t
UPD
) 220 ns
Input Pulse Width
Interrupt Input High Time 1 t
c
Interrupt Input Low Time 1 t
c
Timer Input High Time 1 t
c
Timer Input Low Time 1 t
c
Reset Pulse Width 1 ms
Note 4: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCCand the pins will
have sink current to V
CC
when biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective
resistance to V
CC
is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
http://www.national.com9
Typical Performance Characteristics (
b
40§CsT
A
s
a
85§C)
HaltÐI
DD
TL/DD/9766– 27
IdleÐIDD(Crystal Clock Option)
TL/DD/9766– 28
DynamicÐIDDvs V
CC
(Crystal Clock Option)
TL/DD/9766– 29
Port L/C/G Weak Pull-Up
Source Current
TL/DD/9766– 30
Port L/C/G Push-Pull Source Current
TL/DD/9766– 31
Port L/C/G Push-Pull Sink Current
TL/DD/9766– 32
Port D Source Current
TL/DD/9766– 33
Port D Sink Current
TL/DD/9766– 34
http://www.national.com 10
AC Electrical Characteristics (Continued)
TL/DD/9766– 26
FIGURE 2. MICROWIRE/PLUS Timing
Pin Descriptions
VCCand GND are the power supply pins.
CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.
RESET
is the master reset input. See Reset Description
section.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports G and L),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these I/
O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.)
Figure 3
shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
CONFIGURATION DATA
Port Set-Up
Register Register
0 0 Hi-Z Input
(TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
TL/DD/9766– 6
FIGURE 3. I/O Port Configurations
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
Port L supports Multi-Input Wakeup (MIWU) on all eight
pins. L4 and L5 are used for the timer input functions T2A
and T2B.
Port L has the following alternate features:
L0 MIWU
L1 MIWU
L2 MIWU
L3 MIWU
L4 MIWU or T2A
L5 MIWU or T2B
L6 MIWU
L7 MIWU
Port G is an 8-bit port with 5 I/O pins (G0, G2 –G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
G0 and G2 –G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin, but is
also used to bring the device out of HALT mode with a low
to high transition. There are two registers associated with
the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2 – G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (R/C clock configuration), the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits
will return zeros.
Note that the chip will be placed in the HALT mode by writing a ‘‘1’’ to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register.
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
Config Reg. Data Reg.
G7 CLKDLY HALT
G6 Alternate SK IDLE
Port G has the following alternate features:
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
G4 SO (MICROWIRETMSerial Data Output)
G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)
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Pin Descriptions (Continued)
Port G has the following dedicated functions:
G1 WDOUT WATCHDOG and/or Clock Monitor
dedicated output
G7 CKO Oscillator dedicated output or general
purpose input
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredictable values.
Port I is an 8-bit Hi-Z input port. The 40-pin device does not
have a full complement of Port I pins. Pins 15 and 16 on this
package must be connected to GND.
The 28-pin device has four I pins (I0, I1, I4, I5). The user
should pay attention when reading port I to the fact that I4
and I5 are in bit positions 4 and 5 rather than 2 and 3.
The unavailable pins (I4 – I7) are not terminated i.e., they are
floating. A read operation for these unterminated pins will
return unpredictable values. The user must ensure that the
software takes into account by either masking or restricting
the accesses to bit operations. The unterminated port I pins
will draw power only when addressed.
Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs
(except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.8 V
CC
to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000 pF.
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (t
c
) cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program counter (PC). All interrupts vector to program memory location
0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.
The device has 128 bytes of RAM. Sixteen bytes of RAM
are mapped as ‘‘registers’’ at addresses 0F0 to 0FF Hex.
These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
and B are memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers
(other than reserved register 0FF) being available for general usage.
The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET
input is
pulled low. Upon initialization, the data and configuration
registers for Ports L, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is initialized high with RESET
. The PC,
PSW, CNTRL, ICNTRL, and T2CNTRL control registers are
cleared. The Multi-Input Wakeup registers WKEN, WKEDG,
and WKPND are cleared. The Stack Pointer, SP, is initialized to 06F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, and with both
the WATCHDOG service window bits set and the Clock
Monitor bit set. The WATCHDOG and Clock Monitor detector circuits are inhibited during reset. The WATCHDOG service window bits are initialized to the maximum WATCHDOG
service window of 64k t
c
clock cycles. The Clock Monitor bit
is initialized high, and will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor
error will cause an active low error output on pin G1. This
error output will continue until 16 – 32 t
c
clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE
mode.
The external RC network shown in
Figure 4
should be used
to ensure that the RESET
pin is held low until the power
supply to the chip stabilizes.
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