NSC COP8ACC720M8-RE, COP8ACC728N9-RE, COP8ACC728N8-XE, COP8ACC728N8-RE, COP8ACC728M9-XE Datasheet
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COP8ACC7
8-Bit CMOS OTP Microcontroller with 16k Memory and
High Resolution A/D
General Description
The COP8ACC7 OTP (One Time Programmable) microcontrollers are highly integrated COP8
™
Feature core devices
with 16k memory and advanced features including a HighResolution A/D. This multi-chip CMOS device is suited for
applications requiring a full featured controller with a high
resolutionA/D(only one external capacitor required), and for
pre-production devices for a ROM design. Pin and software
compatible (different V
CC
range) 4k ROM versions are available (COPACC5). Erasable windowed versions are available
for use with a range of COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architecture, 4 MHz CKI with 2.5 µs instruction cycle, two external
clock options (–XE= Crystal; –RE= RC), 6 channelA/D with
12-bit resolution, analog capture timer, analog current
source and V
CC
/2 reference, one multi-function 16-bit timer/
counter, MICROWIRE/PLUS
™
serial I/O, two power saving
HALT/IDLE modes, MIWU, high current outputs, software
selectable I/O options, WATCHDOG
™
timer and Clock Monitor, 2.7V to 5.5V operation, program code security, and
20/28 pin packages.
Device included in this datasheet is:
Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature
COP8ACC7xxx9 16k OTP EPROM 128 15/23 20 SOIC, 28 DIP/SOIC 0 to +70˚C
COP8ACC7xxx8 16k OTP EPROM 128 15/23 20 SOIC, 28 DIP/SOIC -40 to +85˚C
Key Features
n Analog Function Block with 12-bit A/D including:
— Analog comparator with seven input muxes
— Constant Current Source and V
CC
/2 Reference
— 16-bit capture timer (upcounter) clocked from CKI
with auto reset on timer startup
n Quiet design (reduced radiated emissions)
n 4096 bytes on-board OTP EPROM with security feature
n 128 bytes on-board RAM
Additional Peripheral Features
n Idle Timer
n One 16-bit timer with two 16-bit registers supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n Multi-Input Wake-Up (MIWU) with optional interrupts
n WATCHDOG and clock monitor logic
n MICROWIRE/PLUS serial I/O with programmable shift
clock-polarity
I/O Features
n Software selectable I/O options (Push-Pull Output, Weak
Pull-Up Input, High Impedance Input)
n High current outputs
n Schmitt Trigger inputs on ports G and L
n Packages:
— 28 DIP/SO with 23 I/O pins
— 20 SO with 15 I/O pins
CPU/Instruction Set Features
n 2.5 µs instruction cycle time
n Eight multi-source vectored interrupt servicing:
— External Interrupt
— Idle Timer T0
— Timer T1 associated Interrupts
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS
— A/D (Capture Timer)
n 8-bit Stack Pointer (SP)— stack in RAM
n Two 8-bit Registers Indirect Data Memory Pointers
(B and X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Temperature ranges: 0˚C to +70˚C, −40˚C to +85˚C
n Available with Crystal (-XE) or R/C (-RE) oscillator
Development System
n Emulation device for COP8ACC5
n Real time emulation and full program debug offered by
MetaLink
®
development system
Applications
n Battery Chargers
n Appliances
n Data Acquisition systems
Driveway™is a trademark of Aisys Intelligent Systems.
COP8
™
, MICROWIRE™, MICROWIRE/PLUS™, and WATCHDOG™are trademarks of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
iceMASTER
®
is a registered trademark of MetaLink Corporation.
May 1999
COP8ACC7 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D
© 1999 National Semiconductor Corporation DS012869 www.national.com
Block Diagram
Connection Diagrams
DS012869-1
FIGURE 1. Block Diagram
DS012869-3
Top View
Order Number COP8ACC720M9–XE/RE or
COP8ACC720N8–XE/RE
See NS Molded Package Number M20B
Note: -X Crystal Oscillator
-R R/C Oscillator
-E Halt Enable
DS012869-2
Top View
Order Number COP8ACC728N9–XE/RE or
COP8ACC728N8–XE/RE
See NS Molded Package Number N28A
Order Number COP8ACC728M9–XE/RE or
COP8ACC728M8–XE/RE
See NS Molded Package Number M28B
FIGURE 2. Connection Diagrams
www.national.com 2
Connection Diagrams (Continued)
Pinouts for 28-Pin, 20-Pin Packages
Port Type Alt. Fun Alt. Fun
28-Pin 20-Pin
DIP/SO SO
L4 I/O MIWU Ext. Int. 4
L5 I/O MIWU Ext. Int. 5
L6 I/O MIWU Ext. Int. 6
L7 I/O MIWU Ext. Int. 7
G0 I/O INT 23 15
G1 WDOUT 24 16
G2 I/O T1B 25 17
G3 I/O T1A 26 18
G4 I/O SO 27 19
G5 I/O SK 28 20
G6 I SI 1 1
G7 I/CKO HALT Restart 2 2
D0 O 11 7
D1 O 12 8
D2 O 13 9
D3 O 14
I0 I Analog CH1 15 10
I1 I I
SRC
16 11
I2 I Analog CH2 17 12
I3 I Analog CH3 18 13
I4 I Analog CH4 19 14
I5 I Analog CH5 20
I6 I Analog CH6 21
I7 I C
OUT
22
V
CC
95
GND 8 4
CKI 3 3
RESET
10 6
Ordering Information
DS012869-39
FIGURE 3. Part Numbering Scheme
www.national.com3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)7V
Voltage at Any Pin −0.3V to V
CC
+0.3V
Total Current into V
CC
Pin (Source) 100 mA
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range −65˚C to +140˚C
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage Peak-to-Peak 2.7 5.5 V
Power Supply Ripple (Note 2) 0.1 V
CC
V
Supply Current (Note 3)
CKI=4 MHz V
CC
=
5.5V, t
C
=
2.5 µs 9.5 mA
CKI=4 MHz V
CC
=
4V, t
C
=
2.5 µs 6.5 mA
CKI=1 MHz V
CC
=
4V, t
C
=
10 µs 5.4 mA
HALT Current (Note 4) V
CC
=
5.5V, CKI=0 MHz
<
510 µA
V
CC
=
4V, CKI=0 MHz
<
36 µA
IDLE Current
CKI=4 MHz V
CC
=
5.5V, t
C
=
2.5 µs 1.5 mA
CKI=1 MHz V
CC
=
4V, t
C
=
10 µs 0.5 mA
Input Levels (V
IH,VIL
)
RESET
Logic High 0.8 V
CC
V
Logic Low 0.2 V
CC
V
CKI, All Other Inputs
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
Hi-Z Input Leakage V
CC
=
5.5V 1 1 µA
Input Pullup Current V
CC
=
5.5V, V
IN
=
0V −40 −250 µA
G and L Port Input Hysteresis (Note 6) 0.35 V
CC
V
Output Current Levels
D Outputs
Source V
CC
=
4V, V
OH
=
3.3V −0.4 mA
V
CC
=
2.7V, V
OH
=
1.8V −0.2 mA
Sink V
CC
=
4V, V
OL
=
1V 10 mA
V
CC
=
2.7V, V
OL
=
0.4V 2.0 mA
All Others
Source (Weak Pull-Up Mode) V
CC
=
4V, V
OH
=
2.7V −10 −110 µA
V
CC
=
2.7V, V
OH
=
1.8V −2.5 −33 µA
Source (Push-Pull Mode) V
CC
=
4V, V
OH
=
3.3V −0.4 mA
V
CC
=
2.7V, V
OH
=
1.8V −0.2 mA
Sink (Push-Pull Mode) V
CC
=
4V, V
OL
=
0.4V 1.6 mA
V
CC
=
2.7V, V
OL
=
0.4V 0.7 mA
TRI-STATE
®
Leakage V
CC
=
5.5V 1 1 µA
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current Room Temp
±
200 mA
without Latchup (Note 5)
RAM Retention Voltage, V
r
500 ns Rise and Fall Time (min) 2 V
www.national.com 4
DC Electrical Characteristics (Continued)
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Input Capacitance (Note 6) 7 pF
Load Capacitance on D2 (Note 6) 1000 pF
AC Electrical Characteristics
0˚C ≤ TA≤ +70˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (Note 8)
Crystal, Resonator 2.7V ≤ V
CC
≤ 4V 2.5 DC µs
4V ≤ V
CC
≤ 5.5V 1.0 DC µs
R/C Oscillator 2.7V ≤ V
CC
≤ 4V 7.5 DC µs
4V ≤ V
CC
≤ 5.5V 3.0 DC µs
Inputs
t
SETUP
4V ≤ VCC≤ 5.5V 200 ns
2.7V ≤ V
CC
≤ 4V 500 ns
t
HOLD
4V ≤ VCC≤ 5.5V 60 ns
2.7V ≤ V
CC
≤ 4V 150 ns
Output Propagation Delay (Note 6) R
L
=
2.2k, C
L
=
100 pF
t
PD1,tPD0
SO, SK 4V ≤ VCC≤ 5.5V 0.7 µs
2.7V ≤ V
CC
≤ 4V 1.75 µs
All Others 4V ≤ V
CC
≤ 5.5V 1 µs
2.7V ≤ V
CC
≤ 4V 2.5 µs
MICROWIRE
™
Setup Time (t
UWS
) (Note 6) VCC≥ 4V 20 ns
MICROWIRE Hold Time (t
UWH
) (Note 6) VCC≥ 4V 56 ns
MICROWIRE Output Propagation Delay (t
UPD
)VCC≥ 4V 220 ns
Input Pulse Width (Note 7)
Interrupt Input High Time 1 t
C
Interrupt Input Low Time 1 t
C
Timer 1, 2, 3 Input High Time 1 t
C
Timer 1, 2, 3 Input Low Time 1 t
C
Reset Pulse Width 1 µs
Note 2: Maximum rate of voltage change must be<0.5V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I
DD
HALT is done with device neither sourcing or
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
CC
;
clock monitor and comparator disabled. Parameter refers to HALTmode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALTin crystal
clock mode.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
>
VCCand the pins will have sink current to VCCwhen
biased at voltages>VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning
excludes ESD transients.
Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 7: Parameter characterized but not tested.
Note 8: t
C
=
Instruction Cycle Time.
www.national.com5
Absolute Maximum Ratings (Note 9)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)7V
Voltage at Any Pin −0.3V to V
CC
+0.3V
Total Current into V
CC
Pin (Source) 100 mA
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range −65˚C to +140˚C
Note 9: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage 2.7 5.5 V
Power Supply Ripple (Note 10) Peak-to-Peak 0.1 V
CC
V
Supply Current (Note 11)
CKI=4 MHz V
CC
=
5.5V, t
C
=
2.5 µs 9.5 mA
CKI=4 MHz V
CC
=
4V, t
C
=
2.5 µs 6.5 mA
CKI=1 MHz V
CC
=
4V, t
C
=
10 µs 5.4 mA
HALT Current (Note 12) V
CC
=
5.5V, CKI=0 MHz
<
512 µA
V
CC
=
4V, CKI=0 MHz
<
38 µA
IDLE Current
CKI=4 MHz V
CC
=
5.5V, t
C
=
2.5 µs 1.5 mA
CKI=1 MHz V
CC
=
4V, t
C
=
10 µs 0.5 mA
Input Levels (V
IH,VIL
)
RESET
Logic High 0.8 V
CC
V
Logic Low 0.2 V
CC
V
CKI, All Other Inputs
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
Hi-Z Input Leakage V
CC
=
5.5V −2 +2 µA
Input Pullup Current V
CC
=
5.5V, V
IN
=
0V −40 −250 µA
G and L Port Input Hysteresis (Note 14) 0.35 V
CC
V
Output Current Levels
D Outputs
Source V
CC
=
4V, V
OH
=
3.3V −0.4 mA
V
CC
=
2.7V, V
OH
=
1.8V −0.2 mA
Sink V
CC
=
4V, V
OL
=
1V 10 mA
V
CC
=
2.7V, V
OL
=
0.4V 2.0 mA
All Others
Source (Weak Pull-Up Mode) V
CC
=
4V, V
OH
=
2.7V −10 −110 µA
V
CC
=
2.7V, V
OH
=
1.8V −2.5 −33 µA
Source (Push-Pull Mode) V
CC
=
4V, V
OH
=
3.3V −0.4 mA
V
CC
=
2.7V, V
OH
=
1.8V −0.2 mA
Sink (Push-Pull Mode) V
CC
=
4V, V
OL
=
0.4V 1.6 mA
V
CC
=
2.7V, V
OL
=
0.4V 0.7 mA
TRI-STATE Leakage V
CC
=
5.5V −2 +2 µA
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current Room Temp
±
200 mA
without Latchup (Note 13)
RAM Retention Voltage, V
r
500 ns Rise and Fall Time (min) 2 V
www.national.com 6
DC Electrical Characteristics (Continued)
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Input Capacitance (Note 14) 7 pF
Load Capacitance on D2 (Note 14) 1000 pF
AC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (Note 16)
Crystal, Resonator 2.7V ≤ V
CC
<
4V 2.5 DC µs
4V ≤ V
CC
≤ 5.5V 1.0 DC µs
R/C Oscillator 2.7V ≤ V
CC
<
4V 7.5 DC µs
4V ≤ V
CC
<
5.5V 3.0 DC µs
Inputs
t
SETUP
4V ≤ VCC≤ 5.5V 200 ns
2.7V ≤ V
CC
<
4V 500 ns
t
HOLD
4V ≤ VCC≤ 5.5V 60 ns
2.7V ≤ V
CC
<
4V 150 ns
Output Propagation Delay (Note 14) R
L
=
2.2k, C
L
=
100 pF
t
PD1,tPD0
SO, SK 4V ≤ VCC≤ 5.5V 0.7 µs
2.7V ≤ V
CC
<
4V 1.75 µs
All Others 4V ≤ V
CC
≤ 5.5V 1 µs
2.7V ≤ V
CC
<
4V 2.5 µs
MICROWIRE Setup Time (t
UWS
) (Note 14) VCC≥ 4V 20 ns
MICROWIRE Hold Time (t
UWH
) (Note 14) VCC≥ 4V 56 ns
MICROWIRE Output Propagation Delay (t
UPD
)VCC≥ 4V 220 ns
Input Pulse Width (Note 15)
Interrupt Input High Time 1 t
C
Interrupt Input Low Time 1 t
C
Timer 1, 2, 3 Input High Time 1 t
C
Timer 1, 2, 3 Input Low Time 1 t
C
Reset Pulse Width 1 µs
Note 10: Maximum rate of voltage change must be<0.5 V/ms.
Note 11: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 12: The HALTmode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I
DD
HALTis done with device neither sourcing or
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
CC
;
clock monitor and comparator disabled. Parameter refers to HALTmode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALTin crystal
clock mode.
Note 13: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
>
VCCand the pins will have sink current to VCCwhen
biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω (typical).
These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This
warning excludes ESD transients.
Note 14: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 15: Parameter characterized but not tested.
Note 16: t
C
=
Instruction Cycle Time.
www.national.com7
Comparator AC and DC Characteristics
V
CC
=
5V, −40˚C ≤ T
A
≤ +85˚C
Parameter Conditions Min Typ Max Units
Input Offset Voltage 0.4V
<
V
IN
<
V
CC
−1.5V
10 25 mV
Input Common Mode Voltage Range
(Note 17)
0.4 V
CC
−1.5 V
Voltage Gain 300k V/V
V
CC
/2 Reference 4.0V<V
CC
<
5.5V 0.5 VCC−0.04 0.5V
CC
0.5VCC+0.04 V
DC Supply Current V
CC
=
5.5V 250 µA
For Comparator (when enabled)
DC Supply Current V
CC
=
5.5V 50 80 µA
For V
CC
/2 reference (when enabled)
DC Supply Current V
CC
=
5.5V 200 µA
For Constant Current Source (when enabled)
Constant Current Source 4.0V
<
V
CC
<
5.5V 7 20 32 µA
Current Source Variation 4.0V
<
V
CC
<
5.5V 2 µA
Temp=Constant
Current Source Enable Time 1.5 2 µs
Comparator Response Time 10 mV overdrive, 1 µs
100 pF load
Note 17: The device is capable of operating over a common mode voltage range of 0 to VCC− 1.5V, however increased offset voltage will be observed between 0V
and 0.4V.
Typical Performance Characteristics (−55˚C ≤ T
A
=
+125˚C)
DS012869-4
FIGURE 4. MICROWIRE/PLUS Timing
DS012869-26 DS012869-27
www.national.com 8
Typical Performance Characteristics (−55˚C ≤ T
A
=
+125˚C) (Continued)
DS012869-28 DS012869-29
DS012869-30
DS012869-31
DS012869-32 DS012869-33
www.national.com9
Typical Performance Characteristics (−55˚C ≤ T
A
=
+125˚C) (Continued)
Pin Descriptions
VCCand GND are the power supply pins. All VCCand GND
pins must be connected.
CKI is the clock input. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET is the master reset input. See Reset description section.
The device contains two bidirectional (one 8-bit, one 4-bit)
I/O ports (G and L), where each individual bit may be independently configured as a weak pullup input, TRI-STATE
(Hi-Z) input or push pull output under program control. Ports
G- and L- feature Schmitt trigger inputs. Three data memory
address locations are allocated for each of these I/O ports.
Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA
register.A memory mapped address is also reserved for the
input pins of each I/O port. (See the memory map for the
various addresses associated with the I/O ports.)
Figure 5
shows the I/O port configurations. The DATAand CONFIGURATION registers allow for each port bit to be individually
configured under software control as shown below:
PORT L is a 4-bit I/O port. All L-pins have Schmitt triggers on
the inputs.
The Port L supports Multi-Input Wake Up on all four pins.
The Port L has the following alternate features:
L7 MIWU or external interrupt
L6 MIWU or external interrupt
L5 MIWU or external interrupt
L4 MIWU or external interrupt
DS012869-34 DS012869-35
DS012869-36
DS012869-37
DS012869-5
FIGURE 5. I/P Port Configurations
www.national.com 10
Pin Descriptions (Continued)
Configuration Data
Port Set-Up
Register Register
0 0 Hi-Z Input (TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
Please note:
The lower 4 L-bits read all ones (L0:L3). This is independant
from the states of the associated bits in the L-port Data- and
Configuration register. The lower 4 bits in the L-port Dataand Configuration register can be used as general purpose
status indicators (flags).
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and
G2–G6 all have Schmitt Triggers on their inputs. Pin G1
serves as the dedicated WDOUT WATCHDOG output, while
pin G7 is either input or output depending on the oscillator
mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALTmode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose input (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below.Reading the G6 and G7
data bits will return zeros.
Note that the chip will be placed in the HALTmode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Config Reg. Data Reg.
G7 CLKDLY HALT
G6 Alternate SK IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOGand/or Clock Monitor dedicated
output.
Port I is an eight-bit Hi-Z input port.
Port I0–I7 are used for the analog function block.
The Port I has the following alternate features:
I7 C
OUT
(Comparator Output)
I6 Analog CH6 (Comparator Positive Input 6)
I5 Analog CH5 (Comparator Positive Input 5)
I4 Analog CH4 (Comparator Positive Input 4)
I3 Analog CH3 (Comparator Positive Input 3/Comparator
Output)
I2 Analog CH2 (Comparator Positive Input 2)
I1 I
SRC
(Comparator Negative Input/Current Source Out)
I0 Analog CH1 (Comparator Positive Input 1)
Port D is a 4-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
Functional Description
The architecture of the device is a modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on the Harvard architecture, permits transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
C
) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC
®
is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
The program memory consists of 16,384 bytes of OTP
EPROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 0FF Hex.
The device can be configured to inhibit external reads of the
program memory.This is done by programming the Security
Byte.
SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.
Security is an optional feature and can only be asserted after
the memory array has been programmed and verified. A secured part will read all 00(hex) by a programmer. The part
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Functional Description (Continued)
will fail Blank Check and will fail Verify operations. A Read
operation will fill the programmer’s memory with 00(hex).
The Security Byte itself is always readable with value of
00(hex) if unsecure and FF(hex) if secure.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, and SP pointers.
The data memory consists of 128 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, B and SP are memory mapped into this space at
address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L and G are cleared, resulting in these
Ports being initialized to the TRI-STATEmode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL and
CNTRL-control registers are cleared. The Comparator Select Register is cleared. The S register is initialized to zero.
The Multi-Input Wakeup registers WKEN and WKEDG are
cleared. Wakeup register WKPND is unknown. The stack
pointer, SP, is initialized to 6F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
C
clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
C
-32 tCclock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in
Figure 6
should be used
to ensure that the RESET pin is held low until the power supply to the chip stabilizes.
WARNING:
When the device is held in reset for a long time it will consume high current (typically about 7 mA). This is not true for
the equivalent ROM device (COP8ACC5).
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (t
C
).
Figure 7
shows the Crystal and R/C Oscillator diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.
Table 1
shows the component values required for various
standard crystal values.
TABLE 1. Crystal Oscillator Configuration, T
A
=
25˚C
R1 R2 C1 C2 CKI Freq
Conditions
(kΩ)(MΩ) (pF) (pF) (MHz)
0 1 30 30–36 10 V
CC
=
5V
0 1 30 30–36 4 V
CC
=
5V
0 1 200 100–150 0.455 V
CC
=
5V
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart input.
Note: Use of the R/C oscillator option will result in higher electromagnetic
emissions.
Table 2
shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
TABLE 2. RC Oscillator Configuration, T
A
=
25˚C
R C CKI Freq Instr. Cycle
Conditions
(kΩ) (pF) (MHz) (µs)
3.3 82 2.2 to 2.7 3.7 to 4.6 V
CC
=
5V
5.6 100 1.1 to 1.3 7.4 to 9.0 V
CC
=
5V
6.8 100 0.9 to 1.1 8.8 to 10.8 V
CC
=
5V
Note 18: 3k ≤ R ≤ 200k
Note 19: 50 pF ≤ C ≤ 200 pF
DS012869-6
RC>5 x POWER SUPPLY RISE TIME
FIGURE 6. Recommended Reset Circuit
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