NSC CLC5902VLA Datasheet

N

CLC5902
Dual Digital T uner/AGC

0
0

May 1999

CLC5902

Dual Digital Tuner/AGC

General Overview

The CLC5902 Dual Digital Tuner/AGC IC is a two channel digital
downconverter (DDC) with integrated automatic gain control
(AGC). The CLC5902 is a key component in the Diversity
Receiver Chipset (DRCS) which includes one CLC5902 Dual
Digital Tuner/AGC, two CLC5956 12-bit analog-to-digital
converters (ADCs), and two CLC5526 digitally controlled variable
gain amplifiers (DVGAs). A block diagram for a Diversity
Receiver Chipset based narrowband communications system is
shown in Figure 1. This system allows direct IF sampling of signals
up to 300MHz for enhanced receive r performance and reduced
system costs.

The CLC5902 offers high dynamic range digital tuning and
filtering based on hard-wired digital signal processing (DSP)
technology. Each channel has independent tuning, phase offset, and
gain settings. Channel filtering is performed by a series of three
filters. The first is a 4-stage Cascaded Integrator Comb (CIC) filter
with a programmable decimation ratio fr om 8 to 2048. Next there
are two symmetric FIR filters, a 21-tap and a 63-tap, both with
programmable coefficients . The first FIR filter de cimates the data
by 2, the second FIR decimates by either 2 or 4. Channel filter

bandwidth at 52MSPS ranges from ±650kHz down to ±1.3kHz.
The CLC5902’s AGC controller monitors the ADC output and

controls the ADC input signal level by adjusting the DVGA setting.
AGC threshold, deadband+hysteresis, and the loop time constant
are user defined. Total dynamic range of greater than 120dB full­scale signal to noise can be achieved with the Diversity Receiver
Chipset.

Features

n

52MSPS Operation

n

Two Independent Channels with
14-bit inputs

n

Greater than 100 dB image rejec­tion

n

Greater than 100 dB spurious free
dynamic range

n

0.02 Hz tuning resolution

n

User Programmable AGC

n

Channel Filters include a Fourth
Order CIC follow ed by 21 -ta p and
63-tap Symmetric FIRs

n

FIR filters process 21-bit Data
with 16-bit Programmable Coeffi­cients

n

Flexible output formats include
12-bit Floating Point or 8, 16, 24,
and 32 bit Fixed Point

n

Serial and Parallel output ports

n

JTAG Boundary Scan

n

8-bit Microprocessor Interface

n

380mW/channel, 52 MHz, 3.3V

n

128 pin PQFP package

Applications

n

Cellular Basestations

n

Satellite Receivers

n

Wireless Local Loop Receivers

n

Digital Communications

CLC5526 CLC5956 CLC5902

LC

IF A

IF B

CLK

Figure 1 Diversity Receiver Chipset Block Diagram

©1999 National Semiconductor Corporation Rev. 3.05 May 27, 1999

DVGA

DVGA

LC

ADC

ADC

12

Dual Digital

4

Tuner/AGC

12

SerialOutA/B
SerialOutB
SCK
SFS
RDY

ParallelOutput[15. .0]
ParallelOutputEnable
ParallelSelect[2..0]

RD

WR

CE
A[7:0]
D[7:0]

Microprocessor
Interface

Channel A Controls

GAIN_A
FREQ_A
PHASE_A

AGC_IC_A
AGC_RB_A
DITH_A

AGAIN[2..0]
ASTROBE

AIN
BIN

TEST_REG

Input Source

A_SOURCE
B_SOURCE

CK

MR

AGC_EN

SI

MUX

A

MUX

B

CLK
GEN

Sync
Logic

14

14

Channel A
Tuning,
Channel Filters, and
AGC (see Figure 14)

Channel B
Tuning,
Channel Filters, and
AGC (see Figure 14)

Channel B Controls

GAIN_B
FREQ_B
PHASE_B

Common Channel Controls

DEC
DEC_BY_4
SCALE
EXP_INH
F1_COEFF
F2_COEFF

AGC_FORCE
AGC_RESET_EN
AGC_HOLD_IC
AGC_LOOP_GAIN
AGC_COUNT
AGC_TABLE

Output Formatter
Floating Point:

4-bit Exponent and
8-bit Mantissa
or

Two’s Complement:

32-bit Truncate d or
24-bit Rounded or
16-bit Rounded or
8-bit Truncated

(see Figure 26)

AGC_IC_B
AGC_RB_B
DITH_B

AOUT/BOUT
BOUT

SCK
SFS

RDY
POUT[15..0]

PSEL[2..0]
POUT_EN

BSTROBE
BGAIN[2..0]

Output Controls

RATE
SOUT_EN
SCK_POL
SFS_POL
RDY_POL
MUX_MODE
PACKED
FORMAT
DEBUG_EN
DEBUG_TAP

Figure 2 CLC5902 Dual Digital Tuner/AGC Block Diagram with Control Register Associations

Functional Description.

The CLC5902 block diagram is shown in Figure 2. The
CLC5902 contains two identical digital down-conversion
(DDC) circuits. Each DDC accepts a 14-bit sample at up
to 52MSPS, down converts from a selected carrier fre­quency to baseband, decimates the sign al rate by a pro­grammable factor rang ing from 32 to 16384, provides
channel filteri ng, and outputs qua drature symbols.

A crossbar switch enables either of the two inputs or a test
register to be routed to either DDC ch annel. Flex ible ch an­nel filtering is provided by the two programma ble deci­mating FIR filters. The fi nal filter outputs can be
converted to a 12-bit floating point format or standard

two’s complement format. The output data is ava ilable at
both serial and parallel ports.

The CLC5902 maintains over 10 0 dB of spurious free
dynamic range and over 10 0 dB of out-of-band rejection.
This allows considerable latitude in channel filter parti­tioning between the analog and digital domains.

The frequencies, phase offsets, and phase dither of the two
sine/cosine numerica lly contro lled oscill ators (NCOs ) can
be independently specified. Both channels share the same

decimation ratio, bandwidth, filter coefficients, and input/
output formats.

Each channel has its own AG C circuit for use with nar­rowband radio channels where most of the cha nnel filter­ing precedes the ADC. The AGC closes the loop around
the CLC5526 DVGA, compressing the dynamic range of
the signal into the ADC . The AG C can be configure d to
operate continuously or in a gated mode. The two AGC
circuits operate independently but share the same pro­grammed parameters and control sign als.

The chip receives configuration and control information
over a microprocessor-compatible bus consisting of an 8­bit data I/O port, an 8-bit address port, a chip enable
strobe, a read strobe, and a write strobe. The chip’s control
registers (8 bits each) are memory mapped into the 8-bit
address space of the control port.

JTAG boundary scan and on-chip diagnostic circuits are
provided to simplify system debug and test.

The CLC5902 supports 3.3V I/O. The CLC5956 ADC
outputs are compatible with the CLC5902 inputs. The
CLC5902 outputs swing to the 3.3V rail so they can be
directly connected to 5V TTL inputs if desired.

Rev. 3.05 May 27, 1999 2 ©1999 National Semiconductor Corporation

CLC5902 Electrical Characteristics

(VCC=+3.3V, 52MHz, CIC Decimation=48, F2 Decimation=2, T

DC Characteristics

PARAMETER SYMBOL MIN TYP MAX UNITS Notes

Voltage input low V
Voltage input high V
Input current I
Voltage output low (I
Voltage output high (I
Input capacitance C

AC Characteristics

= 4mA/12mA, see pin description) V

OL

= -4mA/-12mA, see pin description) V

OH

PARAMETER (CL=50pF) SYMBOL MIN TYP MAX UNITS Notes

=-40°C, T

min

IL
IH

IN

OL
OH

IN

=+85°C; unless specified)

max

-0.5 0.8 V 1

2.0 VCC+0.5 V 1
10 uA 1

0.4 V 1

2.4 V 1

4.0 pF 3

Clock (CK) Frequency (Figure 7) F

CK

52 MHz 1

Spurious Free Dynamic Range SFDR -100 dBFS
Signal to Noise Ratio SNR -127 dBFS
Tuning Resolution 0.02 Hz
Phase Resoluti on 0.005 °

MR

Active Time (Figure 5) t

MR

Inactive to first Control Port Acc ess (Fi gure 5) t

MR

Setup Time to CK (Fig ure 5) t

MR

Hold Time to CK (Figure 5) t

MR

Inactive to A|BSTROBE Release (Figure 5) t

SI

Setup Time to CK (Figure 6) t

SI

Hold Time from CK (Figure 6) t

SI

Pulse Width (Figure 6) t

SI

Inactive to A|BSTROBE Release (Figure 6) t
CK duty cycle (Figure 7) t
CK rise and fall times (V

to VIH) (Figure 7) t

IL

Input setup before CK goes high (A|BIN) (Figure 7) t
Input hold time after CK goes high (Figure 7) t

A|BSTROBE
A|BGAIN Valid Setup before A|BSTROBE
AGC_EN

Pulse Width (Figure 8) t

(Figure 8) t

Active Width (Figure 8) t

SCK to SFS Valid (Table Note A) (Figure 9) t
SCK to A|BOUT Valid (Table Note B) (Figure 9) t
RDY Pulse Width (Figure 9) t
POUT_EN Active to POUT[15..0] Valid (Figure 10) t
POUT_EN Inactiv e to POUT[15..0] Tri-State (Figure 10) t
PSEL[2..0] to POUT[ 15..0 ] Valid (Figure 11) t
RDY to POUT[15..0] New Value Valid (Table Note C) (Figure 12) t

Propagation Delay TCK to TDO (Figure 13) t
Propagation Delay TCK to Data Out (Figure 13) t
Disable Time TCK to TDO (Figure 13) t
Disable Time TCK to Data Out (Figure 13) t
Enable Time TCK to TDO (Figure 13) t

MRA

MRIC

MRSU

MRH

MRSR

SISU

SIH

SIW

SISR

CKDC

RF

SU

HD

STBPW

GSU

ENW

SFSV

OV

RDYW

OENV

OENT

SELV

RDYV

PLH

PHL

PLZ

PHZ

PZL

4 CK periods 1
10 CK periods 1
9ns1
2ns1

17 ns
9ns1
2ns1
4 CK periods 1

17 ns
40 60 % 1

3ns 1
7ns1
3ns1

1 CK period 2
1 CK period 2

2 CK periods 1
07ns1
07ns1

4 CK periods 1

15 ns 1

15 ns 1

20 ns 1

10 ns 1

30 ns 1

35 ns 1

35 ns 1

35 ns 1
035ns1

©1999 National Semiconductor Corporation 3 Rev. 3.05 May 27, 1999

PARAMETER (C

Notes A - C

Notes 1 - 3

Absolute Maximum Ratings

Enable Time TCK to Data Out (Figure 13) t
Setup Time Data to TCK (Figure 13) t
Setup Time TDI to TCK (Figure 13) t
Setup Time TMS to TCK (Figure 13) t
Hold Time Data to TCK (Figure 13) t
Hold Time TCK to TDI (Figure 13) t
Hold Time TCK to TMS (Figure 13) t

TCK Pulse Width High (Figure 13) t
TCK Pulse Width Low (Figure 13) t
TCK Maximum Frequ ency (Figure 13) JTAG

Control Setup before the co ntrolling signal goes low (Figure 14 ) t
Control hold after the controlling signal goes high (Figure 14) t
Controlling strobe pulse wi dth (Write) (Figure 14) t
Control output delay controlling signal low to D (Read) (Figure 14) t
Control tri-state delay after controlling signal goes high (Figure 14) t
Dynamic Supply Current (F
Dynamic Supply Current (F

=52MHz, N=48) I

CK

=52MHz, N=8) I

CK

=50pF) SYMBOL MIN TYP MAX UNITS Notes

L

PZH

S

S

S

H

H

H

WH

WL

CSU

CHD

CSPW

CDLY

CZ

CC

CC

035ns1
10 ns 1
10 ns 1
15 ns 1
55 ns 1
55 ns 1
10 ns 1
55 ns 1
40 ns 1

FMAX

5ns1
5ns1
30 ns 1

230 280 mA 1
260 320 mA 1

essarily implied. Exposure to maximum ratings for extended periods may
affect device reliab i lity.

10 MHz 1

30 ns 1
20 ns 1

A. t

refers to the ri sing edge of SCK when SC K_POL=0 an d the

SFSV

falling edge when SCK_POL=1.
B. t

refers to the rising edge of SCK when SCK_POL=0 and the fall-

OV

ing edge when SCK_POL=1.
C. t

falling edge when RDY_POL=1.

1. These parameters are 100% tested at 25°C.

2. Typical specifications are the mean values of the distributions of deliv­erable CLC5902s tested to date.

3. Min/max ratings are based on product characterization and simulation.
Individual pa rameters a re tested as noted. Ou tgoing qu ality leve ls are
determined from tested parameters.

refers to the rising edge of RDY when RDY_POL=0 and the

RDYV

Positive Supply Voltage (VCC) -0.3V to 4.2V
Voltage on Any Input or Output Pin -0.3V to VCC+0.5V
Input Current at Any Pin ±25mA
Package Input Curre nt ±50mA
Package Dissipation a t TA=25°C 1W
ESD Susceptibility

Human Body Model
Machine Model

Soldering Temperature, Infrared, 10 seco nds 300°C
Storage Temperature -65°C to 150°C

NOTE: Absolute maximum ratings ar e limiting values, to be applie d
individually, and beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions is not nec-

1500V

100V

Recommended Operating Conditions

Positive Supply Voltage (VCC) 3.3V ±10%
Operating Temperature Range -40°C to +85°C

Package Thermal Resistance

Package

128 pin PQFP 39°C/W TBD°C/W

θja θjc

Reliability Information

Transistor Count 1.2 million

Ordering Information

Order Code

CLC5902VLA

CLC-DRCS-PCASM

CLC-CAPT-PCASM

Temperature

Range

-40°C to
+85°C

Description

128-pin PQFP (industrial
temperature range)

Fully loaded Diversity
Receiver Chipset eval ua tion
board and control panel soft­ware.

Data Capture board for the
DRCS with Matlab analysis
routines.

Rev. 3.05 May 27, 1999 4 ©1999 National Semiconductor Corporation

Package Dimensions

Figure 3 CLC5902 Package Dimensions

DETAIL A

Dimension are in millimeters

©1999 National Semiconductor Corporation 5 Rev. 3.05 May 27, 1999

CLC5902 Pinout

AGAIN[0]

VDD

AGAIN[2]

AGAIN[1]

SCAN_EN

TRST

NC

VSS

TMS

TCK

TDI

ASTROBE

TDO

VDD

POUT_SEL[1]

VSS

POUT[1]

VDD

POUT_SEL[0]

POUT_SEL[2]

POUT_EN

POUT[0]

POUT[3]

POUT[2]

POUT[4]

VSS

NC
NC

(MSB) AIN[13]

(MSB) BIN[ 13]

VSS

AIN[12]
AIN[11]
AIN[10]

AIN[9]
AIN[8]
AIN[7]

VDD
AIN[6]
AIN[5]
AIN[4]
AIN[3]
AIN[2]
AIN[1]
AIN[0]

VSS

CK

VDD

BIN[12]
BIN[11]
BIN[10]

BIN[9]
BIN[8]
BIN[7]

VSS
BIN[6]
BIN[5]
BIN[4]
BIN[3]
BIN[2]
BIN[1]
BIN[0]

VSS

NC

1
2
3
4
5
6

7
8

9
10
11

12
13
14
15
16
17
18
19
20
21
22
23

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

127

126

128

414344

394042

125

124

123

122

121

120

119

116

118

115

114

117

113

CLC5902

Dual Digital Tuner/AGC

(Top View)

46

45

47

49

485051

535556

52

54

112

110

109

111

57

58

105

107

108

59

60

103

104

106

102
101
100

64

61

62

63

NC
NC
NC
NC

99

VSS

98

POUT[5]

97

POUT[6]

96
95

POUT[7]
POUT[8]

94
93

POUT[9]

92

VDD
POUT[10]

91

POUT[11]

90

VSS

89
88

POUT[12]

87

POUT[13]

86

POUT[14]

85

VDD

84

POUT[15]
VSS

83

AOUT

82
81

SFS
SCK

80
79

VDD

78

BOUT

77

RDY
VSS

76

D[0]

75

VDD

74

D[1]

73
72

D[2]

71

D[3]

70

D[4]

69

D[5]

68

VSS
NC

67

NC

66

NC

65

SI

VDD

BGAIN[1]

BGAIN[2]

MR

AGC_EN

BGAIN[0]

BSTROBE

VSS

A[6]

A[7]

A[5]

VSS

VDD

A[1]

A[3]

A[2]

A[4]

CE

RD

WR

A[0]

D[7]

D[6]

VSS

VDD

Figure 4 CLC5902 Pinout

Rev. 3.05 May 27, 1999 6 ©1999 National Semiconductor Corporation

Pin Descriptions

Signal Pin DESCRIPTION

MR

AIN[13:0],
BIN[13:0]

AOUT
BOUT
(12mA drive)

AGAIN[2:0],
BGAIN[2:0]

ASTROBE
BSTROBE

SCK
(12mA drive)

SFS
(12mA drive)

POUT[15:0]
(12mA drive)

POUT_SEL[2:0] 112:114

POUT_EN

RDY
(12mA drive)

CK 20

SI

D[7:0]
(12mA drive)

,

45

4:10,12:18
22:28,30:36

82
78

125:127
40:42

124
43

80

81

84,86:88,90,91,
93:97,104:106,
108,109

111

77

46

62,63,69:73,75

MASTER RESET, Active low
Resets all registers within the chip. ASTROBE

INPUT DATA, Active high

2’s comp le ment input data. AIN[13] and BIN[13] are the MSBs. The data is clocked into the chi p on the
rising edge of the clock (CK) . Th e CLC595X connects direct ly to these input pins with no addit ion al logic.

SERIAL OUTPUT DA TA, Active high
The 2’s complement serial output data is transmitted on these pins, MSB first. The output bits change on
the rising edge of SCK (falling e dge if SCK_POL=1) and should be captu red on the falling edge of SCK
(rising if SCK_POL=1). These pins are tri-stated at power up and are enabled by the SOUT_EN control
register bit. See Figure 9 and Figure 29 timing diagrams. In Debug Mode AOUT=DE BUG[1],
BOUT=DEBUG[0].

OUTPUT DAT A TO DVGA, Active high
3 bit bus that sets the gain of the DVGA determined by the AGC circuit.

DVGA STROBE, Active low
Strobes the data into the DVGA. See Figure 8 and Figure 33 timing diagrams.

SERIAL DATA CLOCK, Active high or low
The serial data is clocke d out of the chi p by this clock. The active edg e of th e clock is user programmable.
This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See Figure 9 and Fig­ure 29 timing diagrams . In D ebu g Mode outputs an appropriate clo ck for the debug data.

SERIAL FRAME STROBE, Active high or low
The serial word strobe. This strobe delineates the words within the serial output streams. This strobe is a
pulse at the beginning of each serial word (PACKED=0) or each serial word I/Q pair (PACKED=1). The
polarity of this signal is use r programmable. This pin is tri -stated at power up and is enabl ed by the
SOUT_EN control register bit. See Figure 9 and Figure 29 timing diagrams. In Debug Mode
SFS=DEBUG[2].

PARALLEL OUTPUT DATA, Active high
The output data is transmitted on these pins in parallel format. The POUT_SEL[2..0] pins select one of
eight 16-bit output word s. T he P O U T_ EN
Mode POUT[15..0]=DEBUG[19..4].

PARALLEL OUTPUT DATA SELECT, Active high
The 16-bit output word is sel ecte d wi th these 3 pins according to Table 3. Not used in Debug Mode.

PARALLEL OUTPUT ENABLE. Active low
This pin enables the chip to output the selected output word on the POUT[15:0] pins. Not used in Debu g
Mode.

READY FLAG, Active high or low
The chip asserts this signal to identify the beginning of an output sample period (OSP). The polarity of this
signal is user programmable. This signal is typically used as an interrupt to a DSP chip, but can also be used
as a start pulse to dedicated circuitry. This pin is active regardless of the state of SOUT_EN. In Debug
Mode RDY=DEBUG[3].

INPUT CLOCK. Active high
The clock input to the chip. The AIN, BIN, and SI
of this clock.

SYNC IN. Active low
The sync input to the chip. The decimation counters, dither, and NCO phase can be synchronized by SI
This sync is clocked into the chi p on the rising edge of the input cloc k (CK ). Tie this pin high if external
sync is not required. All sample data is flushed by SI

BSTROBE

DATA BUS. Active high
This is the 8 bit control data I/O bus. Control register data is loade d int o the chip or read from the chip
through these pins. The chip will only drive output data on these pins when CE
is high.

are asserted during SI.

and BSTROBE are asserted during MR.

pin enables these outputs. POUT[15] is t he MSB. In Debug

input signals are clocked into the chip on the rising edge

.

. To properly initialize the DVGA ASTROBE and

is low , RD is low, and WR

Table 1 CLC5902 Pin Descriptions

©1999 National Semiconductor Corporation 7 Rev. 3.05 May 27, 1999

Signal Pin DESCRIPTION

ADDRESS BUS. Active high

A[7:0] 48,50,52:57

RD

WR

CE

AGC_EN

TDO 116 TEST DATA OUT. Active high
TDI 117 TEST DATA IN. Active high with pull-up
TMS 118 TEST MODE SELECT. Active high with pull-up
TCK 119 TEST CLOCK. Active high

TRST

SCAN_EN

VSS

VDD

59

58

60

44

121

122

3,19,29,37,47,51,
61,68,76,83,89,
98,103,110,120

11,21,39,49,64,
74,79,85,92,107,
115,128

These pins are used to address the control registers within the chip. Each of the control registers within the
chip are assigned a unique address in a flat address space. A control register can be written to or read from
by setting A[7:0] to the register’s address.

READ ENABLE. Active low
This pin enables the chip to output the contents of the selected register on the D[7:0] pins when CE is also
low.

WRITE ENABLE. Active low
This pin enables the chip to writ e the value on the D[7:0] pins into the selected register when CE is also
low. This pin can also function as RD/WR

CHIP ENABLE. Active low
This control st ro b e enables the read or w r ite operation. Th e co ntents of the regis ter selected by A[7:0] will
be output on D[7:0] when RD
will be loaded w i th the contents of D[7:0] .

AGC ENABLE. Active low
When enabled thi s pin starts the AGC counter. The AGC will operate until the counter decrements to zero
then the AGC holds the last setting.

RESET. Active low with pull-up
Asynchronous reset for TAP controller. Tie low or to MR

SCAN ENABLE. Active low with pull-up
Enables access to interna l sc an re gisters. Tie high. Used for manufacturing test only!

Ground. Quantity 15.

Power. Quantity 12.

is low and CE is low. If WR is low and CE is low, then the selected register

if RD is held low.

if JTAG is not used.

Table 1 CLC5902 Pin Descriptions

Timing Diagrams

CK

MR

RD

or WR

A|BSTROBE

Figure 5 CLC5902 Master Reset Timing

t

MRH

t

MRA

t

MRSR

t

MRIC

t

MRSU

Rev. 3.05 May 27, 1999 8 ©1999 National Semiconductor Corporation

CK

t

SIW

SI

A|BSTROBE

Figure 6 CLC5902 Synchronization Input (SI) Timing

1/F

CK

t

CKDC

t

CK

t

HD

t

SU

A|BIN

Figure 7 CLC5902 ADC Input and Clock Timing

CKDC

t

SIH

t

SISU

t

SISR

V

V

IL

t

RF

IH

CK

A|BSTROBE

A|BGAIN[2..0]

t

ENW

AGC_EN

Figure 8 CLC5902 DVGA Interface Timing

(n-1)

t

GSU

valid (n)

t

STBPW

©1999 National Semiconductor Corporation 9 Rev. 3.05 May 27, 1999