NSC ADC0851BIV, ADC0851BIN Datasheet
ADC0851 and ADC0858 8-Bit Analog Data
Acquisition and Monitoring Systems
ADC0851 and ADC0858 8-Bit Analog Data Acquisition and Monitoring Systems
January 1995
General Description
The ADC0851 and ADC0858 are 2 and 8 input analog data
acquisition systems. They can function as conventional multiple input A/D converters, automatic scanning A/D converters or programmable analog ‘‘watchdog’’ systems. In
‘‘watchdog’’ mode they monitor analog inputs and determine whether these inputs are inside or outside user programmed window limits. This monitoring process takes
place independent of the host processor. When any input
falls outside of its programmed window limits, an interrupt is
automatically generated which flags the processor; the chip
can then be interrogated as to exactly which channels
crossed which limits.
The advantage of this approach is that its frees the processor from having to frequently monitor analog variables. It
can consequently save having to insert many A/D subroutine calls throughout real time application code. In control
systems where many variables are continually being monitored this can significantly free up the processor, especially
if the variables are DC or slow varying signals.
The Auto A/D conversion feature allows the device to scan
through selected input channels, performing an A/D conversion on each channel without the need to select a new
channel after each conversion.
Applications
Y
Instrumentation monitoring and process control
Y
Digitizing automotive sensor signals
Y
Embedded diagnostics
Simplified Block Diagram
Key Specifications
Y
Resolution 8 Bits
Y
Total error
Y
Low power 50 mW
Y
Conversion time 18 ms/Channel
Y
Limit comparison time 2 ms/Limit
g
(/2 LSB org1 LSB
Features
Y
Watchdog operation signals processor when any
channel is outside user programmed window limits
Y
Frees microprocessor from continually monitoring
analog signals and simplifies applications software
Y
2 (ADC0851) or 8 (ADC0858) analog input channels
Y
Single ended or differential input pairs
Y
COM input for DC offsetting of input voltage
Y
4 (ADC0851) and 16 (ADC0858), 8-bit programmable
limits
Y
NSC MICROWIRETMinterface
Y
Power fail detection
Y
Auto A/D conversion feature
Y
Single 5V supply
Y
Window limits are user programmable via serial interface
FIGURE 1
TL/H/11021– 22
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
MICROWIRE
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
is a trademark of National Semiconductor Corporation.
TL/H/11021
Connection Diagrams
ADC0851
2-Channel MUX
Dual-In-Line Package
Top View
ADC0851 PLCC Package
ADC0858
8-Channel MUX
Dual-In-Line Package
TL/H/11021– 1
TL/H/11021– 2
Top View
ADC0858 PLCC Package
Top View
Ordering Information
Industrial
b
(
40§CsT
s
a
85§C)
A
ADC0851BIN, N16E, 16-Pin
ADC0851CIN Plastic DIP
ADC0858BIN, N20A, 20-Pin
ADC0858CIN Plastic DIP
ADC0851BIV, V20A, 20-Lead
ADC0851CIV PLCC
ADC0858BIV, V20A, 20-Lead
ADC0858CIV PLCC
TL/H/11021– 3
Package
Top View
TL/H/11021– 4
b
(
55§CsT
Military
s
A
a
125§C)
Package
ADC0851CMJ/883 J16A, 16-Pin
Ceramic DIP
ADC0858CMJ/883 J20A, 20-Pin
Ceramic DIP
2
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V
Voltage at Logic and Analog
Inputs (Note 3)
CC
b
0.3V to V
Input Current per Pin
Input Current per Package
Storage Temperature
Package Dissipation 500 mW
ea
at T
25§C (Board Mount) 800 mW
A
b
65§Ctoa150§C
Lead Temperature (Soldering, 10 Sec.)
Dual-In-Line (Plastic)
Dual-In-Line (Ceramic)
ESD Susceptibility (Note 4) 2000V
CC
a
g
g
a
a
6.5V
0.3V
5mA
20 mA
260§C
300§C
Operating Ratings (Notes1&2)
Supply Voltage, V
Temperature Range T
ADC0858CMJ/883
ADC0851CMJ/883
ADC0858BIN, ADC0858CIN
ADC0851BIN, ADC0851CIN
ADC0858BIV, ADC0858CIV
ADC0851BIV, ADC0851CIV
CC
b
55§CsT
b
55§CsT
b
40§CsT
b
40§CsT
b
40§CsT
b
40§CsT
MIN
4.5V to 5.5V
s
s
T
A
s
a
A
s
a
A
s
a
A
s
a
A
s
a
A
s
a
A
T
MAX
125§C
125§C
85§C
85§C
85§C
85§C
DC Electrical Characteristics
The following specifications apply for V
3.16 kX,C
at T
A
e
170 pF) unless otherwise specified. Boldface limits apply for T
ext
e
ea
T
25§C.
J
Parameter Conditions
CC
ea
5VDC,V
REF
ea
4.5 VDC, AGNDeDGNDe0V and f
e
e
T
A
J
Typical Limit Units
(Note 5) (Note 6) (Limits)
e
1 MHz (R
T
MIN
OSC
to T
; all other limits apply
MAX
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error (Note 7)
ADC0851/8/BIN, ADC0851/8/BIV
ADC0851/8/CIN, ADC0851/8/CMJ,
ADC0851/8/CIV
g
(/2 LSB (Max)
g
1 LSB (Max)
g
1 LSB (Max)
Comparator Offset
ADC0851/8/BIN, ADC0858BIV
ADC0851/8/CIN, ADC0851/8/CMJ,
ADC0858CIV
V
Input Resistance 6 3.5 kX (Min)
REF
g
2.5
g
2.5
g
2.5
g
10 mV (Max)
g
20 mV (Max)
g
20 mV (Max)
10 kX (Max)
Common Mode Input Voltage All MUX Inputs GNDb0.05 V (Min)
(Note 8) and COM Input V
DC Common Mode Error DV
Power Supply Sensitivity V
I
, On Channele5V
OFF
Off Channel Off Channel
Leakage Current
(Note 9)
eb
0.05V toa5.05V
CM
e
4.75V
REF
e
V
5Vg5%
CC
e
V
4.5V
REF
e
5Vg10%
V
CC
e
0V
On Channele0V
e
Off Channel
5V
ION, On Channele5V
e
On Channel Off Channel
Leakage Current
(Note 9)
On Channele0V
Off Channel
0V
e
5V
g
g
g
b
a
a
b
1/16
1/16
1/16
0.01
0.01
0.01
0.01
a
0.05 V (Max)
CC
g
1/4 LSB (Max)
g
1/4 LSB (Max)
g
1/2
b
3 mA (Max)
a
3 mA (Max)
a
3 mA (Max)
b
3 mA (Max)
ext
e
3
DC Electrical Characteristics (Continued)
The following specifications apply for V
3.16 kX,C
at T
A
e
170 pF) unless otherwise specified. Boldface limits apply for T
ext
e
ea
T
25§C.
J
CC
ea
5VDC,V
Parameter Conditions
DIGITAL CHARACTERISTICS
I
OUT
OUT
OUT
V
e
5.5V
CC
e
4.5V
CC
e
V
IN
CC
e
0V
IN
e
4.5V
CC
eb
360 mA 2.4 V (Min)
eb
10 mA 4.2 V (Min)
e
1.6 mA
e
4.5V
CC
Logic ‘‘1’’ Input V
Voltage, V
IH
Logic ‘‘0’’ Input V
Voltage, V
IL
Logic ‘‘1’’ Input V
Current, I
IH
Logic ‘‘0’’ Input V
Current, I
IL
Logic ‘‘1’’ Output V
Voltage, V
(Except INT
OH
)I
Logic ‘‘0’’ Output I
Voltage, V
OL
TRI-STATEÉOutput CSeLogic ‘‘1’’ (5V)
Current (DO) V
I
SOURCE
(Except INT
I
SINK
Supply Current, I
ADC0851 or ADC0858 f
)
CC
e
0.4V
OUT
e
V
5V 0.1 3 mA (Max)
OUT
V
Short to GND
OUT
V
Short to V
OUT
e
f
1 MHz 7 10 mA (Max)
CLK
e
2 MHz 7.2 mA
CLK
(Note 10)
CC
REF
ea
4.5 VDC, AGNDeDGNDe0V and f
e
e
T
A
J
Typical Limit Units
(Note 5) (Note 6) (Limits)
0.005 3 mA (Max)
b
0.005
b
0.1
b
14
16 8 mA (Min)
e
1 MHz (R
T
MIN
OSC
to T
; all other limits apply
MAX
2.2 V (Min)
0.8 V(Max)
b
3 mA (Max)
0.4 V (Max)
b
3 mA (Max)
b
6.5 mA (Min)
ext
e
AC Electrical Characteristics
The following specifications apply for V
5 ns unless otherwise specified. Boldface limits apply for T
CC
ea
5VDC,V
REF
Symbol Parameter Conditions
f
CLK
Data Clock Frequency 1 2 MHz (Max)
Clock Duty Cycle 40 % (Min)
(Note 11) 60 % (Max)
t
SET-UP
CS Falling Edge or
Data Input Valid to 30 70 ns (Min)
CLK Rising Edge
t
HOLD
t
PD1,tPD0
Data Input Valid after
CLK Rising Edge
CLK Rising Edge to C
Output Data Valid
e
L
ea
4.5 VDC, AGNDeDGNDe0V, f
e
e
T
T
A
J
MIN
to T
MAX
Typical Limit Units
(Note 5) (Note 6) (Limits)
5 30 ns (Min)
100 pF
80 200 ns (Max)
4
e
; all other limits apply at T
CLK
1 MHz, t
e
A
e
e
t
r
f
e
T
25§C.
J
AC Electrical Characteristics (Continued)
The following specifications apply for V
5 ns unless otherwise specified. Boldface limits apply for T
Symbol Parameter Conditions
t1H,t
0H
Rising Edge of CS to Ce100 pF, Re2k
Data Output Hi-Z (See TRI-STATE 90 200 ns (Max)
CC
ea
5VDC,V
REF
ea
4.5 VDC, AGNDeDGNDe0V, f
e
e
T
T
to T
A
J
MIN
; all other limits apply at T
MAX
Typical Limit Units
(Note 5) (Note 6) (Limits)
CLK
e
1 MHz, t
e
T
A
e
t
r
f
e
25§C.
J
Test Circuits)
f
t
OSC
EOC
Oscillator Clock Freq. R
(Analog Timing) C
CS to End of OSC Clock
Conversion Delay Periods
e
3.16 kX
ext
e
170 pF 0.6 MHz (Min)
ext
1
1.4 MHz (Max)
1 Min
2 Max
t
Conv
Conversion Time OSC Clock
Periods
17 (Min)
18 (Max)
t
CS-INT
C
IN
C
OUT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to ground (AGND
Note 3: All of the analog and digital input pins are internally diode clamped to the supply pins. Should the applied voltage at any pin exceed the power supply
voltage, the additional absolute value of current at that pin (caused by the forward biasing of the internal diodes) should be limited to 5 mA or less.
Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 5: Typical specifications are at
Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 7: Total unadjusted error includes comparator offset, ADC linearity and multiplexer error, and, is expressed in LSBs.
Note 8: Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog input voltages one diode drop below ground or one diode drop
above V
. Care should be exercised when operating the device at low supply voltages (e.g., V
CC
diodes to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full scale. The specification allows 50 mV forward bias of either
clamp diode. Thus as long as V
to5VDCinput voltage range will therefore require a minimum supply voltage of 4.950 VDC.
Note 9: Leakage current is measured with the oscillator clock disabled.
Note 10: Measured supply current does not include the DAC ladder current.
Note 11: A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies.
CS to Interrupt Delay 60 120 ns (Max)
Capacitance of
Logic Input
Capacitance of
Logic Output
a
25§C and represent the most likely parametric norm.
or V
IN
REF
e
DGNDe0V).
does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V
5pF
5pF
e
4.5V) because high analog inputs (5V) can cause the input
CC
e
DC
5
Typical Performance Characteristics
Offset Error vs
Reference Voltage Reference Voltage
OSC Frequency
vs Temperature
Linearity Error vs
OSC Frequency vs
and C
R
ext
ext
Total Unadjusted Error
vs Temperature
TL/H/11021– 5
6
Test Circuits and Waveforms
Timing Diagrams
t
1H
TL/H/11021– 6
t
0H
TL/H/11021– 7
t1H,C
t1H,C
e
10 pF
L
TL/H/11021– 8
e
10 pF
L
TL/H/11021– 9
Data Input Timing
Data Output Timing
TL/H/11021– 11
TL/H/11021– 10
7
Timing Diagrams (Continued)
Watchdog Timing
A/D Conversion Timing
Timing Diagrams for ADC0851 and ADC0858
Read Power Flag after Power Up ADC0851/ADC0858
TL/H/11021– 12
TL/H/11021– 13
TL/H/11021– 14
8
Timing Diagrams for ADC0851 and ADC0858 (Continued)
TL/H/11021– 15
TL/H/11021– 16
Write 1 Limit to ADC0851/ADC0858
9
Timing Diagrams for ADC0851 and ADC0858 (Continued)
Write all Limits to ADC0851/ADC0858
TL/H/11021– 17
Read 1 Limit from ADC0851/ADC0858
TL/H/11021– 18
TL/H/11021– 19
Read all Limits from ADC0851/ADC0858
10
Timing Diagrams for ADC0851 and ADC0858 (Continued)
TL/H/11021– 20
TL/H/11021– 21
1 A/D Conversion ADC0851/ADC0858
Auto A/D Conversion ADC0851/ADC0858
11
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