Electrical Characteristics (Continued)
The following specifications apply for VCC=5VDCunless otherwise specified.Boldface limits apply from T
MIN
to T
MAX
; all
other limits T
A=Tj
= 25˚C.
Parameter Conditions
ADC0844BCJ
ADC0844CCJ
ADC0844CCN
ADC0848BCN, ADC0848CCN
ADC0848BCV, ADC0848CCV
Limit
Units
Typ Tested Design Typ Tested Design
(Note 5) Limit Limit (Note 5) Limit Limit
(Note 6) (Note 7) (Note 6) (Note 7)
DIGITAL AND DC CHARACTERISTICS
V
OUT(0)
, Logical “0” VCC=4.75V 0.4 0.34 0.4 V
Output Voltage (Max) I
OUT
=1.6 mA
I
OUT
, TRI-STATE Output V
OUT
=0V −0.01 −3 −0.01 −0.3 −3 µA
Current (Max) V
OUT
=5V 0.01 3 0.01 0.3 3 µA
I
SOURCE
, Output Source V
OUT
=0V −14 −6.5 −14 −7.5 −6.5 mA
Current (Min)
I
SINK
, Output Sink V
OUT=VCC
16 8.0 16 9.0 8.0 mA
Current (Min)
I
CC
, Supply Current (Max) CS =1, V
REF
Open
1 2.5 1 2.3 2.5 mA
AC Electrical Characteristics
The following specifications apply for VCC=5VDC,tr=tf= 10 ns unless otherwise specified. Boldface limits apply from T
MIN
to T
MAX
; all other limits TA=Tj= 25˚C.
Tested Design
Parameter Conditions Typ Limit Limit Units
(Note 5) (Note 6) (Note 7)
t
C
, Maximum Conversion Time (See Graph) 30 40 60 µs
t
W(WR)
, Minimum WR Pulse Width (Note 11) 50 150 ns
t
ACC
, Maximum Access Time (Delay from Falling Edge of CL= 100 pF 145 225 ns
RD to Output Data Valid)
(Note 11)
t
1H,t0H
, TRI-STATE Control (Maximum Delay from Rising CL= 10 pF, RL= 10k 125 200 ns
Edge of RD to Hi-Z State)
(Note 11)
t
WI,tRI
, Maximum Delay from Falling Edge of WR or RD to (Note 11) 200 400 ns
Reset of INTR
tDS, Minimum Data Set-Up Time (Note 11) 50 100 ns
t
DH
, Minimum Data Hold Time (Note 11) 0 50 ns
C
IN
, Capacitance of Logic Inputs 5 pF
C
OUT
, Capacitance of Logic Outputs 5 pF
Note 1: Absolute Maximum Ratingsindicate limits beyond which damageto the device may occur. DC andAC electrical specificationsdo not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the ground pins.
Note 3: When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
V−or V
IN
>
V+) the absolute value of the current at that pinshould be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Typicals are at 25˚C and represent most likely parametric norm.
Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.
Note 9: For V
IN
(−) ≥ VIN(+) the digital outputcode will be 0000 0000. Twoon-chip diodes are tied to each analog input, which will forward-conduct for analog input
voltages one diode drop below ground or one diode drop greaterthan V
CC
supply.Be careful during testingat low VCClevels (4.5V), as high level analog inputs (5V)
can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias
of either diode. This means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an
absolute 0 V
DC
to5VDCinput voltage range will therefore require a minimum supply voltage of4.950 VDCover temperature variations, initial tolerance and loading.
Note 10: Off channel leakage current is measured after the channel selection.
Note 11: The temperature coefficient is 0.3%/˚C.
ADC0844/ADC0848
www.national.com 4