NSC ADC0820BMWC, ADC0820BMDC, ADC0820BCJ, ADC0820CMWC, ADC0820CMDC Datasheet

ADC0820
8-Bit High Speed µP Compatible A/D Converter with
Track/Hold Function

General Description

By using a half-flash conversion technique, the 8-bit
ADC0820 CMOS A/D offers a 1.5 µs conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bitADCand
a least significant 4-bit ADC.

The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external
sample-and-hold for signals moving at less than 100 mV/µs.

For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or I/O port
without the need for external interfacing logic.

Key Specifications

j

Resolution 8 Bits

j

Conversion Time 2.5 µs Max (RD Mode)

1.5 µs Max (WR-RD Mode)

j

Low Power 75 mW Max

j

Total Unadjusted

Error

±

1

⁄2LSB and±1 LSB

Features

n Built-in track-and-hold function
n No missing codes
n No external clocking
n Single supply —5 V

DC

n Easy interface to all microprocessors, or operates

stand-alone

n Latched STRI-STATE output
n Logic inputs and outputs meet both MOS and T

2

L

voltage level specifications

n Operates ratiometrically or with any reference value

equal to or less than V

CC

n 0V to 5V analog input voltage range with single 5V

supply

n No zero or full-scale adjust required
n Overflow output available for cascading
n 0.3" standard width 20-pin DIP
n 20-pin molded chip carrier package
n 20-pin small outline package
n 20-pin shrink small outline package (SSOP)

Connection and Functional Diagrams

Dual-In-Line, Small Outline

and SSOP Packages

DS005501-1

Top View

Molded Chip Carrier

Package

DS005501-33

June 1999

ADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold Function

© 2001 National Semiconductor Corporation DS005501 www.national.com

Connection and Functional Diagrams (Continued)

Ordering Information

Part Number Total Package Temperature

Unadjusted Error Range

ADC0820BCV V20A—Molded Chip Carrier 0˚C to +70˚C
ADC0820BCWM

±

1

⁄2LSB M20B—Wide Body Small Outline 0˚C to +70˚C
ADC0820BCN N20A—Molded DIP 0˚C to +70˚C
ADC0820CCJ

±

1 LSB

J20A—Cerdip −40˚C to +85˚C
ADC0820CCWM M20B—Wide Body Small Outline 0˚C to +70˚C
ADC0820CIWM M20B—Wide Body Small Outline −40˚C to +85˚C
ADC0820CCN N20A—Molded DIP 0˚C to +70˚C

DS005501-2

FIGURE 1.

ADC0820

www.national.com 2

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the NationalSemiconductorSales Office/
Distributors for availability and specifications.

Supply Voltage (V

CC

) 10V

Logic Control Inputs −0.2V to V

CC

+0.2V

Voltage at Other Inputs and Output −0.2V to V

CC

+0.2V
Storage Temperature Range −65˚C to +150˚C
Package Dissipation at T

A

= 25˚C 875 mW
Input Current at Any Pin (Note 5) 1 mA
Package Input Current (Note 5) 4 mA
ESD Susceptability (Note 9) 1200V
Lead Temp. (Soldering, 10 sec.)

Dual-In-Line Package (plastic) 260˚C

Dual-In-Line Package (ceramic) 300˚C
Surface Mount Package

Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C

Operating Ratings (Notes 1, 2)

Temperature Range T

MIN≤TA≤TMAX

ADC0820CCJ −40˚C≤TA≤+85˚C
ADC0820CIWM −40˚C≤T

A

≤+85˚C

ADC0820BCN, ADC0820CCN 0˚C≤T

A

≤70˚C

ADC0820BCV 0˚C≤T

A

≤70˚C

ADC0820BCWM, ADC0820CCWM 0˚C≤T

A

≤70˚C

V

CC

Range 4.5V to 8V

Converter Characteristics

The following specifications apply for RD mode (pin 7=0), VCC=5V, V

REF

(+)=5V,and V

REF

(−)=GND unless otherwise specified.

Boldface limits apply from T

MIN

to T

MAX

; all other limits TA=Tj=25˚C.

Parameter Conditions ADC0820BCN, ADC0820CCN Limit

Units

ADC0820CCJ ADC0820BCV, ADC0820BCWM

ADC0820CCWM, ADC0820CIWM

Typ Tested Design Typ Tested Design

(Note 6) Limit Limit (Note 6) Limit Limit

(Note 7) (Note 8) (Note 7) (Note 8)
Resolution 8 8 8 Bits
Total Unadjusted ADC0820BCN, BCWM

±

1

⁄

2

±

1

⁄

2

LSB

Error ADC0820CCJ

±

1 LSB

(Note 3) ADC0820CCN, CCWM, CIWM,

±

1

±

1 LSB

ADC0820CCMSA

±

1

±

1 LSB

Minimum Reference 2.3 1.00 2.3 1.2 kΩ
Resistance
Maximum Reference 2.3 6 2.3 5.3 6 kΩ
Resistance
Maximum V

REF

(+) V

CC

V

CC

V

CC

V
Input Voltage
Minimum V

REF

(−) GND GND GND V
Input Voltage
Minimum V

REF

(+) V

REF

(−) V

REF

(−) V

REF

(−) V

Input Voltage
Maximum V

REF

(−) V

REF

(+) V

REF

(+) V

REF

(+) V

Input Voltage
Maximum V

IN

Input VCC+0.1 VCC+0.1 VCC+0.1 V
Voltage
Minimum V

IN

Input GND−0.1 GND−0.1 GND−0.1 V
Voltage
Maximum Analog CS =V

CC

Input Leakage VIN=V

CC

3 0.3 3 µA

Current V

IN

=GND −3 −0.3 −3 µA

Power Supply V

CC

=5V±5%

±

1/16

±

1

⁄

4

±

1/16

±

1

⁄

4

±

1

⁄

4

LSB

Sensitivity

ADC0820

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DC Electrical Characteristics

The following specifications apply for VCC=5V, unless otherwise specified. Boldface limits apply from T

MIN

to T

MAX

; all other

limits T

A=TJ

=25˚C.

Parameter Conditions ADC0820BCN, ADC0820CCN Limit

Units

ADC0820CCJ ADC0820BCV, ADC0820BCWM

ADC0820CCWM, ADC0820CIWM

Typ Tested Design Typ Tested Design

(Note 6) Limit Limit (Note 6) Limit Limit

(Note 7) (Note 8) (Note 7) (Note 8)

V

IN(1)

, Logical “1” VCC=5.25V CS , WR , RD 2.0 2.0 2.0 V
Input Voltage Mode 3.5 3.5 3.5 V
V

IN(0)

, Logical “0” VCC=4.75V CS , WR , RD 0.8 0.8 0.8 V
Input Voltage Mode 1.5 1.5 1.5 V
I

IN(1)

, Logical “1” V

IN(1)

=5V; CS , RD 0.005 1 0.005 1 µA

Input Current V

IN(1)

=5V; WR 0.1 3 0.1 0.3 3 µA

V

IN(1)

=5V; Mode 50 200 50 170 200 µA

I

IN(0)

, Logical “0” V

IN(0)

=0V;CS,RD,WR, −0.005 −1 −0.005 −1 µA
Input Current Mode
V

OUT(1)

, Logical “1” VCC=4.75V, I

OUT

=−360 µA; 2.4 2.8 2.4 V

Output Voltage DB0–DB7, OFL , INT

VCC=4.75V, I

OUT

=−10 µA; 4.5 4.6 4.5 V

DB0–DB7, OFL , INT

V

OUT(0)

, Logical “0” VCC=4.75V, I

OUT

=1.6 mA; 0.4 0.34 0.4 V
Output Voltage DB0–DB7, OFL , INT , RDY
I

OUT

, TRI-STATE V

OUT

=5V; DB0–DB7, RDY 0.1 3 0.1 0.3 3 µA

Output Current V

OUT

=0V; DB0–DB7, RDY −0.1 −3 −0.1 −0.3 −3 µA

I

SOURCE

, Output V

OUT

=0V; DB0–DB7, OFL −12 −6 −12 −7.2 −6 mA

Source Current INT

−9 −4.0 −9 −5.3 −4.0 mA

I

SINK

, Output Sink V

OUT

=5V; DB0–DB7, OFL , 14 7 14 8.4 7 mA
Current INT , RDY
ICC, Supply Current CS =WR =RD =0 7.5 15 7.5 13 15 mA

AC Electrical Characteristics

The following specifications apply for VCC=5V, tr=tf=20 ns, V

REF

(+)=5V, V

REF

(−)=0V and TA=25˚C unless otherwise specified.

Typ Tested Design

Parameter Conditions (Note 6) Limit Limit Units

(Note 7) (Note 8)

t

CRD

, Conversion Time for RD

Mode

Pin 7 = 0,

Figure 2

1.6 2.5 µs

t

ACC0

, Access Time (Delay from Pin 7 = 0,

Figure 2

t

CRD

+20 t

CRD

+50 ns

Falling Edge of RD to Output
Valid)

t

CWR-RD

, Conversion Time for Pin 7 = VCC;tWR= 600 ns, 1.52 µs

WR-RD Mode t

RD

=600 ns;

Figures 3, 4

tWR, Write Time Min Pin 7 = VCC;

Figures 3, 4

600 ns

Max (Note 4) See Graph 50 µs

t

RD

, Read Time Min Pin 7 = VCC;

Figures 3, 4

600 ns

(Note 4) See Graph

t

ACC1

, Access Time (Delay from Pin 7 = VCC,t

RD

<

tI;

Figure 3

Falling Edge of RD to Output
Valid)

C

L

=15 pF 190 280 ns

C

L

=100 pF 210 320 ns

ADC0820

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AC Electrical Characteristics (Continued)

The following specifications apply for VCC=5V, tr=tf=20 ns, V

REF

(+)=5V, V

REF

(−)=0V and TA=25˚C unless otherwise specified.

Typ Tested Design

Parameter Conditions (Note 6) Limit Limit Units

(Note 7) (Note 8)

t

ACC2

, Access Time (Delay from
Falling Edge of RD to Output
Valid)

Pin 7 = V

CC,tRD

>

tI;

Figure 4

CL=15 pF 70 120 ns
C

L

=100 pF 90 150 ns

t

ACC3

, Access Time (Delay from
Rising Edge of RDY to Output
Valid)

R

PULLUP

= 1k and CL=15pF 30 ns

t

I

, Internal Comparison Time Pin 7=VCC;

Figures 4, 5

800 1300 ns

C

L

=50 pF

t

1H,t0H

, TRI-STATE Control RL=1k, CL=10 pF 100 200 ns
(Delay from Rising Edge of RD to
Hi-Z State)
t

INTL

, Delay from Rising Edge of Pin 7 = VCC,CL=50pF

WR to Falling Edge of INT

t

RD

>

tI;

Figure 4

t

I

ns

t

RD

<

tI;

Figure 3

tRD+200 tRD+290 ns

t

INTH

, Delay from Rising Edge of

Figures 2, 3, 4

125 225 ns

RD to Rising Edge of INT

CL=50 pFc

t

INTHWR

, Delay from Rising Edge of

Figure 5

,CL=50 pF 175 270 ns
WR to Rising Edge of INT
t

RDY

, Delay from CS to RDY

Figure 2

,CL=50 pF, Pin 7 =0 50 100 ns
t

ID

, Delay from INT to Output Valid

Figure 5

20 50 ns

t

RI

, Delay from RD to INT Pin 7=VCC,t

RD

<

t

I

200 290 ns

Figure 3

tP, Delay from End of Conversion

Figures 2, 3, 4, 5

500 ns
to Next Conversion (Note 4) See Graph
Slew Rate, Tracking 0.1 V/µs
C

VIN

, Analog Input Capacitance 45 pF

C

OUT

, Logic Output Capacitance 5 pF

C

IN

, Logic Input Capacitance 5 pF

Note 1: Absolute MaximumRatings indicate limitsbeyond which damageto the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4: Accuracy may degrade if t

WR

or tRDis shorter than the minimum value specified. See Accuracy vs tWRand Accuracy vs tRDgraphs.

Note 5: When the input voltage (V

IN

) at any pin exceeds the power supply rails (V

IN

<

V−or V

IN

>

V+) the absolute value of current at that pin should be limited

to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries witha1mAcurrent limit to four.

Note 6: Typicals are at 25˚C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF discharaged through a 1.5 kΩ resistor.

ADC0820

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TRI-STATE Test Circuits and Waveforms

Timing Diagrams

t

1H

DS005501-3

DS005501-4

tr=20 ns

t

0H

DS005501-5

DS005501-6

tr=20 ns

DS005501-7

Note: On power-up the state of INT can be high or low.

FIGURE 2. RD Mode (Pin 7 is Low)

ADC0820

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Timing Diagrams (Continued)

DS005501-8

FIGURE 3. WR-RD Mode (Pin 7 is High and t

RD

<

tI)

DS005501-9

FIGURE 4. WR-RD Mode (Pin 7 is High and t

RD

>

tI)

DS005501-10

FIGURE 5. WR-RD Mode (Pin 7 is High)

Stand-Alone Operation

ADC0820

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Typical Performance Characteristics

Logic Input Threshold
Voltage vs Supply Voltage

DS005501-34

Conversion Time (RD Mode)
vs Temperature

DS005501-35

Power Supply Current vs
Temperature (not including
reference ladder)

DS005501-36

Accuracy vs t

WR

DS005501-37

Accuracy vs t

RD

DS005501-38

Accuracy vs t

p

DS005501-39

Accuracy vs V

REF

[V

REF=VREF

(+)-V

REF

(-)]

DS005501-40

tI, Internal Time Delay vs
Temperature

DS005501-41

Output Current vs
Temperature

DS005501-42

ADC0820

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Description of Pin Functions

Pin Name Function

1V

IN

Analog input; range =GND≤VIN≤V

CC

2 DB0 TRI-STATE data output—bit 0 (LSB)
3 DB1 TRI-STATE data output—bit 1
4 DB2 TRI-STATE data output—bit 2
5 DB3 TRI-STATE data output—bit 3
6WR

/RDY

WR-RD Mode
WR: With CS low, the conversion is

started on the falling edge of WR.
Approximately 800 ns (the preset internal
time out, t

I

) after the WR rising edge, the
result of the conversion will be strobed
into the output latch, provided that RD
does not occur prior to this time out (see

Figures 3, 4

).

RD Mode
RDY: This is an open drain output (no

internal pull-up device). RDY will go low
after the falling edge of CS; RDY will go
TRI-STATE when the result of the
conversion is strobed into the output
latch. It is used to simplify the interface
to a microprocessor system (see

Figure

2

).

7 Mode Mode: Mode selection input—it is

internally tied to GND through a 50 µA
current source.

RD Mode: When mode is low
WR-RD Mode: When mode is high

8RD

WR-RD Mode

With CS low, the TRI-STATE data
outputs (DB0-DB7) will be activated
when RD goes low (see

Figure 5

). RD
can also be used to increase the speed
of the converter by reading data prior to
the preset internal time out (t

I

, ∼800 ns).
If this is done, the data result transferred
to output latch is latched after the falling
edge of the RD (see

Figures 3, 4

).

RD Mode

With CS low, the conversion will start
with RD going low, also RD will enable
the TRI-STATE data outputs at the
completion of the conversion. RDY going
TRI-STATE and INT going low indicates
the completion of the conversion (see

Figure 2

).

Pin Name Function

9 INT

WR-RD Mode

INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT will go
low, ∼800 ns (the preset internal time
out, t

I

) after the rising edge of WR (see

Figure 4

); or INT will go low after the
falling edge of RD , if RD goes low prior
to the 800 ns time out (see

Figure 3

).
INT is reset by the rising edge of RD or
CS (see

Figures 3, 4

).

RD Mode

INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT is reset
by the rising edge of RD or CS (see

Figure 2

).
10 GND Ground
11 V

REF

(−) The bottom of resistor ladder, voltage

range: GND≤V

REF

(−)≤V

REF

(+) (Note 5)

12 V

REF

(+) The top of resistor ladder, voltage range:

V

REF

(−)≤V

REF

(+)≤VCC(Note 5)

13 CS

CS must be low in order for the RD or

WR to be recognized by the converter.
14 DB4 TRI-STATE data output—bit 4
15 DB5 TRI-STATE data output—bit 5
16 DB6 TRI-STATE data output—bit 6
17 DB7 TRI-STATE data output—bit 7 (MSB)
18 OFL

Overflow output —If the analog input is

higher than the V

REF

(+), OFL will be low
at the end of conversion. It can be used
to cascade 2 or more devices to have
more resolution (9, 10-bit). This output is
always active and does not go into
TRI-STATE as DB0–DB7 do.

19 NC No connection
20 V

CC

Power supply voltage

1.0 Functional Description

1.1 GENERAL OPERATION

The ADC0820 uses two 4-bit flash A/D converters to make
an 8-bit measurement (

Figure 1

). Each flash ADC is made
up of 15 comparators which compare the unknown input to a
reference ladder to get a 4-bit result. To take a full 8-bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4

MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.

The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor

ADC0820

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1.0 Functional Description (Continued)

ladder for the A/D as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
which most closely approximates the analog input. In addi­tion, the “sampled-data” comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.

1.2 THE SAMPLED-DATA COMPARATOR

Each comparator in the ADC0820 consists of a CMOS in­verter with a capacitively coupled input (

Figures 6, 7

). Ana­log switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverter’s input and out­put. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the com­parator, and another for making the comparison.

In the first cycle, one input switch and the inverter’sfeedback
switch (

Figure 6

) are closed. In this interval, C is charged to

the connected input (V1) less the inverter’s bias voltage (V

B

,

approximately 1.2V). In the second cycle (

Figure 7

), these
two switches are opened and the other (V2) input’s switch is
closed. The input capacitor now subtracts its stored voltage
from the second input and the difference is amplified by the
inverter’s open loop gain. The inverter’s input (V

B

') becomes

and the output will go high or low depending on the sign of
V

B

'−VB.

The actual circuitry used in the ADC0820 is a simple but
important expansion of the basic comparator described
above. By adding a second capacitor and another set of
switches to the input (

Figure 8

), the scheme can be ex­panded to make dual differential comparisons. In thiscircuit,
the feedback switch and one input switch on each capacitor
(Z switches) are closed in the zeroing cycle. A comparison is

then made by connecting the second input on each capacitor
and opening all of the other switches (S switches). The
change in voltage at the inverter’s input, as a result of the
change in charge on each input capacitor, will now depend
on both input signal differences.

1.3 ARCHITECTURE

In the ADC0820, one bank of 15 comparators is used in each
4-bit flash A/D converter (

Figure 12

). The MS (most signifi­cant) flash ADC also has one additional comparator to detect
input overrange. These two sets of comparators operate
alternately,with one group in its zeroing cycle while the other
is comparing.

When a typical conversion is started, the WR line is brought
low. At this instant the MS comparators go from zeroing to
comparison mode (

Figure 11

). When WR is returned high

after at least 600 ns, the output from the first set of compara­tors (the first flash) is decoded and latched.At this point the
two 4-bit converters change modes and the LS (least signifi­cant) flash ADC enters its compare cycle. No less than 600
ns later, the RD line may be pulled low to latch the lower 4
data bits and finish the 8-bit conversion. When RD goes low,
the flash A/Ds change state once again in preparation for the
next conversion.

Figure 11

also outlines how the converter’s interface timing

relates to its analog input (V

IN

). In WR-RD mode, VINis

DS005501-12

•

VO=V

B

•

V on C = V1−V

B

•

CS= stray input node capacitor

•

VB= inverter input bias voltage

Zeroing Phase

FIGURE 6. Sampled-Data Comparator

DS005501-13

Compare Phase

FIGURE 7. Sampled-Data Comparator

DS005501-14

DS005501-45

FIGURE 8. ADC0820 Comparator (from MS Flash ADC)

ADC0820

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1.0 Functional Description (Continued)

measured while WR is low. In RD mode, sampling occurs
during the first 800 ns of RD. Because of the input connec­tions to the ADC0820’s LS and MS comparators, the con­verter has the ability to sample V

IN

at one instant (Section

2.4), despite the fact that two separate 4-bit conversions are
being done. More specifically, when WR is low the MS flash
is in compare mode (connected to VIN), and the LS flash is in
zero mode (also connected to V

IN

). Therefore both flash

ADCs sample V

IN

at the same time.

1.4 DIGITAL INTERFACE

The ADC0820 has two basic interface modes which are
selected by strapping the MODE pin high or low.

RD Mode

With the MODE pin grounded, the converter is set to Read
mode. In this configuration, a complete conversion is done
by pulling RD low until output data appears. An INT line is
provided which goes low at the end of the conversion as well
as a RDY output which can be used to signal a processor
that the converter is busy or can also serve as a system
Transfer Acknowledge signal.

When in RD mode, the comparator phases are internally
triggered. At the falling edge of RD, the MS flash converter
goes from zero to compare mode and the LS ADC’s com­parators enter their zero cycle. After 800 ns, data from the
MS flash is latched and the LS flash ADC enters compare
mode. Following another 800 ns, the lower 4 bits are recov­ered.

WR then RD Mode

With the MODE pin tied high, the A/D will be set up for the
WR-RD mode. Here, a conversion is started with the WR
input; however, there are two options for reading the output
data which relate to interface timing. If an interrupt driven
scheme is desired, the user can wait for INT to go low before
reading the conversion result (

Figure 10

). INT will typically

go low 800 ns after WR’s rising edge. However, if a shorter
conversion time is desired, the processor need not wait for
INT and can exercise a read after only 600 ns (

Figure 9

). If
this is done, INT will immediately go low and data will appear
at the outputs.

Stand-Alone

For stand-alone operation in WR-RD mode, CS and RD can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WR’s rising
edge.

RD Mode (Pin 7 is Low)

DS005501-16

DS005501-17

FIGURE 9. WR-RD Mode (Pin 7 is High and t

RD

<

tI)

DS005501-18

FIGURE 10. WR-RD Mode (Pin 7 is High and t

RD

>

tI)

WR-RD Mode (Pin 7 is High) Stand-Alone Operation

DS005501-19

ADC0820

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1.0 Functional Description (Continued)

OTHER INTERFACE CONSIDERATIONS

In order to maintain conversion accuracy, WR has a maxi­mum width spec of 50 µs. When the MS flash ADC’s
sampled-data comparators (Section 1.2) are in comparison
mode (WR is low), the input capacitors (C,

Figure 8

) must
hold their charge. Switch leakage and inverter bias current
can cause errors if the comparator is left in this phase for too
long.

Since the MS flash ADC enters its zeroing phase at the end
of a conversion (Section 1.3), a new conversion cannot be
started until this phase is complete. The minimum spec for
this time (t

P

,

Figures 2, 3, 4, 5

) is 500 ns.

DS005501-20

Note: MS means most significant
LS means least significant

FIGURE 11. Operating Sequence (WR-RD Mode)

ADC0820

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Detailed Block Diagram

DS005501-15

FIGURE 12.

ADC0820

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2.0 Analog Considerations

2.1 REFERENCE AND INPUT

The two V

REF

inputs of the ADC0820 are fully differential and
define the zero to full-scale input range of the A to D con­verter.This allows the designer to easily vary the span of the
analog input since this range will be equivalent to the voltage
difference between V

IN

(+) and VIN(−). By reducing

V

REF(VREF=VREF

(+)−V

REF

(−)) to less than 5V,the sensitivity

of the converter can be increased (i.e., if V

REF

=2V then 1
LSB=7.8 mV). The input/reference arrangement also facili­tates ratiometric operation and in many cases the chip power
supply can be used for transducer power as well as the V

REF

source.
This reference flexibility lets the input span not only be varied

but also offset from zero. The voltage at V

REF

(−) sets the
input level which produces a digital output of all zeroes.
Though V

IN

is not itself differential, the reference design
affords nearly differential-input capability for most measure­ment applications.

Figure 13

shows some of the configura-

tions that are possible.

2.2 INPUT CURRENT

Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The A/D’s sampled-data com­parators take varying amounts of input current depending on
which cycle the conversion is in.

The equivalent input circuit of the ADC0820 is shown in

Figure 14

. When a conversion starts (WR low, WR-RD
mode), all input switches close, connecting VINto thirty-one
1 pF capacitors. Although the two 4-bit flash circuits are not
both in their compare cycle at the same time, V

IN

still sees all
input capacitors at once. This is because the MS flash
converter is connected to the input during its compare inter­val and the LS flash is connected to the input during its
zeroing phase (Section 1.3). In other words, the LS ADC
uses V

IN

as its zero-phase input.

The input capacitors must charge to the input voltage
through the on resistance of the analog switches (about 5 kΩ
to 10 kΩ). In addition, about 12 pF of input stray capacitance
must also be charged. For large source resistances, the
analog input can be modeled as an RCnetwork as shown in

Figure 15

.AsRSincreases, it will take longer for the input

capacitance to charge.
In RD mode, the input switches are closed for approximately

800 ns at the start of the conversion. In WR-RD mode, the
time that the switches are closed to allow this charging is the
time that WR is low. Since other factors force this time to be
at least 600 ns, input time constants of 100 ns can be
accommodated without special consideration. Typical total
input capacitance values of 45 pF allow R

S

to be 1.5 kΩ

without lengthening WR to give V

IN

more time to settle.

External Reference 2.5V Full-Scale

DS005501-21

Power Supply as Reference

DS005501-22

Input Not Referred to GND

DS005501-23

FIGURE 13. Analog Input Options

ADC0820

www.national.com 14

2.0 Analog Considerations (Continued)

2.3 INPUT FILTERING

It should be made clear that transients in the analog input
signal, caused by charging current flowing into V

IN

, will not
degrade the A/D’s performance in most cases. In effect the
ADC0820 does not “look” at the input when these transients
occur.The comparators’ outputs are not latched while WR is
low, so at least 600 ns will be provided to charge the ADC’s
input capacitance. It is therefore not necessary to filter out
these transients by putting an external cap on the V

IN

termi-

nal.

2.4 INHERENT SAMPLE-HOLD

Another benefit of the ADC0820’s input mechanism is its
ability to measure a variety of high speed signals without the
help of an external sample-and-hold. In a conventional SAR
type converter, regardless of its speed, the input must re­main at least

1

⁄2LSB stable throughout the conversion pro­cess if full accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally
sampled, and held stationary during the conversion.

Sampled-data comparators, by nature of their input switch­ing, already accomplish this function to a large degree (Sec­tion 1.2). Although the conversion time for the ADC0820 is

1.5 µs, the time through which V

IN

must be1⁄2LSB stable is

much smaller. Since the MS flash ADC uses V

IN

as its

“compare” input and the LS ADC uses V

IN

as its “zero” input,

the ADC0820 only “samples” V

IN

when WR is low (Sections

1.3 and 2.2). Even though the two flashes are not done
simultaneously,the analog signal is measured at one instant.
The value of V

IN

approximately 100 ns after the rising edge
of WR (100 ns due to internal logic prop delay) will be the
measured value.

Input signals with slew rates typically below 100 mV/µs can
be converted without error. However, because of the input
time constants, and charge injection through the opened
comparator input switches, faster signals may cause errors.
Still, the ADC0820’s loss in accuracy for a given increase in
signal slope is far less than what would be witnessed in a
conventional successive approximation device. An SAR type
converter with a conversion time as fast as 1 µs would still
not be able to measure a 5V 1 kHz sine wave without the aid
of an external sample-and-hold. The ADC0820, with no such
help, can typically measure 5V, 7 kHz waveforms.

DS005501-24

FIGURE 14.

DS005501-25

FIGURE 15.

ADC0820

www.national.com15

3.0 Typical Applications

8-Bit Resolution Configuration

DS005501-26

9-Bit Resolution Configuration

DS005501-27

ADC0820

www.national.com 16

3.0 Typical Applications (Continued)

Telecom A/D Converter

DS005501-28

•

VIN=3 kHz max±4V

P

•

No track-and-hold needed

•

Low power consumption

Multiple Input Channels

DS005501-29

8-Bit 2-Quadrant Analog Multiplier

DS005501-30

ADC0820

www.national.com17

3.0 Typical Applications (Continued)

Fast Infinite Sample-and-Hold

DS005501-31

ADC0820

www.national.com 18

3.0 Typical Applications (Continued)

Digital Waveform Recorder

DS005501-32

ADC0820

www.national.com19

Physical Dimensions inches (millimeters) unless otherwise noted

Hermetic Dual-In-Line Package (J)

Order Number ADC0820CCJ

NS Package Number J20A

ADC0820

www.national.com 20

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

SO Package (M)

Order Number ADC0820BCWM, ADC0820CCWM or ADC0820CIWM

NS Package Number M20B

Molded Dual-In-Line Package (N)

Order Number ADC0820BCN or ADC0820CCN

NS Package Number N20A

ADC0820

www.national.com21

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.

2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.

National Semiconductor
Corporation

Americas
Email: [e-mail]

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Europe

Fax: [phone]

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Tel: [phone]
Fax: [phone]

www.national.com

Molded Chip Carrier Package (V)

Order Number ADC0820BCV

NS Package Number V20A

ADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold Function

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.