NSC ADC08200CIMTX Datasheet
ADC08200
8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D
Converter
General Description
The ADC08200 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use,
this product operates at conversion rates up to 230 MSPS
while consuming just 1.05 mW per MHz of clock frequency,
or 210 mW at 200 MSPS. Raising the PD pin puts the
ADC08200 into a Power Down mode where it consumes
1mW.
The unique architecture achieves 7.3 Effective Bits with
50 MHz input frequency. The ADC08200 is resistant to
latch-up and the outputs are short-circuit proof. The top and
bottom of the ADC08200’s reference ladder are available for
connections, enabling a wide range of input possibilities. The
digital outputs are TTL/CMOS compatible with a separate
output power supply pin to support interfacing with 3V or
2.5V logic. The digital inputs (CLK and PD) are TTL/CMOS
compatible.
The ADC08200 is offered in a 24-lead plastic package
(TSSOP) and is specified over the industrial temperature
range of −40˚C to +85˚C.
Features
n Single-ended input
n Internal sample-and-hold function
n Low voltage (single +3V) operation
n Small package
n Power-down feature
Key Specifications
j
Resolution: 8 bits
j
Maximum sampling frequency: 200 MSPS (min)
j
DNL:
±
0.4 LSB (typ)
j
ENOB (fIN= 50 MHz): 7.3 bits (typ)
j
THD (fIN= 50 MHz): −61 dB (typ)
j
No missing codes Guaranteed
j
Power Consumption
Operating 1.05 mW/MSPS (typ)
Power down 1 mW (typ)
Applications
n Flat panel displays
n Projection systems
n Set-top boxes
n Battery-powered instruments
n Communications
n Medical scan converters
n X-ray imaging
n High speed viterbi decoders
n Astronomy
Pin Configuration
20017901
November 2002
ADC08200 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter
© 2002 National Semiconductor Corporation DS200179 www.national.com
Ordering Information
ADC08200CIMT TSSOP
ADC08200CIMTX TSSOP (tape and reel)
Block Diagram
20017902
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
6V
IN
Analog signal input. Conversion range is VRBto VRT.
3V
RT
Analog Input that is the high (top) side of the reference
ladder of the ADC. Nominal range is 0.5V to V
A
. Voltage
on V
RT
and VRBinputs define the VINconversion range.
Bypass well. See Section 2.0 for more information.
9V
RM
Mid-point of the reference ladder. This pin should be
bypassed to a quiet point in the analog ground plane with
a 0.1 µF capacitor.
10 V
RB
Analog Input that is the low side (bottom) of the
reference ladder of the ADC. Nominal range is 0.0V to
(V
RT
– 0.5V). Voltage on VRTand VRBinputs define the
V
IN
conversion range. Bypass well. See Section 2.0 for
more information.
ADC08200
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
23 PD
Power Down input. When this pin is high, the converter is
in the Power Down mode and the data output pins hold
the last conversion result.
24 CLK
CMOS/TTL compatible digital clock Input. V
IN
is sampled
on the rising edge of CLK input.
13 thru 16
and
19 thru 22
D0–D7
Conversion data digital Output pins. D0 is the LSB, D7 is
the MSB. Valid data is output just after the rising edge of
the CLK input.
7V
IN
GND Reference ground for the single-ended analog input, VIN.
1, 4, 12 V
A
Positive analog supply pin. Connect to a quiet voltage
source of +3V. V
A
should be bypassed with a 0.1 µF
ceramic chip capacitor for each pin, plus one
10 µF capacitor. See Section 3.0 for more information.
18 V
DR
Power supply for the output drivers. If connected to VA,
decouple well from V
A
.
17 DR GND The ground return for the output driver supply.
2, 5, 8, 11 AGND The ground return for the analog supply.
ADC08200
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Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
A
) 3.8V
Driver Supply Voltage (V
DR
)V
A
+0.3V
Voltage on Any Input or Output Pin −0.3V to V
A
Reference Voltage (VRT,VRB)V
A
to AGND
CLK, PD Voltage Range −0.05V to
(V
A
+ 0.05V)
Input Current at Any Pin (Note 3)
±
25 mA
Package Input Current (Note 3)
±
50 mA
Power Dissipation at T
A
= 25˚C See (Note 4)
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
2500V
200V
Soldering Temperature, Infrared,
10 seconds (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range −40˚C ≤ T
A
≤ +85˚C
Supply Voltage (V
A
) +2.7V to +3.6V
Driver Supply Voltage (V
DR
) +2.4V to V
A
Ground Difference |GND - DR GND| 0V to 300 mV
Upper Reference Voltage (V
RT
) 0.5V to (VA−0.3V)
Lower Reference Voltage (V
RB
) 0Vto(VRT−0.5V)
V
IN
Voltage Range VRBto V
RT
Converter Electrical Characteristics
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 5 pF, f
CLK
= 200 MHz at 50% duty
cycle. Boldface limits apply for T
A=TMIN
to T
MAX
: all other limits TA= 25˚C (Notes 7, 8)
Symbol Parameter Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
DC ACCURACY
INL Integral Non-Linearity
+1.0
−0.3
+1.9
−1.2
LSB (max)
LSB (min)
DNL Differential Non-Linearity
±
0.4
±
0.95 LSB (max)
Missing Codes 0 (max)
FSE Full Scale Error 36 50 mV (max)
V
OFF
Zero Scale Offset Error 46 60 mV (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
V
IN
Input Voltage 1.6
V
RB
V (min)
V
RT
V (max)
C
IN
VINInput Capacitance
V
IN
= 0.75V +0.5
Vrms
(CLK LOW) 3 pF
(CLK HIGH) 4 pF
R
IN
RINInput Resistance
>
1MΩ
BW Full Power Bandwidth 500 MHz
V
RT
Top Reference Voltage 1.9
V
A
V (max)
0.5 V (min)
V
RB
Bottom Reference Voltage 0.3
V
RT
− 0.5 V (max)
0 V (min)
R
REF
Reference Ladder Resistance VRTto V
RB
160
120 Ω (min)
200 Ω (max)
CLK, PD DIGITAL INPUT CHARACTERISTICS
V
IH
Logical High Input Voltage VDR=VA= 3.6V 2.0 V (min)
V
IL
Logical Low Input Voltage VDR=VA= 2.7V 0.8 V (max)
I
IH
Logical High Input Current VIH=VDR=VA= 3.6V 10 nA
I
IL
Logical Low Input Current VIL= 0V, VDR=VA= 2.7V −50 nA
C
IN
Logic Input Capacitance 3 pF
DIGITAL OUTPUT CHARACTERISTICS
V
OH
High Level Output Voltage VA=VDR= 2.7V, IOH= −400 µA 2.6 2.4 V (min)
V
OL
Low Level Output Voltage VA=VDR= 2.7V, IOL= 1.0 mA 0.4 0.5 V (max)
ADC08200
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 5 pF, f
CLK
= 200 MHz at 50% duty
cycle. Boldface limits apply for T
A=TMIN
to T
MAX
: all other limits TA= 25˚C (Notes 7, 8)
Symbol Parameter Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
DYNAMIC PERFORMANCE
ENOB Effective Number of Bits
f
IN
= 4 MHz, VIN= FS − 0.25 dB 7.5 Bits
f
IN
= 20 MHz, VIN= FS − 0.25 dB 7.4 Bits
f
IN
= 50 MHz, VIN= FS − 0.25 dB 7.3 6.9 Bits (min)
f
IN
= 70 MHz, VIN= FS − 0.25 dB 7.2 Bits
f
IN
= 100 MHz, VIN= FS − 0.25 dB 7.0 Bits
SINAD Signal-to-Noise & Distortion
f
IN
= 4 MHz, VIN= FS − 0.25 dB 47 dB
f
IN
= 20 MHz, VIN= FS − 0.25 dB 46 dB
f
IN
= 50 MHz, VIN= FS − 0.25 dB 46 43.3 dB (min)
f
IN
= 70 MHz, VIN= FS − 0.25 dB 45 dB
f
IN
= 100 MHz, VIN= FS − 0.25 dB 44 dB
SNR Signal-to-Noise Ratio
f
IN
= 4 MHz, VIN= FS − 0.25 dB 47 dB
f
IN
= 20 MHz, VIN= FS − 0.25 dB 46 dB
f
IN
= 50 MHz, VIN= FS − 0.25 dB 46 43.4 dB (min)
f
IN
= 70 MHz, VIN= FS − 0.25 dB 45 dB
f
IN
= 100 MHz, VIN= FS − 0.25 dB 44 dB
SFDR Spurious Free Dynamic Range
f
IN
= 4 MHz, VIN= FS − 0.25 dB 60 dBc
f
IN
= 20 MHz, VIN= FS − 0.25 dB 58 dBc
f
IN
= 50 MHz, VIN= FS − 0.25 dB 60 dBc
f
IN
= 70 MHz, VIN= FS − 0.25 dB 57 dBc
f
IN
= 100 MHz, VIN= FS − 0.25 dB 54 dBc
THD Total Harmonic Distortion
f
IN
= 4 MHz, VIN= FS − 0.25 dB −60 dBc
f
IN
= 20 MHz, VIN= FS − 0.25 dB −58 dBc
f
IN
= 50 MHz, VIN= FS − 0.25 dB −60 dBc
f
IN
= 70 MHz, VIN= FS − 0.25 dB -56 dBc
f
IN
= 100 MHz, VIN= FS − 0.25 dB −53 dBc
HD2 2nd Harmonic Distortion
f
IN
= 4 MHz, VIN= FS − 0.25 dB −66 dBc
f
IN
= 20 MHz, VIN= FS − 0.25 dB -68 dBc
f
IN
= 50 MHz, VIN= FS − 0.25 dB −66 dBc
f
IN
= 70 MHz, VIN= FS − 0.25 dB -60 dBc
f
IN
= 100 MHz, VIN= FS − 0.25 dB −55 dBc
HD3 3rd Harmonic Distortion
f
IN
= 4 MHz, VIN= FS − 0.25 dB −72 dBc
f
IN
= 20 MHz, VIN= FS − 0.25 dB −58 dBc
f
IN
= 50 MHz, VIN= FS − 0.25 dB −72 dBc
f
IN
= 70 MHz, VIN= FS − 0.25 dB -58 dBc
f
IN
= 100 MHz, VIN= FS − 0.25 dB −60 dBc
IMD Intermodulation Distortion
f
1
= 11 MHz, VIN= FS − 6.25 dB
f
2
= 12 MHz, VIN= FS − 6.25 dB
-55 dBc
POWER SUPPLY CHARACTERISTICS
I
A
Analog Supply Current
DC Input 69.75 86 mA (max)
f
IN
= 10 MHz, VIN=FS−3dB 69.75 mA (max)
I
DR
Output Driver Supply Current DC Input, PD = Low 0.25 0.6 mA (max)
I
A+IDR
Total Operating Current
DC Input, PD = Low 70 86.6 mA (max)
CLK Low, PD = Hi 0.3 mA
PC Power Consumption DC Input, Excluding Reference 210 260 mW (max)
PSRR
1
Power Supply Rejection Ratio
FSE change with 2.7V to 3.3V change
in V
A
54 dB
ADC08200
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 5 pF, f
CLK
= 200 MHz at 50% duty
cycle. Boldface limits apply for T
A=TMIN
to T
MAX
: all other limits TA= 25˚C (Notes 7, 8)
Symbol Parameter Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
AC ELECTRICAL CHARACTERISTICS
f
C1
Maximum Conversion Rate 230 200 MHz (min)
f
C2
Minimum Conversion Rate 10 MHz
t
CL
Minimum Clock Low Time 0.87 1.0 ns (min)
t
CH
Minimum Clock High Time 0.65 0.75 ns (min)
t
OH
Output Hold Time CLK to Data Invalid 2.1 ns
t
OD
Output Delay CLK to Data Transition 3.5
2.5 ns (min)
5 ns (max)
Pipeline Delay (Latency) 6 Clock Cycles
t
AD
Sampling (Aperture) Delay CLK Rise to Acquisition of Data 2.6 ns
t
AJ
Aperture Jitter 2 ps rms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less thanAGND or DR GND, or greater than V
A
or VDR), the current at that pin should
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperature (T
J
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θ
JA
), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/θJA. In the 24-pin
TSSOP, θ
JA
is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 435 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
this device under normal operation will typically be about 245 mW (205 mW quiescent power + 16 mW reference ladder power + 24 mW to drive the output bus
capacitance). The values for maximum power dissipation listed above will be reached only when the ADC08200 is operated in a severe fault condition (e.g., when
input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to V
A
+ 300 mV or to 300 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if the input goes above V
DR
or below GND by more than 100 mV. For example, if VAis 2.7VDCthe full-scale input
voltage must be ≤2.8V
DC
to ensure accurate conversions.
20017907
Note 8: To guarantee accuracy, it is required that VAand VDRbe well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at T
J
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
ADC08200
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