NSC ADC0819CIN, ADC0819CCVX, ADC0819CCV, ADC0819BCVX, ADC0819BCN Datasheet

TL/H/9287

ADC0819 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer

December 1994

ADC0819 8-Bit Serial I/O A/D Converter
with 19-Channel Multiplexer

General Description

The ADC0819 is an 8-Bit successive approximation A/D
converter with simultaneous serial I/O. The serial input con­trols an analog multiplexer which selects from 19 input
channels or an internal half scale test voltage.

An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator. This allows
the input signal to vary during the conversion cycle.

Separate serial I/O and conversion clock inputs are provid­ed to facilitate the interface to various microprocessors.

Features

Y

Separate asynchronous converter clock and serial data
I/O clock.

Y

19-Channel multiplexer with 5-Bit serial address logic.

Y

Built-in sample and hold function.

Y

Ratiometric or absolute voltage referencing.

Y

No zero or full-scale adjust required.

Y

Internally addressable test voltage.

Y

0V to 5V input range with single 5V power supply.

Y

TTL/MOS input/output compatible.

Y

28-pin molded chip carrier or 28-pin molded DIP

Key Specifications

Y

Resolution 8-Bits

Y

Total unadjusted error

g

(/2LSB andg1LSB

Y

Single supply 5V

DC

Y

Low Power 15 mW

Y

Conversion Time 16 ms

Connection Diagrams

Molded Chip Carrier (PCC) Package

TL/H/9287– 1

Top View

Order Number ADC0819BCV, CCV

See NS Package Number V28A

Dual-In-Line Package

TL/H/9287– 20

Top View

Order Number ADC0819BCN, CIN

See NS Package Number N28B

Functional Diagram

TL/H/9287– 2

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

CC

) 6.5V

Voltage

Inputs and Outputs

b

0.3V to V

CC

a

0.3V

Input Current Per Pin (Note 3)

g

5mA

Total Package Input Current (Note 3)

g

20mA

Storage Temperature

b

65§Ctoa150§C

Package Dissipation at T

A

e

25§C 875 mW

Lead Temperature (Soldering, 10 sec.)

Dual-In-Line Package (Plastic) 260

§

C

Surface Mount Package

Vapor Phase (60 sec.) 215

§

C

Infrared (15 sec.) 220

§

C

ESD Susceptibility (Note 11) 2000V

Operating Ratings (Notes1&2)

Supply Voltage (VCC) 4.5 VDCto 6.0 V

DC

Temperature Range T

MIN

s

T

A

s

T

MAX

ADC0819BCV, ADC0819CCV

b

40§CsT

A

s

a

85§C

ADC0819BCN 0§CsT

A

s

a

70§C

ADC0819CIN

b

40§CsT

A

s

a

85§C

Electrical Characteristics

The following specifications apply for V

CC

e

5V, V

REF

e

5V, w

2 CLK

e

2.097 MHz unless otherwise specified. Boldface limits

apply from T

MIN

to T

MAX

; all other limits T

A

e

T

J

e

25§C.

Typical

Tested Design

Parameter Conditions

(Note 6)

Limit Limit Units

(Note 7) (Note 8)

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Maximum Total V

REF

e

5.00 V

DC

Unadjusted Error (Note 4)
ADC0819BCV, BCN

g

(/2

g

(/2 LSB

ADC0819CCV, CIN

g

1

g

1 LSB

Minimum Reference

8 5 kX

Input Resistance

Maximum Reference

811 11 kX

Input Resistance

Maximum Analog Input Range (Note 5) V

CC

a

0.05 V

CC

a

0.05 V

Minimum Analog Input Range GNDb0.05 GNDb0.05 V

On Channel Leakage Current (Note 9)

On Channel

e

5V 400 1000 nA

Off Channel

e

0V

On Channele0V

b

400

b

1000 nA

Off Channel

e

5V

(Note 9)

Off Channel Leakage Current (Note 9)

On Channel

e

5V

b

400

b

1000 nA

Off Channel

e

0V

On Channele0V 400 1000 nA
Off Channel

e

5V

(Note 9)

Minimum V

TEST

V

REF

e

VCC, (Note 10)

Internal Test Voltage CH 19 Selected 125 125 Counts

Maximum V

TEST

V

REF

e

VCC, (Note 10)

Internal Test Voltage CH 19 Selected 130 130 Counts

DIGITAL AND DC CHARACTERISTICS

V

IN(1)

, Logical ‘‘1’’ Input V

CC

e

5.25V

2.0 2.0 V

Voltage (Min)

V

IN(0)

, Logical ‘‘0’’ Input V

CC

e

4.75V

0.8 0.8 V

Voltage (Max)

I

IN(1)

, Logical ‘‘1’’ Input V

IN

e

5.0V 0.005

2.5 2.5 mA

Current (Max)

I

IN(0)

, Logical ‘‘0’’ Input V

IN

e

0V

b

0.005

b

2.5

b

2.5 mA

Current (Max)

2

Electrical Characteristics (Continued)

The following specifications apply for V

CC

e

5V, V

REF

e

5V, w

2 CLK

e

2.097 MHz unless otherwise specified. Boldface limits

apply from T

MIN

to T

MAX

; all other limits T

A

e

T

J

e

25§C.

Typical

Tested Design

Parameter Conditions

(Note 6)

Limit Limit Units

(Note 7) (Note 8)

DIGITAL AND DC CHARACTERISTICS (Continued)

V

OUT(1)

, Logical ‘‘1’’ V

CC

e

4.75V

Output Voltage (Min) I

OUT

eb

360 mA 2.4 2.4 V

I

OUT

eb

10 mA 4.5 4.5 V

V

OUT(0)

, Logical ‘‘0’’ V

CC

e

5.25V

0.4 0.4 V

Output Voltage (Max) I

OUT

e

1.6 mA

I

OUT

, TRI-STATE Output V

OUT

e

0V

b

0.01

b

3

b

3 mA

Current (Max) V

OUT

e

5V 0.01 3 3 mA

I

SOURCE

, Output Source V

OUT

e

0V

b

14

b

6.5

b

6.5 mA

Current (Min)

I

SINK

, Output Sink Current (Min) V

OUT

e

V

CC

16 8.0 8.0 mA

ICC, Supply Current (Max) CSe1, V

REF

Open 1 2.5 2.5 mA

I

REF

(Max) V

REF

e

5V 0.7 1 1 mA

AC CHARACTERISTICS

Tested Design

Parameter Conditions Typical Limit Limit Units

(Note 6) (Note 7) (Note 8)

w

2 CLK

, w2Clock Frequency MIN 0.70 1.0

MHz

MAX 4.0 2.0 2.1

S

CLK

, Serial Data Clock MIN 5.0

KHz

Frequency

MAX 1000 525 525

TC, Conversion Process Time MIN Not Including MUX 26 26 w2cycles

Addressing and

MAX

Analog Input

32 32

Sampling Times

t

ACC

, Access Time Delay From CS MIN 1 w2cycles

Falling Edge to DO Data Valid MAX 3

t

SET-UP

, Minimum Set-up Time of CS Falling

4/w

2CLK

a

1

2S

CLK

sec

Edge to S

CLK

Rising Edge

t

HCS

,CSHold Time After the Falling

0 ns

Edge of S

CLK

tCS, Total CS Low Time MIN t

set-up

a

8/S

CLK

sec

MAX tCS(min)a26/w

2CLK

sec

t

HDI

, Minimum DI Hold Time from

0 0 ns

S

CLK

Rising Edge

t

HDO

, Minimum DO Hold Time from S

CLK

R

L

e

30k,

10 ns

Falling Edge C

L

e

100 pF

t

SDI

, Minimum DI Set-up Time to S

CLK

200 400 ns

Rising Edge

t

DDO

, Maximum Delay From S

CLK

R

L

e

30k,

180 200 250 ns

Falling Edge to DO Data Valid C

L

e

100 pF

t

TRI

, Maximum DO Hold Time, R

L

e

3k,

90 150 150 ns

(CS

Rising edge to DO TRI-STATE) C

L

e

100 pF

3

Electrical Characteristics The following specifications apply for V

CC

e

5V, t

r

e

t

f

e

20 ns, V

REF

e

5V, unless

otherwise specified. Boldface limits apply from T

MIN

to T

MAX

; all other limits T

A

e

T

J

e

25§C.

Typical

Tested Design

Parameter Conditions

(Note 6)

Limit Limit Units

(Note 7) (Note 8)

AC CHARACTERISTICS (Continued)

tCA, Analog After Address Is Latched

3/S

CLK

a

1 ms sec

Sampling Time CS

e

Low

t

RDO

, Maximum DO R

L

e

30 kX, ‘‘TRI-STATE’’ to ‘‘HIGH’’ State 75 150 150

ns

Rise Time C

L

e

100 pf ‘‘LOW’’ to ‘‘HIGH’’ State 150 300 300

t

FDO

, Maximum DO R

L

e

30 kX, ‘‘TRI-STATE’’ to ‘‘LOW’’ State 75 150 150

ns

Fall Time C

L

e

100 pf ‘‘HIGH’’ to ‘‘LOW’’ State 150 300 300

CIN, Maximum Input Analog Inputs, ANO–AN10 and V

REF

11 55

pF

Capacitance All Others 5 15

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to ground.

Note 3: Under over voltage conditions (V

IN

k

0V and V

IN

l

VCC) the maximum input current at any one pin isg5 mA. If the voltage at more than one pin exceeds

V

CC

a

.3V the total package current must be limited to 20 mA. For example the maximum number of pins that can be over driven at the maximum current level of

g

5 mA is four.

Note 4: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.

Note 5: Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop

greater than V

CC

supply. Be careful during testing at low VCClevels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at
elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the
analog V

IN

does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDCto5VDCinput voltage range will

therefore require a minimum supply voltage of 4.950 V

DC

over temperature variations, initial tolerance and loading.

Note 6: Typicals are at 25

§

C and represent most likely parametric norm.

Note 7: Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: Design Limits are guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.

Note 9: Channel leakage current is measured after the channel selection.

Note 10: 1 count

e

V

REF

/256.

Note 11: Human body model; 100 pF discharged through a 1.5 kX resistor.

Test Circuits

Leakage Current

TL/H/9287– 3

D0 Except ‘‘TRI-STATE’’

TL/H/9287– 4

t

TRI

‘‘TRI-STATE’’

TL/H/9287– 5

Timing Diagrams

D0 ‘‘TRI-STATE’’ Rise & Fall Times

TL/H/9287– 6

4