NSC ADC08161CIN, ADC08161BIWMX, ADC08161BIWM, ADC08161BIN Datasheet

ADC08161 500 ns A/D Converter with S/H Function and

2.5V Bandgap Reference

General Description

Using a patented multi-step A/D conversion technique, the 8-bit ADC08161 CMOS A/D converter offers 500 ns conversion time, internal sample-and-hold (S/H), a 2.5V bandgap reference, and dissipates only 100 mW of power. The ADC08161 performs an 8-bit conversion with a 2-bit voltage estimator that generates the 2 MSBs and two low-resolution (3-bit) flashes that generate the 6 LBSs.

Input signals are tracked and held by the input sampling circuitry, eliminating the need for an external sample-and-hold. TheADC08161 can perform accurate conversions of full-scale input signals at frequencies from DC to typically more than 300 kHz (full power bandwidth) without the need of an external sample-and-hold (S/H).

For ease of interface to microprocessors, this part has been designed to appear as a memory location or I/O port without the need for external interfacing logic.

Key Specifications

n Resolution 8 Bits n Conversion time (t

CONV

) 560 ns max (WR-RD Mode)

n Full power bandwidth 300 kHz (typ) n Throughput rate 1.5 MHz min n Power dissipation 100 mW max n Total unadjusted error

⁄2LSB and±1 LSB max

Features

n No external clock required n Analog input voltage range from GND to V

n 2.5V bandgap reference

Applications

n Mobile telecommunications n Hard-disk drives n Instrumentation n High-speed data acquisition systems

Block Diagram

DS011149-1

June 1999

ADC08161 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference

Connection Diagram

Ordering Information

Industrial (−40˚C ≤ TA≤ 85˚C) Package

ADC08161CIWM M20B

Pin Description

This is the analog input. The input range is GND–50 mV ≤ V

INPUT

≤ V++50mV.

DB0–DB7 TRI-STATE data outputs—bit 0 (LSB)

through bit 7 (MSB).

WR /RDY

WR-RD Mode (Logic high applied to MODE pin)

WR: With CS low, the conversion is started on the rising edge of WR. The digital result will be strobed into the output latch at the end of conversion (

Figures 2,

3, 4

RD Mode (Logic low applied to MODE pin)

RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling edge of CS and returns high at the end of conversion.

MODE Mode: Mode (RD or WR-RD ) selection

input– This pin is pulled to a logic low through an internal 50 µA current sink when left unconnected.

RD Mode is selected if the MODE pin is left unconnected or externally forced low. Acomplete conversion is accomplished by pulling RD low until output data appears.

WR-RD Mode is selected when a high is applied to the MODE pin. A conversion starts with the WR signal’s rising edge and then using RD to access the data.

RD WR-RD Mode (logic high on the MODE

pin) This is the active low Read input. With a

logic low applied to the CS pin, the TRI-STATE data outputs (DB0–DB7) will be activated when RD goes low (

Figures

2, 3, 4

RD Mode (logic low on the MODE pin) With CS low, a conversion starts on the

falling edge of RD. Output data appears on DB0–DB7 at the end of conversion (

Figures 1, 5

INT

This is an active low output that indicates that a conversion is complete and the data is in the output latch. INT is reset by the rising edge of RD.

GND This is the power supply ground pin. The

ground pin should be connected to a “clean” ground reference point.

REF−,VREF+

These are the reference voltage inputs. They may be placed at any voltage between GND − 50 mV and V

+50mV,but

REF+

must be greater than V

REF−

. Ideally,

an input voltage equal to V

REF−

produces an output code of 0, and an input voltage greater than V

REF+

− 1.5 LSB produces an

output code of 255. For the ADC08161 an input voltage that

exceeds V

by more than 100 mV or is below GND by more than 100 mV will create conversion errors.

This is the active low Chip Select input. A logic low signal applied to this input pin enables the RD and WR inputs. Internally, the CS signal is ORed with RD and WR signals.

OFL

Overflow Output. If the analog input is higher than V

REF+

, OFL will be low at the end of conversion. It can be used when cascading two ADC08161s to achieve higher resolution (9 bits). This output is always active and does not go into TRI-STATE as DB0–DB7 do. When OFL is set, all data outputs remain high when the ADC08061’s output data is read.

Positive power supply voltage input. Nominal operating supply voltage is +5V. The supply pin should be bypassed with a 10 µF bead tantalum in parallel with a 0.1 ceramic capacitor. Lead length should be as short as possible.

REFOUT

The internal bandgap reference’s 2.5V output is available on this pin. Use a 220 µF bypass capacitor between this pin and analog ground.

Wide-Body Small-Outline Package

DS011149-14

See NS Package Number M20B

ADC08161

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V

)6V

Logic Control Inputs −0.3V to V

+ 0.3V

Voltage at Other Inputs and Outputs −0.3V to V

+ 0.3V Input Current at Any Pin (Note 3) 5 mA Package Input Current (Note 3) 20 mA

Power Dissipation (Note 4) 875 mW Lead Temperature (Note 5)

(Vapor Phase, 60 sec.) +215˚C

(Infrared, 15 sec.) +220˚C Storage Temperature −65˚C to +150˚C ESD Susceptibility (Note 6) 750V

Operating Ratings(Notes 1, 2)

Temperature Range T

MIN

≤ TA≤ T

MAX

ADC08161CIWM −40˚C ≤ TA≤ 85˚C Supply Voltage, (V

) 4.5V to 5.5V

Converter Characteristics

The following specifications apply for RD Mode, V+= 5V, V

REF+

= 5V, and V

REF−

= GND unless otherwise specified. Boldface

limits apply for TA=TJ=T

MIN

to T

MAX

; all other limits TA=TJ= 25˚C.

Symbol Parameter Conditions Typical Limits Units

(Note 7) (Note 8) (Limit)

INL Integral Non Linearity V

REF

=5V

1 LSB (max)

TUE Total Unadjusted Error (Note 9) V

REF

=5V

1 LSB (max)

INL Integral Non Linearity V

REF

= 2.5V

1 LSB (max)

TUE Total Unadjusted Error V

REF

= 2.5V

1 LSB (max)

Missing Codes V

REF

=5V 0 Bits (max)

REF

= 2.5V 0 Bits (max)

Reference Input Resistance 700 500 Ω (min)

700 1250 Ω (max)

REF+

Positive Reference Input Voltage V

REF−

V (min)

V (max)

REF−

Negative Reference GND V (min) Input Voltage V

REF+

V (max)

Analog (Note 10) GND − 0.1 V (min) Input Voltage V

+ 0.1 V (max)

On-Channel Input Current On Channel Input = 5V,

Off Channel Input = 0V −0.4 −20 µA (max) (Note 11) On Channel Input = 0V, Off Channel Input = 5V −0.4 −20 µA (max) (Note 11)

PSS Power Supply Sensitivity V

=5V±5%,

REF

= 4.75V

1/16

⁄

LSB (max)

All Codes Tested

Effective Bits V

= 4.85 V

p-p

7.8 Bits

=20Hzto20kHz

Full-Power Bandwidth V

= 4.85 V

p-p

300 kHz

THD Total Harmonic Distortion V

= 4.85 V

p-p

0.5 %

=20Hzto20kHz

S/N Signal-to-Noise Ratio V

= 4.85 V

p-p

50 dB

=20Hzto20kHz

IMD Intermodulation Distortion V

= 4.85 V

p-p

50 dB

=20Hzto20kHz

VIN

Analog Input Capacitance 25 pF

ADC08161

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AC Electrical Characteristics

The following specifications apply for V+= 5V, tr=tf= 10 ns, V

REF+

= 5V, V

REF−

= 0V unless otherwise specified. Boldface

limits apply for T

A=TJ=TMIN

to T

MAX

; all other limits TA=TJ= 25˚C.

Symbol Parameter Conditions

Typical

(Note 7)

Limit

(Note 8)

Units

(Limit)

Write Time Mode Pin to V

100 100 ns (min)

(

Figures 2, 3, 4

)

Read Time (Time from Rising Edge Mode Pin to V+,(

Figure 2

) 350 350 ns (min)

of WR to Falling Edge of RD )

RDW

RD Width Mode Pin to GND (

Figure 5

) 200 250 ns (min)

400 400 ns (max)

CONV

WR -RD Mode Conversion Time Mode Pin to V+,(

Figure 2

) 500 560 ns (max)

WR+tRD+tACC1

)

CRD

RD Mode Conversion Time Mode Pin to GND, (

Figure 1

) 655 900 ns (max)

ACCO

Access Time (Delay from Falling CL≤ 100 pF, Mode Pin to GND 640 900 ns (max) Edge of RD to Output Valid)

(

Figure 1

)

ACC1

Access Time (Delay from CL≤ 10 pF 45 ns Falling Edge of RD

CL= 100 pF 50 110 ns (max)

to Output Valid) Mode Pin to V

,tRD≤ t

INTL

(

Figure 2

)

ACC2

Access Time (Delay from CL≤ 10 pF 25 ns Falling Edge of RD

CL= 100 pF 30 55 ns (max)

to Output Valid) t

INTL

(

Figures 3, 5

)

1H,t0H

TRI-STATE Control RL=3kΩ,CL=10pF (Delay from Rising Edge (

Figures 1, 2, 3, 4, 5

)3060 ns (max)

of RD to HI-Z State)

INTL

Delay from Rising Edge of Mode Pin = V+,CL= 50 pF 520 690 ns (max) WR to Falling Edge of INT

(

Figures 3, 4

)

INTH

Delay from Rising Edge of CL= 50 pF, 50 95 ns (max) RD to Rising Edge of INT

(

Figures 1, 2, 3, 5

)

INTH

Delay from Rising Edge of CL= 50 pF, (

Figure 4

)4595 ns (max)

WR to Rising Edge of INT

RDY

Delay from CS to RDY Mode Pin = 0V, CL= 50 pF, 25 45 ns (max)

=3kΩ,(

Figure 1

)

Delay from INT RL=3kΩ,CL= 100 pF 0 15 ns (max) to Output Valid (

Figure 4

)

Delay from RD to INT Mode Pin = V+,tRD≤ t

INTL

60 115 ns (max)

(

Figure 2

)

Time between End of RD (

Figures 1, 2, 3, 4, 5

)5050 ns (min)

and Start of New Conversion

CSS

CS Setup Time (

Figures 1, 2, 3, 4, 5

)00ns (max)

CSH

CS Hold Time (

Figures 1, 2, 3, 4, 5

)00ns (max)

DC Electrical Characteristics

The following specifications apply for V+= 5V unless otherwise specified. Boldface limits apply for TA=TJ=T

MIN

to T

MAX

;

all other limits T

A=TJ

= 25˚C.

Symbol Parameter Conditions

Typical

(Note 7)

Limit

(Note 8)

Units

(Limit)

Logic “1” Input Voltage V+= 5.5 V

CS, WR, RD, A0, A1, A2 Pins

2.0 V (min)

Mode Pin 3.5

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DC Electrical Characteristics (Continued)

The following specifications apply for V+= 5V unless otherwise specified. Boldface limits apply for TA=TJ=T

MIN

to T

MAX

;

all other limits T

A=TJ

= 25˚C.

Symbol Parameter Conditions

Typical

(Note 7)

Limit

(Note 8)

Units

(Limit)

Logic “0” Input Voltage V+= 4.5V

CS, WR, RD, A0, A1, A2 Pins

0.8 V (max)

Mode Pin 1.5

Logic “1” Input Current VH=5V

CS, RD, A0, A, A2 Pins

0.005 1

WR Pin

0.1 3 µA (max)

Mode Pin 50 200

Logic “0” Input Current VL=0V

CS, RD, WR, A0, A1, A2 Mode Pins −0.005 −2 µA (max)

Logic “1” Output Voltage V+= 4.75V

OUT

= −360 µA 2.4 V (min) DB0–DB7, OFL, INT I

OUT

= −10 µA 4.5 V (min) DB0–DB7, OFL, INT

Logic “0” Output Voltage V+= 4.75V

OUT

= 1.6 mA 0.4 V (max) DB0–DB7, OFL, INT, RDY

TRI-STATE Output Current V

OUT

= 5.0V 0.1 3 µA (max) DB0–DB7, RDY V

OUT

= 0V −0.1 −3 µA (max) DB0–DB7, RDY

SOURCE

Output Source Current V

OUT

= 0V −26 −6 mA (min) DB0–DB7, OFL, INT

SINK

Output Sink Current V

OUT

=5V 24 7 mA (min) DB0–DB7, OFL, INT, RDY

Supply Current CS = WR = RD = 0 11.5 20 mA (max)

OUT

Logic Output Capacitance 5 pF

Logic Input Capacitance 5 pF

Bandgap Reference Electrical Characteristics

The following specifications apply for V+= 5V unless otherwise specified. Boldface limits apply for T

MIN

to T

MAX

; all other

limits T

A=TJ

= 25˚C.

Symbol Parameter Conditions Typical Limits Units

(Note 7) (Note 8) (Limit)

REFOUT

Internal Reference Output Voltage 2.5±2.0% V (max)

∆V

REF

/∆T Internal Reference Temperature 40 ppm/˚C

Coefficient

∆V

REF

/∆ILInternal Reference Load Sourcing (0 ≤ IL≤ +10 mA) 0.01 0.1 %/mA (max)

Regulation Line Regulation 4.75V ≤ V

≤ 5.25V 0.5 6.0 mV (max)

Short Circuit Current V

REV

= 0V 35 mA (max)

∆V

REF/∆t

Long Term Stability 200 ppm/kHr Start-Up Time V

:0V→5V, CL= 220 µF 40 ms

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications do not apply when operating the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

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