NSC 5962-9450202QXA Datasheet
54ABT16646
16-Bit Transceivers and Registers with TRI-STATE
®
Outputs
General Description
The ’ABT16646 consists of bus transceiver circuits with
TRI-STATE, D-type flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from the input
bus or from the internal registers. Data on the A or B bus will
be clocked into the registers as the appropriate clock pin
goes to a high logic level. Control OE and direction pins are
provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may
be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus will
receive data when the enable control OE is Active LOW. In
the isolation mode (control OE HIGH), A data may be stored
in the B register and/or B data may be stored in the A register.
Features
n Independent registers for A and B buses
n Multiplexed real-time and stored data
n A and B output sink capability of 48 mA, source
capability of 24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Nondestructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9450202
Ordering Code
Military Package Package Description
Number
54ABT16646W-QML WA56A 56-Lead Cerpack
Logic Symbol
Pin Names Description
A
0–A15
Data Register A Inputs/
TRI-STATE Outputs
B
0–B15
Data Register B Inputs/
TRI-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OE
n
Output Enable Input
DIR Direction Control Input
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS100226-1
July 1998
54ABT16646 16-Bit Transceivers and Registers with TRI-STATE Outputs
54ABT16646
© 1998 National Semiconductor Corporation DS100226 www.national.com
1
PrintDate=1998/07/14 PrintTime=11:10:43 43606 ds100226 Rev. No. 1 cmserv
Proof 1
Connection Diagram
Pin Assignment for Cerpack
DS100226-2
Real Time Transfer
A-Bus to B-Bus
DS100226-3
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
DS100226-4
FIGURE 2.
Storage from
Bus to Register
DS100226-5
FIGURE 3.
Transfer from
Register to Bus
DS100226-6
FIGURE 4.
PrintDate=1998/07/14 PrintTime=11:10:43 43606 ds100226 Rev. No. 1 cmserv Proof 2
www.national.com 2
Function Table
Inputs Data I/O (Note 1) Output Operation Mode
OE
1
DIR1CPAB1CPBA1SAB1SBA1A
0–7
B
0–7
H X H or L H or L X X Isolation
H X N X X X Input Input Clock An Data into A Register
H X X N X X Clock Bn Data Into B Register
L H X X L X An to Bn — Real Time (Transparent Mode)
L H N X L X Input Output Clock An Data to A Register
L H H or L X H X A Register to Bn (Stored Mode)
L H N X H X Clock An Data into A Register and Output to Bn
L L X X X L Bn to An—Real Time (Transparent Mode)
L L X N X L Output Input Clock Bn Data into B Register
L L X H or L X H B Register to An (Stored Mode)
L L X N X H Clock Bn into B Register and Output to An
H=HIGH Voltage Level X=Immaterial
L=LOW Voltage Level N=LOW-to-HIGH Transition.
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at
the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and#2 control pins.
3 www.national.com
PrintDate=1998/07/14 PrintTime=11:10:43 43606 ds100226 Rev. No. 1 cmserv Proof 3
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