NSC 5962-9322001QSA, 5962-9322001QRA, 5962-9322001Q2A Datasheet

54ABT574
Octal D-Type Flip-Flop with TRI-STATE

General Description

The ’ABT574 is an octal flip-flop with a buffered common
Clock (CP) and a buffered common Output Enable (OE).The
information presented to the D inputs is stored in the
flip-flops on the LOW-to-HIGH Clock (CP) transition.

The device is functionally identical to the ’ABT374 except for
the pinouts.

Features

n Inputs and outputs on opposite sides of package

allowing easy interface with microprocessors

n Useful as input or output port for microprocessors
n Functionally identical to ’ABT374

Ordering Code

Military Package Number Package Description

54ABT574J/883 J20A 20-Lead Ceramic Dual-In-Line
54ABT574W/883 W20A 20-Lead Cerpack
54ABT574E/883 E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

n TRI-STATE outputs for bus-oriented applications
n Output sink capability of 48 mA, source capability of

24 mA

n Guaranteed multiple output switching specifications
n Output switching specified for both 50 pF and 250 pF

loads

n Guaranteed simultaneous switching, noise level and

dynamic threshold performance

n Guaranteed latchup protection
n High impedance glitch free bus loading during entire

power up and power down cycle

n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9322001

®

Outputs

54ABT574 Octal D-Type Flip-Flop with TRI-STATE Outputs

July 1998

Connection Diagrams

Pin Assignment for DIP and Flatpak

DS100208-1

FAST®and TRI-STATE®are registered trademarks of NationalSemiconductor Corporation.

Pin Assignment

for LCC

Pin Descriptions

Pin Description

Names

D

0–D7

CP Clock Pulse Input

OE

O

0–O7

Data Inputs

(Active Rising Edge)

TRI-STATE Output Enable

Input (Active LOW)

TRI-STATE Outputs

DS100208-2

© 1998 National Semiconductor Corporation DS100208 www.national.com

Functional Description

The ’ABT574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi­vidual D inputs that meet the setup and hold times require­ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
are in a high impedance state. Operation of the OE input
does not affect the state of the flip-flops.

Function Table

Inputs Internal Outputs Function

OE

CP D Q O

H H or L L NC Z Hold

Logic Diagram

Inputs Internal Outputs Function

OE

CP D Q O

H H or L H NC Z Hold

N

H
H
L
L

L L Z Load

N

H H Z Load

N

L L L Data Available

N

H H H Data Available
L H or L L NC NC No Change in Data
L H or L H NC NC No Change in Data

H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance

=

N

LOW-to-HIGH Transition

NC=No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.national.com 2

DS100208-3

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias

Ceramic −55˚C to +175˚C

Pin Potential to Ground Pin −0.5V to +7.0V

V

CC

Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output in

the Disabled or Power-Off State −0.5V to 5.5V
in the HIGH State −0.5V to V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

OL

Over Voltage Latchup (I/O) 10V

Recommended Operating
Conditions

Free Air Ambient Temperature

Military −55˚C to +125˚C

Supply Voltage

Military +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these

CC

conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Latchup Source Current −500 mA

DC Electrical Characteristics

Symbol Parameter ABT574 Units V

Min Typ Max

V

Input HIGH Voltage 2.0 V Recognized HIGH Signal

IH

V

Input LOW Voltage 0.8 V Recognized LOW Signal

IL

V

Input Clamp Diode Voltage −1.2 V Min I

CD

V

Output HIGH Voltage 54ABT 2.5 V Min I

OH

V

Output LOW Voltage 54ABT 0.55 V Min I

OL

I

Input HIGH Current 5 µA Max V

IH

I

Input HIGH Current Breakdown Test 7 µA Max V

BVI

I

Input LOW Current −5 µA Max V

IL

V

Input Leakage Test 4.75 V 0.0 I

ID

I

Output Leakage Current 50 µA 0 − 5.5V V

OZH

I

Output Leakage Current −50 µA 0 − 5.5V V

OZL

I

Output Short-Circuit Current −100 −275 mA Max V

OS

I

Output High Leakage Current 50 µA Max V

CEX

I

Bus Drainage Test 100 µA 0.0 V

ZZ

I

Power Supply Current 50 µA Max All Outputs HIGH

CCH

I

Power Supply Current 30 mA Max All Outputs LOW

CCL

I

Power Supply Current 50 µA Max OE=V

CCZ

I

Additional ICC/Input Outputs Enabled 2.5 mA V

CCT

Outputs TRI-STATE 2.5 mA Max Enable Input V
Outputs TRI-STATE 2.5 mA Data Input V

I

CCD

Dynamic I

CC

No Load mA/ Max Outputs Open, OE=GND,

(Note 4) 0.30 MHz One Bit Toggling (Note 3),

Note 3: For 8-bit toggling, I
Note 4: Guaranteed, but not tested.

CCD

<

0.8 mA/MHz.

54ABT 2.0 V Min I

5V

−5 V

CC

=

−18 mA

IN

=

−3 mA

OH

=

−24 mA

OH

=

48 mA

OL

=

2.7V (Note 4)

IN

=

V

IN

CC

=

7.0V

IN

=

0.5V (Note 4)

IN

=

0.0V

IN

=

1.9 µA

ID

All Other Pins Grounded

=

2.7V; OE=2.0V

OUT

=

0.5V; OE=2.0V

OUT

=

0.0V

OUT

=

V

OUT

=

5.5V; All Other GND

OUT

CC

All Others at VCCor GND

=

V

I

CC

All Others at V

50%Duty Cycle

Conditions

CC

− 2.1V
=

I

=

V

I

CC

V

CC

− 2.1V

CC

or GND

− 2.1V

3 www.national.com