NSC 5962-9321901QSA, 5962-9321901QRA, 5962-9321901Q2A Datasheet

54ABT573 Octal D-Type Latch with TRI-STATE

General Description

The ’ABT573 is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs.

This device is functionally identical to the ’ABT373 but has different pinouts.

Features

n Inputs and outputs on opposite sides of package allow

easy interface with microprocessors

n Useful as input or output port for microprocessors

Ordering Code

Military Package Package Description

Number

54ABT573J-QML J20A 20-Lead Ceramic Dual-In-Line 54ABT573W-QML W20A 20-Lead Cerpack 54ABT573E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

n Functionally identical to ’ABT373 n TRI-STATE outputs for bus interfacing n Output sink capability of 48 mA, source capability of

24 mA

n Output switching specified for both 50 pF and 250 pF

loads

n Guaranteed latchup protection n High impedance glitch-free bus loading during entire

power up and power down

n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9321901

®

Outputs

54ABT573 Octal D-Type Latch with TRI-STATE Outputs

July 1998

Connection Diagram

Pin Assignment

for DIP and Cerpack

DS100219-1

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Pin Assignment

for LCC

DS100219-39

Names

D

0–D7

LE Latch Enable Input (Active HIGH) OE

O

0–O7

Data Inputs

TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs

Description

Functional Description

The ’ABT573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D latches are transparent, i.e., a latch output will change state

inputs enters the latches. In this condition the

n

each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW,the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

Function Table

Inputs Outputs

OE

LE D O

LHH H LHL L LLX O HXX Z

=

H

HIGH Voltage Level L=LOW Voltage Level X=Immaterial

=

Value stored from previous clock cycle

O

0

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

DS100219-3

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Absolute Maximum Ratings (Note 1)

Storage Temperature −65˚C to +150˚C Ambient Temperature under Bias −55˚C to +125˚C Junction Temperature under Bias

Ceramic −55˚C to +175˚C

Pin Potential to

V

CC

Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Any Output

in the Disabled or

Power-Off State −0.5V to +5.5V

in the HIGH State −0.5V to V Current Applied to Output

in LOW State (Max) Twice the rated I

(mA)

OL

Over Voltage Latchup (I/O) 10V

Recommended Operating Conditions

Free Air Ambient Temperature

Military −55˚C to +125˚C

Supply Voltage

Military +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns Enable Input 20 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these

CC

conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Latchup Source Current −500 mA

DC Electrical Characteristics

Symbol Parameter ABT573 Units V

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IH

Input LOW Voltage 0.8 V Recognized LOW Signal

V

IL

Input Clamp Diode Voltage −1.2 V Min I

V

CD

Output HIGH Voltage 54ABT 2.5 V Min I

V

OH

Output LOW Voltage 54ABT 0.55 V Min I

V

OL

Input HIGH Current 5 µA Max V

I

IH

I

Input HIGH Current 7 µA Max V

BVI

Breakdown Test Input LOW Current −5 µA Max V

I

IL

Input Leakage Test 4.75 V 0.0 I

V

ID

Output Leakage Current 50 µA 0 − 5.5V V

I

OZH

I

Output Leakage Current −50 µA 0 − 5.5V V

OZL

I

Output Short-Circuit Current −100 −275 mA Max V

OS

Output High Leakage Current 50 µA Max V

I

CEX

I

Bus Drainage Test 100 µA 0.0 V

ZZ

Power Supply Current 50 µA Max All Outputs HIGH

I

CCH

Power Supply Current 30 mA Max All Outputs LOW

I

CCL

Power Supply Current 50 µA Max OE=V

I

CCZ

Additional ICC/Input Outputs Enabled 2.5 mA V

I

CCT

Outputs TRI-STATE 2.5 mA Max Enable Input V Outputs TRI-STATE 2.5 mA Data Input V

I

CCD

Dynamic I

CC

No Load mA/ Max Outputs Open

(Note 4) 0.12 MHz OE=GND, LE=V

Note 3: For 8 bits toggling, I Note 4: Guaranteed but not tested.

CCD

<

0.8 mA/MHz.

Min Typ Max

54ABT 2.0 I

5V

−5 V

CC

=

−18 mA

IN

=

−3 mA

OH

=

−24 mA

OH

=

48 mA

OL

=

2.7V (Note 4)

IN

=

V

IN

CC

=

7.0V

IN

=

0.5V (Note 4)

IN

=

0.0V

IN

=

1.9 µA

ID

All Other Pins Grounded

=

2.7V; OE=2.0V

OUT

=

0.5V; OE=2.0V

OUT

=

0.0V

OUT

=

V

OUT

CC

=

5.5V; All Others GND

OUT

CC

All Others at VCCor GND

=

− 2.1V

V

I

CC

I

All Others at V

One Bit Toggling, 50%Duty Cycle

Conditions

=

V

I

CC

=

− 2.1V

V

CC

or GND

CC

− 2.1V

(Note 3)

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DC Electrical Characteristics

Symbol Parameter Min Max Units V

V

OLP

V

OLV

Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.

Quiet Output Maximum Dynamic V Quiet Output Minimum Dynamic V

OL

0.9 V 5.0 T

-1.7 V 5.0 T

CC

=

C

L

=

A

=

A

Conditions

50 pF, R

25˚C (Note 5) 25˚C (Note 5)

AC Electrical Characteristics

Symbol Parameter 54ABT Units Fig.

=

−55˚C to +125˚C

T

A

=

V

4.5V to 5.5V

CC

=

C

50 pF

L

Min Max

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Propagation Delay 1.0 6.4 ns Dnto O

n

1.5 6.7 Propagation Delay 1.0 7.1 ns LE to O

n

1.5 7.5 Output Enable Time 0.8 6.5 ns

1.5 7.2 Output Disable Time 1.5 7.7 ns Time 1.0 7.0

Figure 4

Figure 6

AC Operating Requirements

Symbol Parameter 54ABT Units Fig.

=

−55˚C to +125˚C

T

A

=

V

4.5V to 5.5V

CC

=

C

50 pF

Min Max

t

(H) Set Time, HIGH 2.5

s

ts(L) or LOW Dnto LE 2.5 t

(H) Hold Time, HIGH 2.5

h

th(L) or LOW Dnto LE 2.5 t

(H) Pulse Width, 3.3

w

LE HIGH

L

ns

L

No.

=

500Ω

No.

Figure

7

Figure

7

Figure

5

Capacitance

Symbol Parameter Typ Units Conditions

(T

C

IN

C

(Note 6) Output Capacitance 9 pF V

OUT

Note 6: C

OUT

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Input Capacitance 5 pF V

is measured at frequency f=1 MHz per MIL-STD-883B, Method 3012.

A

CC CC

=

= =

25˚C)

0V

5.0V