NSC 5962-9318801QSA, 5962-9318801QRA, 5962-9318801Q2A Datasheet

54ABT240
Octal Buffer/Line Driver with TRI-STATE

®

Outputs

General Description

The ’ABT240 is an inverting octal buffer and line driver de­signed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which pro­vides improved PC board density.

Features

n Output sink capability of 48 mA, source capability of

24 mA

n Guaranteed latchup protection
n High impedance glitch free bus loading during entire

power up and power down cycle

n Nondestructive hot insertion capability
n Standard Microcircuit Drawing (SMD) —5962-9318801

Ordering Code

Military

Package

Number

Package Description

54ABT240J-QML J20A 20-Lead Ceramic Dual-In-Line
54ABT240W-QML W20A 20-Lead Cerpack
54ABT240E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Connection Diagrams

Pin Names Description

OE

1

,OE2TRI-STATE Output

Enable Inputs

I

0–I7

Inputs

O

0–O7

Outputs

TRI-STATE®is a registeredtrademark of National Semiconductor Corporation.

Pin Assignment

for DIP and Flatpak

DS100202-1

Pin Assignment

for LCC

DS100202-2

July 1998

54ABT240 Octal Buffer/Line Driver with TRI-STATE Outputs

© 1998 National Semiconductor Corporation DS100202 www.national.com

Truth Tables

Inputs Outputs

(Pins 12, 14, 16, 18)

OE

1

I

n

LL H
LH L
HX Z

Inputs Outputs

(Pins 3, 5, 7, 9)

OE

2

I

n

LL H
LH L
HX Z

H

=

HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias

Ceramic −55˚C to +175˚C

V

CC

Pin Potential to

Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disabled or

Power-Off State −0.5V to 5.5V

in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

DC Latchup Source Current

(Across Comm Operating
Range) −150 mA

Over Voltage Latchup (I/O) 10V

Recommended Operating
Conditions

Free Air Ambient Temperature

Military −55˚C to +125˚C

Supply Voltage

Military +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol Parameter ABT240 Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min I

IN

=

−18 mA

V

OH

Output HIGH Voltage 54ABT 2.5 V Min I

OH

=

−3 mA

54ABT 2.0 V Min I

OH

=

−24 mA

V

OL

Output LOW Voltage 54ABT 0.55 V Min I

OL

=

48 mA

I

IH

Input HIGH Current 5 µA Max V

IN

=

2.7V (Note 4)

5V

IN

=

V

CC

I

BVI

Input HIGH Current Breakdown Test 7 µA Max V

IN

=

7.0V

I

IL

Input LOW Current −5 µA Max V

IN

=

0.5V (Note 4)

−5 V

IN

=

0.0V

V

ID

Input Leakage Test 4.75 V 0.0 I

ID

=

1.9 µA

All Other Pins Grounded

I

OZH

Output Leakage Current 50 µA 0 − 5.5V V

OUT

=

2.7V; OE

n

=

2.0V

I

OZL

Output Leakage Current −50 µA 0 − 5.5V V

OUT

=

0.5V; OE

n

=

2.0V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

=

0.0V

I

CEX

Output High Leakage Current 50 µA Max V

OUT

=

V

CC

I

ZZ

Bus Drainage Test 100 µA 0.0 V

OUT

=

5.5V; All Others GND

I

CCH

Power Supply Current 50 µA Max All Outputs HIGH

I

CCL

Power Supply Current 30 mA Max All Outputs LOW

I

CCZ

Power Supply Current 50 µA Max OE

n

=

V

CC

;

All Others at VCCor Ground

I

CCT

Additional ICC/Input Outputs Enabled 1.5 mA Max V

I

=

V

CC

− 2.1V

Outputs TRI-STATE 1.5 mA Enable Input V

I

=

V

CC

− 2.1V

Outputs TRI-STATE 50 µA Data Input V

I

=

V

CC

− 2.1V

All Others at V

CC

or Ground

I

CCD

Dynamic I

CC

No Load mA/ Max Outputs Open

(Note 4) 0.1 MHz OE

n

=

GND, (Note 3)

One Bit Toggling, 50%Duty Cycle

Note 3: For 8 bits toggling, I

CCD

<

0.8 mA/MHz.

Note 4: Guaranteed, but not tested.

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