NSC 5962-9317402QXA Datasheet

54ABT16244
16-Bit Buffer/Line Driver with TRI-STATE

®

Outputs

General Description

The ’ABT16244 contains sixteen non-inverting buffers with
TRI-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble controlled. Individual
TRI-STATE controlinputscan be shorted together for 8-bit or
16-bit operation.

Features

n Separate control logic for each nibble
n 16-bit version of the ’ABT244
n Outputs sink capability of 48 mA, source capability of

24 mA

n Guaranteed output skew
n Guaranteed multiple output switching specifications
n Output switching specified for both 50 pF and 250 pF

loads

n Guaranteed simultaneous switching noise level and

dynamic threshold performance

n Guaranteed latchup protection
n High impedance glitch free bus loading during entire

power up and power down cycle

n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9317402

Ordering Code:

Military Package Package Description

Number

54ABT16244W-QML WA48A 48-Lead Cerpack

Logic Symbol

Pin Description

Pin Names Description

OE

n

Output Enable Inputs (Active Low)

I

0–I15

Inputs

O

0–O15

Outputs

Connection Diagram

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

DS100223-1

Pin Assignment for Cerpack

DS100223-2

July 1998

54ABT16244 16-Bit Buffer/Line Driver with TRI-STATE Outputs

© 1998 National Semiconductor Corporation DS100223 www.national.com

Functional Description

The ’ABT16244 contains sixteen non-inverting buffers with TRI-STATE outputs. The device is nibble (4 bits) controlled with each
nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.

Truth Tables

Inputs Outputs

OE

1

I0–I

3

O0–O

3

LL L
LH H
HX Z

Inputs Outputs

OE

3

I8–I

11

O8–O

11

LL L
LH H
HX Z

H

=

High Voltage Level
L=Low Voltage Level
X=Immaterial
Z=High Impedance

Inputs Outputs

OE

2

I4–I

7

O4–O

7

LL L
LH H

HX Z

Inputs Outputs

OE

4

I12–I

15

O12–O

15

LL L
LH H

HX Z

Logic Diagram

DS100223-3

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Absolute Maximum Ratings (Note 1)

Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias

Ceramic −55˚C to +175˚C

V

CC

Pin Potential to

Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disabled or

Power-off State −0.5V to 5.5V

in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

DC Latchup Source Current −500 mA

Over Voltage Latchup (I/O) 10V

Recommended Operating
Conditions

Free Air Ambient Temperature

Military −55˚C to +125˚C

Supply Voltage

Military +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol Parameter ABT16244 Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min I

IN

=

−18 mA

V

OH

Output HIGH Voltage 54ABT 2.5 V Min I

OH

=

−3 mA

54ABT 2.0 V Min I

OH

=

−24 mA

V

OL

Output LOW Voltage 54ABT 0.55 V Min I

OL

=

48 mA

I

IH

Input HIGH Current 5 µA Max V

IN

=

2.7V (Note 3)

5V

IN

=

V

CC

I

BVI

Input HIGH Current 7 µA Max V

IN

=

7.0V

Breakdown Test

I

IL

Input LOW Current −5 µA Max V

IN

=

0.5V (Note 3)

−5 V

IN

=

0.0V

V

ID

Input Leakage Test 4.75 V 0.0 I

ID

=

1.9 µA

All Other Pins Grounded

I

OZH

Output Leakage Current 50 µA 0 − 5.5V V

OUT

=

2.7V; OE

n

=

2.0V

I

OZL

Output Leakage Current −50 µA 0 − 5.5V V

OUT

=

0.5V; OE

n

=

2.0V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

=

0.0V

I

CEX

Output High Leakage Current 50 µA Max V

OUT

=

V

CC

I

ZZ

Bus Drainage Test 100 µA 0.0 V

OUT

=

5.5V

All Other Pins GND

I

CCH

Power Supply Current 2.0 mA Max All Outputs HIGH

I

CCL

Power Supply Current 60 mA Max All Outputs LOW

I

CCZ

Power Supply Current 2.0 mA Max OE

n

=

V

CC

All Others at VCCor GND

I

CCT

Additional ICC/Input Outputs Enabled 2.5 mA V

I

=

V

CC

− 2.1V

Outputs TRI-STATE 2.5 mA Max Enable Input V

I

=

V

CC

− 2.1V

Outputs TRI-STATE 50 µA Data Input V

I

=

V

CC

− 2.1V

All Others at V

CC

or GND

I

CCD

Dynamic I

CC

No Load mA/ Outputs Open, OE

n

=

GND

(Note 3) 0.1 MHz Max One Bit Toggling,

50%Duty Cycle

Note 3: Guaranteed but not tested.

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